1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 4 */ 5 6 #ifndef _UNIPRO_H_ 7 #define _UNIPRO_H_ 8 9 /* 10 * M-TX Configuration Attributes 11 */ 12 #define TX_HIBERN8TIME_CAPABILITY 0x000F 13 #define TX_HS_DEEMPHASIS_SETTING_CAP 0x0012 14 #define TX_HS_PRESHOOT_SETTING_CAP 0x0015 15 #define TX_MODE 0x0021 16 #define TX_HSRATE_SERIES 0x0022 17 #define TX_HSGEAR 0x0023 18 #define TX_PWMGEAR 0x0024 19 #define TX_AMPLITUDE 0x0025 20 #define TX_HS_SLEWRATE 0x0026 21 #define TX_SYNC_SOURCE 0x0027 22 #define TX_HS_SYNC_LENGTH 0x0028 23 #define TX_HS_PREPARE_LENGTH 0x0029 24 #define TX_LS_PREPARE_LENGTH 0x002A 25 #define TX_HIBERN8_CONTROL 0x002B 26 #define TX_LCC_ENABLE 0x002C 27 #define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D 28 #define TX_BYPASS_8B10B_ENABLE 0x002E 29 #define TX_DRIVER_POLARITY 0x002F 30 #define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030 31 #define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031 32 #define TX_LCC_SEQUENCER 0x0032 33 #define TX_MIN_ACTIVATETIME 0x0033 34 #define TX_PWM_G6_G7_SYNC_LENGTH 0x0034 35 #define TX_HS_DEEMPHASIS_SETTING 0x0037 36 #define TX_HS_PRESHOOT_SETTING 0x003B 37 #define TX_REFCLKFREQ 0x00EB 38 #define TX_CFGCLKFREQVAL 0x00EC 39 #define CFGEXTRATTR 0x00F0 40 #define DITHERCTRL2 0x00F1 41 42 /* 43 * M-RX Configuration Attributes 44 */ 45 #define RX_HS_G5_ADAPT_INITIAL_CAP 0x0074 46 #define RX_HS_G6_ADAPT_INITIAL_CAP 0x007B 47 #define RX_HS_G6_ADAPT_INITIAL_L0L1L2L3_CAP 0x007D 48 #define RX_HS_G1_SYNC_LENGTH_CAP 0x008B 49 #define RX_HS_G1_PREP_LENGTH_CAP 0x008C 50 #define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F 51 #define RX_HIBERN8TIME_CAPABILITY 0x0092 52 #define RX_HS_G2_SYNC_LENGTH_CAP 0x0094 53 #define RX_HS_G3_SYNC_LENGTH_CAP 0x0095 54 #define RX_HS_G2_PREP_LENGTH_CAP 0x0096 55 #define RX_HS_G3_PREP_LENGTH_CAP 0x0097 56 #define RX_ADV_GRANULARITY_CAP 0x0098 57 #define RX_HIBERN8TIME_CAP 0x0092 58 #define RX_ADV_HIBERN8TIME_CAP 0x0099 59 #define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A 60 #define RX_HS_G4_ADAPT_INITIAL_CAP 0x009F 61 #define RX_MODE 0x00A1 62 #define RX_HSRATE_SERIES 0x00A2 63 #define RX_HSGEAR 0x00A3 64 #define RX_PWMGEAR 0x00A4 65 #define RX_LS_TERMINATED_ENABLE 0x00A5 66 #define RX_HS_UNTERMINATED_ENABLE 0x00A6 67 #define RX_ENTER_HIBERN8 0x00A7 68 #define RX_BYPASS_8B10B_ENABLE 0x00A8 69 #define RX_TERMINATION_FORCE_ENABLE 0x00A9 70 #define RXCALCTRL 0x00B4 71 #define RXSQCTRL 0x00B5 72 #define CFGRXCDR8 0x00BA 73 #define CFGRXOVR8 0x00BD 74 #define CFGRXOVR6 0x00BF 75 #define RX_FOM 0x00C2 76 #define RXDIRECTCTRL2 0x00C7 77 #define CFGRXOVR4 0x00E9 78 #define RX_REFCLKFREQ 0x00EB 79 #define RX_CFGCLKFREQVAL 0x00EC 80 #define CFGWIDEINLN 0x00F0 81 #define RX_EYEMON_CAP 0x00F1 82 #define RX_EYEMON_TIMING_MAX_STEPS_CAP 0x00F2 83 #define RX_EYEMON_TIMING_MAX_OFFSET_CAP 0x00F3 84 #define RX_EYEMON_VOLTAGE_MAX_STEPS_CAP 0x00F4 85 #define RX_EYEMON_VOLTAGE_MAX_OFFSET_CAP 0x00F5 86 #define RX_EYEMON_ENABLE 0x00F6 87 #define RX_EYEMON_TIMING_STEPS 0x00F7 88 #define RX_EYEMON_VOLTAGE_STEPS 0x00F8 89 #define RX_EYEMON_TARGET_TEST_COUNT 0x00F9 90 #define RX_EYEMON_TESTED_COUNT 0x00FA 91 #define RX_EYEMON_ERROR_COUNT 0x00FB 92 #define RX_EYEMON_START 0x00FC 93 #define RX_EYEMON_EXTENDED_ERROR_COUNT 0x00FD 94 95 #define ENARXDIRECTCFG4 0x00F2 96 #define ENARXDIRECTCFG3 0x00F3 97 #define ENARXDIRECTCFG2 0x00F4 98 99 #define RX_EYEMON_NEGATIVE_STEP_BIT BIT(6) 100 #define RX_EYEMON_EXTENDED_VRANGE_BIT BIT(6) 101 102 #define is_mphy_tx_attr(attr) (attr < RX_MODE) 103 #define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1) 104 #define SYNC_LEN_FINE(x) ((x) & 0x3F) 105 #define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F)) 106 #define PREP_LEN(x) ((x) & 0xF) 107 108 #define RX_MIN_ACTIVATETIME_UNIT_US 100 109 #define HIBERN8TIME_UNIT_US 100 110 111 /* 112 * Common Block Attributes 113 */ 114 #define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B) 115 #define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF) 116 #define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD) 117 #define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6) 118 #define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA) 119 #define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0) 120 #define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1) 121 #define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3) 122 #define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8) 123 #define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB) 124 125 #define UNIPRO_CB_OFFSET(x) (0x8000 | x) 126 127 #define ADAPT_LENGTH_MASK 0x7F 128 #define ADAPT_RANGE_BIT BIT(7) 129 #define IS_ADAPT_RANGE_COARSE(x) ((x) & ADAPT_RANGE_BIT) 130 131 /* Adapt definitions */ 132 #define ADAPT_LENGTH_MAX 0x91 133 #define ADAPT_L0L3_LENGTH_MAX 0x90 134 #define ADAPT_L0L1L2L3_LENGTH_MAX 0x8C 135 #define TADAPT_FACTOR 650 136 #define TADAPT_L0L3_FACTOR (1 << 9) 137 #define TADAPT_L0L1L2L3_FACTOR (1 << 15) 138 139 /* 140 * PHY Adapter attributes 141 */ 142 #define PA_PHY_TYPE 0x1500 143 #define PA_AVAILTXDATALANES 0x1520 144 #define PA_MAXTXSPEEDFAST 0x1521 145 #define PA_MAXTXSPEEDSLOW 0x1522 146 #define PA_MAXRXSPEEDFAST 0x1541 147 #define PA_MAXRXSPEEDSLOW 0x1542 148 #define PA_TXLINKSTARTUPHS 0x1544 149 #define PA_AVAILRXDATALANES 0x1540 150 #define PA_MINRXTRAILINGCLOCKS 0x1543 151 #define PA_TXHSG1SYNCLENGTH 0x1552 152 #define PA_TXHSG2SYNCLENGTH 0x1554 153 #define PA_TXHSG3SYNCLENGTH 0x1556 154 #define PA_LOCAL_TX_LCC_ENABLE 0x155E 155 #define PA_ACTIVETXDATALANES 0x1560 156 #define PA_CONNECTEDTXDATALANES 0x1561 157 #define PA_TXFORCECLOCK 0x1562 158 #define PA_TXPWRMODE 0x1563 159 #define PA_TXTRAILINGCLOCKS 0x1564 160 #define PA_TXSPEEDFAST 0x1565 161 #define PA_TXSPEEDSLOW 0x1566 162 #define PA_TXPWRSTATUS 0x1567 163 #define PA_TXGEAR 0x1568 164 #define PA_TXTERMINATION 0x1569 165 #define PA_HSSERIES 0x156A 166 #define PA_LEGACYDPHYESCDL 0x1570 167 #define PA_PWRMODE 0x1571 168 #define PA_ACTIVERXDATALANES 0x1580 169 #define PA_CONNECTEDRXDATALANES 0x1581 170 #define PA_RXPWRSTATUS 0x1582 171 #define PA_RXGEAR 0x1583 172 #define PA_RXTERMINATION 0x1584 173 #define PA_MAXRXPWMGEAR 0x1586 174 #define PA_MAXRXHSGEAR 0x1587 175 #define PA_PACPREQTIMEOUT 0x1590 176 #define PA_PACPREQEOBTIMEOUT 0x1591 177 #define PA_REMOTEVERINFO 0x15A0 178 #define PA_LOGICALLANEMAP 0x15A1 179 #define PA_SLEEPNOCONFIGTIME 0x15A2 180 #define PA_STALLNOCONFIGTIME 0x15A3 181 #define PA_SAVECONFIGTIME 0x15A4 182 #define PA_RXHSUNTERMCAP 0x15A5 183 #define PA_RXLSTERMCAP 0x15A6 184 #define PA_HIBERN8TIME 0x15A7 185 #define PA_LOCALVERINFO 0x15A9 186 #define PA_GRANULARITY 0x15AA 187 #define PA_TACTIVATE 0x15A8 188 #define PA_PWRMODEUSERDATA0 0x15B0 189 #define PA_PWRMODEUSERDATA1 0x15B1 190 #define PA_PWRMODEUSERDATA2 0x15B2 191 #define PA_PWRMODEUSERDATA3 0x15B3 192 #define PA_PWRMODEUSERDATA4 0x15B4 193 #define PA_PWRMODEUSERDATA5 0x15B5 194 #define PA_PWRMODEUSERDATA6 0x15B6 195 #define PA_PWRMODEUSERDATA7 0x15B7 196 #define PA_PWRMODEUSERDATA8 0x15B8 197 #define PA_PWRMODEUSERDATA9 0x15B9 198 #define PA_PWRMODEUSERDATA10 0x15BA 199 #define PA_PWRMODEUSERDATA11 0x15BB 200 #define PA_PACPFRAMECOUNT 0x15C0 201 #define PA_PACPERRORCOUNT 0x15C1 202 #define PA_PHYTESTCONTROL 0x15C2 203 #define PA_TXHSG4SYNCLENGTH 0x15D0 204 #define PA_PEERRXHSG4ADAPTINITIAL 0x15D3 205 #define PA_TXHSADAPTTYPE 0x15D4 206 #define PA_TXHSG5SYNCLENGTH 0x15D6 207 #define PA_PEERRXHSG5ADAPTINITIAL 0x15D9 208 #define PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3 0x15DE 209 #define PA_PEERRXHSG6ADAPTINITIALL0L3 0x15DF 210 #define PA_PEERRXHSG6ADAPTINITIALL0L1L2L3 0x15E0 211 #define PA_TXEQG1SETTING 0x15E1 212 #define PA_TXEQG2SETTING 0x15E2 213 #define PA_TXEQG3SETTING 0x15E3 214 #define PA_TXEQG4SETTING 0x15E4 215 #define PA_TXEQG5SETTING 0x15E5 216 #define PA_TXEQG6SETTING 0x15E6 217 #define PA_TXEQTRSETTING 0x15E7 218 #define PA_PEERTXEQTRSETTING 0x15E8 219 #define PA_PRECODEEN 0x15E9 220 #define PA_EQTR_GEAR 0x15EA 221 #define PA_TXADAPTLENGTH_EQTR 0x15EB 222 223 /* Adapt type for PA_TXHSADAPTTYPE attribute */ 224 #define PA_REFRESH_ADAPT 0x00 225 #define PA_INITIAL_ADAPT 0x01 226 #define PA_NO_ADAPT 0x03 227 228 #define PA_TACTIVATE_TIME_UNIT_US 10 229 #define PA_HIBERN8_TIME_UNIT_US 100 230 231 /*Other attributes*/ 232 #define VS_POWERSTATE 0xD083 233 #define VS_MPHYCFGUPDT 0xD085 234 #define VS_DEBUGOMC 0xD09E 235 #define VS_MPHYDISABLE 0xD0C1 236 237 #define PA_GRANULARITY_MIN_VAL 1 238 #define PA_GRANULARITY_MAX_VAL 6 239 240 /* PHY Adapter Protocol Constants */ 241 #define PA_MAXDATALANES 4 242 243 /* 244 * TX EQTR's minimum TAdapt should not be less than 10us. 245 * This value is rounded up into the nearest Unit Intervals (UI) 246 */ 247 #define TX_EQTR_HS_G4_MIN_T_ADAPT 166400 248 #define TX_EQTR_HS_G5_MIN_T_ADAPT 332800 249 #define TX_EQTR_HS_G6_MIN_T_ADAPT 262144 250 251 #define TX_EQTR_HS_G4_ADAPT_DEFAULT 0x88 252 #define TX_EQTR_HS_G5_ADAPT_DEFAULT 0x89 253 #define TX_EQTR_HS_G6_ADAPT_DEFAULT 0x89 254 255 #define TX_EQTR_CAP_MASK 0x7F 256 257 #define TX_EQTR_ADAPT_LENGTH_L0L1L2L3_SHIFT 8 258 #define TX_EQTR_ADAPT_RESERVED 0xFF 259 260 #define TX_HS_NUM_PRESHOOT 8 261 #define TX_HS_NUM_DEEMPHASIS 8 262 #define TX_HS_PRESHOOT_SHIFT 4 263 #define TX_HS_DEEMPHASIS_SHIFT 4 264 #define TX_HS_PRESHOOT_OFFSET 0 265 #define TX_HS_DEEMPHASIS_OFFSET 16 266 267 #define TX_HS_PRESHOOT_LANE_SHIFT(lane) \ 268 (TX_HS_PRESHOOT_OFFSET + (lane) * TX_HS_PRESHOOT_SHIFT) 269 #define TX_HS_DEEMPHASIS_LANE_SHIFT(lane) \ 270 (TX_HS_DEEMPHASIS_OFFSET + (lane) * TX_HS_DEEMPHASIS_SHIFT) 271 272 #define TX_HS_PRESHOOT_BITS(lane, val) \ 273 ((val) << TX_HS_PRESHOOT_LANE_SHIFT(lane)) 274 #define TX_HS_DEEMPHASIS_BITS(lane, val) \ 275 ((val) << TX_HS_DEEMPHASIS_LANE_SHIFT(lane)) 276 277 #define RX_FOM_VALUE_MASK 0x7F 278 #define RX_FOM_PRECODING_EN_BIT BIT(7) 279 280 #define PRECODEEN_TX_OFFSET 0 281 #define PRECODEEN_RX_OFFSET 4 282 #define PRECODEEN_TX_BIT(lane) (1 << (PRECODEEN_TX_OFFSET + (lane))) 283 #define PRECODEEN_RX_BIT(lane) (1 << (PRECODEEN_RX_OFFSET + (lane))) 284 285 enum ufs_tx_eq_preset { 286 UFS_TX_EQ_PRESET_P0, 287 UFS_TX_EQ_PRESET_P1, 288 UFS_TX_EQ_PRESET_P2, 289 UFS_TX_EQ_PRESET_P3, 290 UFS_TX_EQ_PRESET_P4, 291 UFS_TX_EQ_PRESET_P5, 292 UFS_TX_EQ_PRESET_P6, 293 UFS_TX_EQ_PRESET_P7, 294 UFS_TX_EQ_PRESET_MAX, 295 }; 296 297 enum ufs_tx_hs_preshoot { 298 UFS_TX_HS_PRESHOOT_DB_0P0, 299 UFS_TX_HS_PRESHOOT_DB_0P4, 300 UFS_TX_HS_PRESHOOT_DB_0P8, 301 UFS_TX_HS_PRESHOOT_DB_1P2, 302 UFS_TX_HS_PRESHOOT_DB_1P6, 303 UFS_TX_HS_PRESHOOT_DB_2P5, 304 UFS_TX_HS_PRESHOOT_DB_3P5, 305 UFS_TX_HS_PRESHOOT_DB_4P7, 306 }; 307 308 enum ufs_tx_hs_deemphasis { 309 UFS_TX_HS_DEEMPHASIS_DB_0P0, 310 UFS_TX_HS_DEEMPHASIS_DB_0P8, 311 UFS_TX_HS_DEEMPHASIS_DB_1P6, 312 UFS_TX_HS_DEEMPHASIS_DB_2P5, 313 UFS_TX_HS_DEEMPHASIS_DB_3P5, 314 UFS_TX_HS_DEEMPHASIS_DB_4P7, 315 UFS_TX_HS_DEEMPHASIS_DB_6P0, 316 UFS_TX_HS_DEEMPHASIS_DB_7P6, 317 }; 318 319 enum ufs_eom_eye_mask { 320 UFS_EOM_EYE_MASK_M, 321 UFS_EOM_EYE_MASK_L, 322 UFS_EOM_EYE_MASK_U, 323 }; 324 325 #define DL_FC0ProtectionTimeOutVal_Default 8191 326 #define DL_TC0ReplayTimeOutVal_Default 65535 327 #define DL_AFC0ReqTimeOutVal_Default 32767 328 #define DL_FC1ProtectionTimeOutVal_Default 8191 329 #define DL_TC1ReplayTimeOutVal_Default 65535 330 #define DL_AFC1ReqTimeOutVal_Default 32767 331 332 #define DME_LocalFC0ProtectionTimeOutVal 0xD041 333 #define DME_LocalTC0ReplayTimeOutVal 0xD042 334 #define DME_LocalAFC0ReqTimeOutVal 0xD043 335 336 /* PA power modes */ 337 enum ufs_pa_pwr_mode { 338 FAST_MODE = 1, 339 SLOW_MODE = 2, 340 FASTAUTO_MODE = 4, 341 SLOWAUTO_MODE = 5, 342 UNCHANGED = 7, 343 }; 344 345 #define PWRMODE_MASK 0xF 346 #define PWRMODE_RX_OFFSET 4 347 348 /* PA TX/RX Frequency Series */ 349 enum ufs_hs_gear_rate { 350 PA_HS_MODE_A = 1, 351 PA_HS_MODE_B = 2, 352 }; 353 354 enum ufs_pwm_gear_tag { 355 UFS_PWM_DONT_CHANGE, /* Don't change Gear */ 356 UFS_PWM_G1, /* PWM Gear 1 (default for reset) */ 357 UFS_PWM_G2, /* PWM Gear 2 */ 358 UFS_PWM_G3, /* PWM Gear 3 */ 359 UFS_PWM_G4, /* PWM Gear 4 */ 360 UFS_PWM_G5, /* PWM Gear 5 */ 361 UFS_PWM_G6, /* PWM Gear 6 */ 362 UFS_PWM_G7, /* PWM Gear 7 */ 363 }; 364 365 enum ufs_hs_gear_tag { 366 UFS_HS_DONT_CHANGE, /* Don't change Gear */ 367 UFS_HS_G1, /* HS Gear 1 (default for reset) */ 368 UFS_HS_G2, /* HS Gear 2 */ 369 UFS_HS_G3, /* HS Gear 3 */ 370 UFS_HS_G4, /* HS Gear 4 */ 371 UFS_HS_G5, /* HS Gear 5 */ 372 UFS_HS_G6, /* HS Gear 6 */ 373 UFS_HS_GEAR_MAX = UFS_HS_G6, 374 }; 375 376 enum ufs_lanes { 377 UFS_LANE_DONT_CHANGE, /* Don't change Lane */ 378 UFS_LANE_1, /* Lane 1 (default for reset) */ 379 UFS_LANE_2, /* Lane 2 */ 380 }; 381 382 enum ufs_unipro_ver { 383 UFS_UNIPRO_VER_RESERVED = 0, 384 UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */ 385 UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */ 386 UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */ 387 UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */ 388 UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */ 389 UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */ 390 /* UniPro version field mask in PA_LOCALVERINFO */ 391 UFS_UNIPRO_VER_MASK = 0xF, 392 }; 393 394 /* 395 * Data Link Layer Attributes 396 */ 397 #define DL_TXPREEMPTIONCAP 0x2000 398 #define DL_TC0TXMAXSDUSIZE 0x2001 399 #define DL_TC0RXINITCREDITVAL 0x2002 400 #define DL_TC1TXMAXSDUSIZE 0x2003 401 #define DL_TC1RXINITCREDITVAL 0x2004 402 #define DL_TC0TXBUFFERSIZE 0x2005 403 #define DL_TC1TXBUFFERSIZE 0x2006 404 #define DL_TC0TXFCTHRESHOLD 0x2040 405 #define DL_FC0PROTTIMEOUTVAL 0x2041 406 #define DL_TC0REPLAYTIMEOUTVAL 0x2042 407 #define DL_AFC0REQTIMEOUTVAL 0x2043 408 #define DL_AFC0CREDITTHRESHOLD 0x2044 409 #define DL_TC0OUTACKTHRESHOLD 0x2045 410 #define DL_PEERTC0PRESENT 0x2046 411 #define DL_PEERTC0RXINITCREVAL 0x2047 412 #define DL_TC1TXFCTHRESHOLD 0x2060 413 #define DL_FC1PROTTIMEOUTVAL 0x2061 414 #define DL_TC1REPLAYTIMEOUTVAL 0x2062 415 #define DL_AFC1REQTIMEOUTVAL 0x2063 416 #define DL_AFC1CREDITTHRESHOLD 0x2064 417 #define DL_TC1OUTACKTHRESHOLD 0x2065 418 #define DL_PEERTC1PRESENT 0x2066 419 #define DL_PEERTC1RXINITCREVAL 0x2067 420 421 /* 422 * Network Layer Attributes 423 */ 424 #define N_DEVICEID 0x3000 425 #define N_DEVICEID_VALID 0x3001 426 #define N_TC0TXMAXSDUSIZE 0x3020 427 #define N_TC1TXMAXSDUSIZE 0x3021 428 429 /* 430 * Transport Layer Attributes 431 */ 432 #define T_NUMCPORTS 0x4000 433 #define T_NUMTESTFEATURES 0x4001 434 #define T_CONNECTIONSTATE 0x4020 435 #define T_PEERDEVICEID 0x4021 436 #define T_PEERCPORTID 0x4022 437 #define T_TRAFFICCLASS 0x4023 438 #define T_PROTOCOLID 0x4024 439 #define T_CPORTFLAGS 0x4025 440 #define T_TXTOKENVALUE 0x4026 441 #define T_RXTOKENVALUE 0x4027 442 #define T_LOCALBUFFERSPACE 0x4028 443 #define T_PEERBUFFERSPACE 0x4029 444 #define T_CREDITSTOSEND 0x402A 445 #define T_CPORTMODE 0x402B 446 #define T_TC0TXMAXSDUSIZE 0x4060 447 #define T_TC1TXMAXSDUSIZE 0x4061 448 449 /* CPort setting */ 450 #define E2EFC_ON (1 << 0) 451 #define E2EFC_OFF (0 << 0) 452 #define CSD_N_ON (0 << 1) 453 #define CSD_N_OFF (1 << 1) 454 #define CSV_N_ON (0 << 2) 455 #define CSV_N_OFF (1 << 2) 456 #define CPORT_DEF_FLAGS (CSV_N_OFF | CSD_N_OFF | E2EFC_OFF) 457 458 /* CPort connection state */ 459 enum { 460 CPORT_IDLE = 0, 461 CPORT_CONNECTED, 462 }; 463 464 #endif /* _UNIPRO_H_ */ 465