1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * 6 * Authors: 7 * Santosh Yaraganavi <santosh.sy@samsung.com> 8 * Vinayak Holikatti <h.vinayak@samsung.com> 9 */ 10 11 #ifndef _UFSHCI_H 12 #define _UFSHCI_H 13 14 #include <linux/types.h> 15 #include <ufs/ufs.h> 16 17 enum { 18 TASK_REQ_UPIU_SIZE_DWORDS = 8, 19 TASK_RSP_UPIU_SIZE_DWORDS = 8, 20 ALIGNED_UPIU_SIZE = 512, 21 }; 22 23 /* UFSHCI Registers */ 24 enum { 25 REG_CONTROLLER_CAPABILITIES = 0x00, 26 REG_MCQCAP = 0x04, 27 REG_UFS_VERSION = 0x08, 28 REG_CONTROLLER_DEV_ID = 0x10, 29 REG_CONTROLLER_PROD_ID = 0x14, 30 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, 31 REG_INTERRUPT_STATUS = 0x20, 32 REG_INTERRUPT_ENABLE = 0x24, 33 REG_CONTROLLER_STATUS = 0x30, 34 REG_CONTROLLER_ENABLE = 0x34, 35 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, 36 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, 37 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, 38 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, 39 REG_UIC_ERROR_CODE_DME = 0x48, 40 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, 41 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, 42 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, 43 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, 44 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, 45 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, 46 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, 47 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, 48 REG_UTP_TASK_REQ_DOOR_BELL = 0x78, 49 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, 50 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, 51 REG_UIC_COMMAND = 0x90, 52 REG_UIC_COMMAND_ARG_1 = 0x94, 53 REG_UIC_COMMAND_ARG_2 = 0x98, 54 REG_UIC_COMMAND_ARG_3 = 0x9C, 55 56 UFSHCI_REG_SPACE_SIZE = 0xA0, 57 58 REG_UFS_CCAP = 0x100, 59 REG_UFS_CRYPTOCAP = 0x104, 60 61 REG_UFS_MEM_CFG = 0x300, 62 REG_UFS_MCQ_CFG = 0x380, 63 REG_UFS_ESILBA = 0x384, 64 REG_UFS_ESIUBA = 0x388, 65 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, 66 }; 67 68 /* Controller capability masks */ 69 enum { 70 MASK_TRANSFER_REQUESTS_SLOTS_SDB = 0x0000001F, 71 MASK_TRANSFER_REQUESTS_SLOTS_MCQ = 0x000000FF, 72 MASK_NUMBER_OUTSTANDING_RTT = 0x0000FF00, 73 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, 74 MASK_EHSLUTRD_SUPPORTED = 0x00400000, 75 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, 76 MASK_64_ADDRESSING_SUPPORT = 0x01000000, 77 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, 78 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, 79 MASK_CRYPTO_SUPPORT = 0x10000000, 80 MASK_MCQ_SUPPORT = 0x40000000, 81 }; 82 83 /* MCQ capability mask */ 84 enum { 85 MASK_EXT_IID_SUPPORT = 0x00000400, 86 }; 87 88 enum { 89 REG_SQATTR = 0x0, 90 REG_SQLBA = 0x4, 91 REG_SQUBA = 0x8, 92 REG_SQDAO = 0xC, 93 REG_SQISAO = 0x10, 94 95 REG_CQATTR = 0x20, 96 REG_CQLBA = 0x24, 97 REG_CQUBA = 0x28, 98 REG_CQDAO = 0x2C, 99 REG_CQISAO = 0x30, 100 }; 101 102 enum { 103 REG_SQHP = 0x0, 104 REG_SQTP = 0x4, 105 REG_SQRTC = 0x8, 106 REG_SQCTI = 0xC, 107 REG_SQRTS = 0x10, 108 }; 109 110 enum { 111 REG_CQHP = 0x0, 112 REG_CQTP = 0x4, 113 }; 114 115 enum { 116 REG_CQIS = 0x0, 117 REG_CQIE = 0x4, 118 }; 119 120 enum { 121 SQ_START = 0x0, 122 SQ_STOP = 0x1, 123 SQ_ICU = 0x2, 124 }; 125 126 enum { 127 SQ_STS = 0x1, 128 SQ_CUS = 0x2, 129 }; 130 131 #define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4) 132 #define UFS_MASK(mask, offset) ((mask) << (offset)) 133 134 /* UFS Version 08h */ 135 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) 136 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) 137 138 #define UFSHCD_NUM_RESERVED 1 139 /* 140 * Controller UFSHCI version 141 * - 2.x and newer use the following scheme: 142 * major << 8 + minor << 4 143 * - 1.x has been converted to match this in 144 * ufshcd_get_ufs_version() 145 */ 146 static inline u32 ufshci_version(u32 major, u32 minor) 147 { 148 return (major << 8) + (minor << 4); 149 } 150 151 /* 152 * HCDDID - Host Controller Identification Descriptor 153 * - Device ID and Device Class 10h 154 */ 155 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0) 156 #define DEVICE_ID UFS_MASK(0xFF, 24) 157 158 /* 159 * HCPMID - Host Controller Identification Descriptor 160 * - Product/Manufacturer ID 14h 161 */ 162 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) 163 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) 164 165 /* AHIT - Auto-Hibernate Idle Timer */ 166 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0) 167 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10) 168 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10 169 #define UFSHCI_AHIBERN8_MAX (1023 * 100000) 170 171 /* 172 * IS - Interrupt Status - 20h 173 */ 174 #define UTP_TRANSFER_REQ_COMPL 0x1 175 #define UIC_DME_END_PT_RESET 0x2 176 #define UIC_ERROR 0x4 177 #define UIC_TEST_MODE 0x8 178 #define UIC_POWER_MODE 0x10 179 #define UIC_HIBERNATE_EXIT 0x20 180 #define UIC_HIBERNATE_ENTER 0x40 181 #define UIC_LINK_LOST 0x80 182 #define UIC_LINK_STARTUP 0x100 183 #define UTP_TASK_REQ_COMPL 0x200 184 #define UIC_COMMAND_COMPL 0x400 185 #define DEVICE_FATAL_ERROR 0x800 186 #define CONTROLLER_FATAL_ERROR 0x10000 187 #define SYSTEM_BUS_FATAL_ERROR 0x20000 188 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000 189 #define MCQ_CQ_EVENT_STATUS 0x100000 190 191 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\ 192 UIC_HIBERNATE_EXIT) 193 194 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\ 195 UIC_POWER_MODE) 196 197 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK) 198 199 #define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS) 200 201 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ 202 CONTROLLER_FATAL_ERROR |\ 203 SYSTEM_BUS_FATAL_ERROR |\ 204 CRYPTO_ENGINE_FATAL_ERROR |\ 205 UIC_LINK_LOST) 206 207 /* HCS - Host Controller Status 30h */ 208 #define DEVICE_PRESENT 0x1 209 #define UTP_TRANSFER_REQ_LIST_READY 0x2 210 #define UTP_TASK_REQ_LIST_READY 0x4 211 #define UIC_COMMAND_READY 0x8 212 #define HOST_ERROR_INDICATOR 0x10 213 #define DEVICE_ERROR_INDICATOR 0x20 214 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) 215 216 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ 217 UTP_TASK_REQ_LIST_READY |\ 218 UIC_COMMAND_READY) 219 220 enum { 221 PWR_OK = 0x0, 222 PWR_LOCAL = 0x01, 223 PWR_REMOTE = 0x02, 224 PWR_BUSY = 0x03, 225 PWR_ERROR_CAP = 0x04, 226 PWR_FATAL_ERROR = 0x05, 227 }; 228 229 /* HCE - Host Controller Enable 34h */ 230 #define CONTROLLER_ENABLE 0x1 231 #define CONTROLLER_DISABLE 0x0 232 #define CRYPTO_GENERAL_ENABLE 0x2 233 234 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ 235 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000 236 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F 237 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF 238 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10 239 240 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */ 241 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000 242 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF 243 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2 244 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4 245 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8 246 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20 247 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 248 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001 249 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002 250 251 /* UECN - Host UIC Error Code Network Layer 40h */ 252 #define UIC_NETWORK_LAYER_ERROR 0x80000000 253 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7 254 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1 255 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2 256 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4 257 258 /* UECT - Host UIC Error Code Transport Layer 44h */ 259 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000 260 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F 261 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1 262 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2 263 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4 264 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8 265 #define UIC_TRANSPORT_BAD_TC 0x10 266 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20 267 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40 268 269 /* UECDME - Host UIC Error Code DME 48h */ 270 #define UIC_DME_ERROR 0x80000000 271 #define UIC_DME_ERROR_CODE_MASK 0x1 272 273 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */ 274 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF 275 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8) 276 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000 277 #define INT_AGGR_STATUS_BIT 0x100000 278 #define INT_AGGR_PARAM_WRITE 0x1000000 279 #define INT_AGGR_ENABLE 0x80000000 280 281 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ 282 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 283 284 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ 285 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 286 287 /* REG_UFS_MEM_CFG - Global Config Registers 300h */ 288 #define MCQ_MODE_SELECT BIT(0) 289 290 /* CQISy - CQ y Interrupt Status Register */ 291 #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1 292 293 /* UICCMD - UIC Command */ 294 #define COMMAND_OPCODE_MASK 0xFF 295 #define GEN_SELECTOR_INDEX_MASK 0xFFFF 296 297 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) 298 #define RESET_LEVEL 0xFF 299 300 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) 301 #define CONFIG_RESULT_CODE_MASK 0xFF 302 #define GENERIC_ERROR_CODE_MASK 0xFF 303 304 /* GenSelectorIndex calculation macros for M-PHY attributes */ 305 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) 306 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) 307 308 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ 309 ((sel) & 0xFFFF)) 310 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) 311 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) 312 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) 313 314 /* Link Status*/ 315 enum link_status { 316 UFSHCD_LINK_IS_DOWN = 1, 317 UFSHCD_LINK_IS_UP = 2, 318 }; 319 320 /* UIC Commands */ 321 enum uic_cmd_dme { 322 UIC_CMD_DME_GET = 0x01, 323 UIC_CMD_DME_SET = 0x02, 324 UIC_CMD_DME_PEER_GET = 0x03, 325 UIC_CMD_DME_PEER_SET = 0x04, 326 UIC_CMD_DME_POWERON = 0x10, 327 UIC_CMD_DME_POWEROFF = 0x11, 328 UIC_CMD_DME_ENABLE = 0x12, 329 UIC_CMD_DME_RESET = 0x14, 330 UIC_CMD_DME_END_PT_RST = 0x15, 331 UIC_CMD_DME_LINK_STARTUP = 0x16, 332 UIC_CMD_DME_HIBER_ENTER = 0x17, 333 UIC_CMD_DME_HIBER_EXIT = 0x18, 334 UIC_CMD_DME_TEST_MODE = 0x1A, 335 }; 336 337 /* UIC Config result code / Generic error code */ 338 enum { 339 UIC_CMD_RESULT_SUCCESS = 0x00, 340 UIC_CMD_RESULT_INVALID_ATTR = 0x01, 341 UIC_CMD_RESULT_FAILURE = 0x01, 342 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, 343 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, 344 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, 345 UIC_CMD_RESULT_BAD_INDEX = 0x05, 346 UIC_CMD_RESULT_LOCKED_ATTR = 0x06, 347 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, 348 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, 349 UIC_CMD_RESULT_BUSY = 0x09, 350 UIC_CMD_RESULT_DME_FAILURE = 0x0A, 351 }; 352 353 #define MASK_UIC_COMMAND_RESULT 0xFF 354 355 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8) 356 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0) 357 358 /* Interrupt disable masks */ 359 enum { 360 /* Interrupt disable mask for UFSHCI v1.1 */ 361 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, 362 363 /* Interrupt disable mask for UFSHCI v2.1 */ 364 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, 365 }; 366 367 /* CCAP - Crypto Capability 100h */ 368 union ufs_crypto_capabilities { 369 __le32 reg_val; 370 struct { 371 u8 num_crypto_cap; 372 u8 config_count; 373 u8 reserved; 374 u8 config_array_ptr; 375 }; 376 }; 377 378 enum ufs_crypto_key_size { 379 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0, 380 UFS_CRYPTO_KEY_SIZE_128 = 0x1, 381 UFS_CRYPTO_KEY_SIZE_192 = 0x2, 382 UFS_CRYPTO_KEY_SIZE_256 = 0x3, 383 UFS_CRYPTO_KEY_SIZE_512 = 0x4, 384 }; 385 386 enum ufs_crypto_alg { 387 UFS_CRYPTO_ALG_AES_XTS = 0x0, 388 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, 389 UFS_CRYPTO_ALG_AES_ECB = 0x2, 390 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, 391 }; 392 393 /* x-CRYPTOCAP - Crypto Capability X */ 394 union ufs_crypto_cap_entry { 395 __le32 reg_val; 396 struct { 397 u8 algorithm_id; 398 u8 sdus_mask; /* Supported data unit size mask */ 399 u8 key_size; 400 u8 reserved; 401 }; 402 }; 403 404 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7) 405 #define UFS_CRYPTO_KEY_MAX_SIZE 64 406 /* x-CRYPTOCFG - Crypto Configuration X */ 407 union ufs_crypto_cfg_entry { 408 __le32 reg_val[32]; 409 struct { 410 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE]; 411 u8 data_unit_size; 412 u8 crypto_cap_idx; 413 u8 reserved_1; 414 u8 config_enable; 415 u8 reserved_multi_host; 416 u8 reserved_2; 417 u8 vsb[2]; 418 u8 reserved_3[56]; 419 }; 420 }; 421 422 /* 423 * Request Descriptor Definitions 424 */ 425 426 /* To accommodate UFS2.0 required Command type */ 427 enum { 428 UTP_CMD_TYPE_UFS_STORAGE = 0x1, 429 }; 430 431 enum { 432 UTP_SCSI_COMMAND = 0x00000000, 433 UTP_NATIVE_UFS_COMMAND = 0x10000000, 434 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, 435 }; 436 437 /* UTP Transfer Request Data Direction (DD) */ 438 enum utp_data_direction { 439 UTP_NO_DATA_TRANSFER = 0, 440 UTP_HOST_TO_DEVICE = 1, 441 UTP_DEVICE_TO_HOST = 2, 442 }; 443 444 /* Overall command status values */ 445 enum utp_ocs { 446 OCS_SUCCESS = 0x0, 447 OCS_INVALID_CMD_TABLE_ATTR = 0x1, 448 OCS_INVALID_PRDT_ATTR = 0x2, 449 OCS_MISMATCH_DATA_BUF_SIZE = 0x3, 450 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, 451 OCS_PEER_COMM_FAILURE = 0x5, 452 OCS_ABORTED = 0x6, 453 OCS_FATAL_ERROR = 0x7, 454 OCS_DEVICE_FATAL_ERROR = 0x8, 455 OCS_INVALID_CRYPTO_CONFIG = 0x9, 456 OCS_GENERAL_CRYPTO_ERROR = 0xA, 457 OCS_INVALID_COMMAND_STATUS = 0x0F, 458 }; 459 460 enum { 461 MASK_OCS = 0x0F, 462 }; 463 464 /* The maximum length of the data byte count field in the PRDT is 256KB */ 465 #define PRDT_DATA_BYTE_COUNT_MAX SZ_256K 466 /* The granularity of the data byte count field in the PRDT is 32-bit */ 467 #define PRDT_DATA_BYTE_COUNT_PAD 4 468 469 /** 470 * struct ufshcd_sg_entry - UFSHCI PRD Entry 471 * @addr: Physical address; DW-0 and DW-1. 472 * @reserved: Reserved for future use DW-2 473 * @size: size of physical segment DW-3 474 */ 475 struct ufshcd_sg_entry { 476 __le64 addr; 477 __le32 reserved; 478 __le32 size; 479 /* 480 * followed by variant-specific fields if 481 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined. 482 */ 483 }; 484 485 /** 486 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD) 487 * @command_upiu: Command UPIU Frame address 488 * @response_upiu: Response UPIU Frame address 489 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct 490 * ufshcd_sg_entry's. Variant-specific fields may be present after each. 491 */ 492 struct utp_transfer_cmd_desc { 493 u8 command_upiu[ALIGNED_UPIU_SIZE]; 494 u8 response_upiu[ALIGNED_UPIU_SIZE]; 495 u8 prd_table[]; 496 }; 497 498 /** 499 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD 500 */ 501 struct request_desc_header { 502 u8 cci; 503 u8 ehs_length; 504 #if defined(__BIG_ENDIAN) 505 u8 enable_crypto:1; 506 u8 reserved2:7; 507 508 u8 command_type:4; 509 u8 reserved1:1; 510 u8 data_direction:2; 511 u8 interrupt:1; 512 #elif defined(__LITTLE_ENDIAN) 513 u8 reserved2:7; 514 u8 enable_crypto:1; 515 516 u8 interrupt:1; 517 u8 data_direction:2; 518 u8 reserved1:1; 519 u8 command_type:4; 520 #else 521 #error 522 #endif 523 524 __le32 dunl; 525 u8 ocs; 526 u8 cds; 527 __le16 ldbc; 528 __le32 dunu; 529 }; 530 531 static_assert(sizeof(struct request_desc_header) == 16); 532 533 /** 534 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD) 535 * @header: UTRD header DW-0 to DW-3 536 * @command_desc_base_addr: UCD base address DW 4-5 537 * @response_upiu_length: response UPIU length DW-6 538 * @response_upiu_offset: response UPIU offset DW-6 539 * @prd_table_length: Physical region descriptor length DW-7 540 * @prd_table_offset: Physical region descriptor offset DW-7 541 */ 542 struct utp_transfer_req_desc { 543 544 /* DW 0-3 */ 545 struct request_desc_header header; 546 547 /* DW 4-5*/ 548 __le64 command_desc_base_addr; 549 550 /* DW 6 */ 551 __le16 response_upiu_length; 552 __le16 response_upiu_offset; 553 554 /* DW 7 */ 555 __le16 prd_table_length; 556 __le16 prd_table_offset; 557 }; 558 559 /* MCQ Completion Queue Entry */ 560 struct cq_entry { 561 /* DW 0-1 */ 562 __le64 command_desc_base_addr; 563 564 /* DW 2 */ 565 __le16 response_upiu_length; 566 __le16 response_upiu_offset; 567 568 /* DW 3 */ 569 __le16 prd_table_length; 570 __le16 prd_table_offset; 571 572 /* DW 4 */ 573 __le32 status; 574 575 /* DW 5-7 */ 576 __le32 reserved[3]; 577 }; 578 579 static_assert(sizeof(struct cq_entry) == 32); 580 581 /* 582 * UTMRD structure. 583 */ 584 struct utp_task_req_desc { 585 /* DW 0-3 */ 586 struct request_desc_header header; 587 588 /* DW 4-11 - Task request UPIU structure */ 589 struct { 590 struct utp_upiu_header req_header; 591 __be32 input_param1; 592 __be32 input_param2; 593 __be32 input_param3; 594 __be32 __reserved1[2]; 595 } upiu_req; 596 597 /* DW 12-19 - Task Management Response UPIU structure */ 598 struct { 599 struct utp_upiu_header rsp_header; 600 __be32 output_param1; 601 __be32 output_param2; 602 __be32 __reserved2[3]; 603 } upiu_rsp; 604 }; 605 606 #endif /* End of Header */ 607