1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * 6 * Authors: 7 * Santosh Yaraganavi <santosh.sy@samsung.com> 8 * Vinayak Holikatti <h.vinayak@samsung.com> 9 */ 10 11 #ifndef _UFSHCI_H 12 #define _UFSHCI_H 13 14 #include <linux/types.h> 15 #include <ufs/ufs.h> 16 17 enum { 18 TASK_REQ_UPIU_SIZE_DWORDS = 8, 19 TASK_RSP_UPIU_SIZE_DWORDS = 8, 20 ALIGNED_UPIU_SIZE = 512, 21 }; 22 23 /* UFSHCI Registers */ 24 enum { 25 REG_CONTROLLER_CAPABILITIES = 0x00, 26 REG_MCQCAP = 0x04, 27 REG_UFS_VERSION = 0x08, 28 REG_EXT_CONTROLLER_CAPABILITIES = 0x0C, 29 REG_CONTROLLER_PID = 0x10, 30 REG_CONTROLLER_MID = 0x14, 31 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, 32 REG_INTERRUPT_STATUS = 0x20, 33 REG_INTERRUPT_ENABLE = 0x24, 34 REG_CONTROLLER_STATUS = 0x30, 35 REG_CONTROLLER_ENABLE = 0x34, 36 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, 37 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, 38 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, 39 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, 40 REG_UIC_ERROR_CODE_DME = 0x48, 41 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, 42 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, 43 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, 44 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, 45 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, 46 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, 47 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, 48 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, 49 REG_UTP_TASK_REQ_DOOR_BELL = 0x78, 50 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, 51 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, 52 REG_UIC_COMMAND = 0x90, 53 REG_UIC_COMMAND_ARG_1 = 0x94, 54 REG_UIC_COMMAND_ARG_2 = 0x98, 55 REG_UIC_COMMAND_ARG_3 = 0x9C, 56 57 UFSHCI_REG_SPACE_SIZE = 0xA0, 58 59 REG_UFS_CCAP = 0x100, 60 REG_UFS_CRYPTOCAP = 0x104, 61 62 REG_UFS_MEM_CFG = 0x300, 63 REG_UFS_MCQ_CFG = 0x380, 64 REG_UFS_ESILBA = 0x384, 65 REG_UFS_ESIUBA = 0x388, 66 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, 67 }; 68 69 /* Controller capability masks */ 70 enum { 71 MASK_TRANSFER_REQUESTS_SLOTS_SDB = 0x0000001F, 72 MASK_TRANSFER_REQUESTS_SLOTS_MCQ = 0x000000FF, 73 MASK_NUMBER_OUTSTANDING_RTT = 0x0000FF00, 74 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, 75 MASK_EHSLUTRD_SUPPORTED = 0x00400000, 76 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, 77 MASK_64_ADDRESSING_SUPPORT = 0x01000000, 78 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, 79 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, 80 MASK_CRYPTO_SUPPORT = 0x10000000, 81 MASK_LSDB_SUPPORT = 0x20000000, 82 MASK_MCQ_SUPPORT = 0x40000000, 83 }; 84 85 enum { 86 /* Submission Queue (SQ) Configuration Registers */ 87 REG_SQATTR = 0x0, 88 REG_SQLBA = 0x4, 89 REG_SQUBA = 0x8, 90 REG_SQDAO = 0xC, 91 REG_SQISAO = 0x10, 92 93 /* Completion Queue (CQ) Configuration Registers */ 94 REG_CQATTR = 0x20, 95 REG_CQLBA = 0x24, 96 REG_CQUBA = 0x28, 97 REG_CQDAO = 0x2C, 98 REG_CQISAO = 0x30, 99 }; 100 101 /* Operation and Runtime Registers - Submission Queues and Completion Queues */ 102 enum { 103 REG_SQHP = 0x0, 104 REG_SQTP = 0x4, 105 REG_SQRTC = 0x8, 106 REG_SQCTI = 0xC, 107 REG_SQRTS = 0x10, 108 }; 109 110 enum { 111 REG_CQHP = 0x0, 112 REG_CQTP = 0x4, 113 }; 114 115 enum { 116 REG_CQIS = 0x0, 117 REG_CQIE = 0x4, 118 REG_MCQIACR = 0x8, 119 }; 120 121 enum { 122 SQ_START = 0x0, 123 SQ_STOP = 0x1, 124 SQ_ICU = 0x2, 125 }; 126 127 enum { 128 SQ_STS = 0x1, 129 SQ_CUS = 0x2, 130 }; 131 132 #define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4) 133 #define UFS_MASK(mask, offset) ((mask) << (offset)) 134 135 /* UFS Version 08h */ 136 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) 137 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) 138 139 #define UFSHCD_NUM_RESERVED 1 140 /* 141 * Controller UFSHCI version 142 * - 2.x and newer use the following scheme: 143 * major << 8 + minor << 4 144 * - 1.x has been converted to match this in 145 * ufshcd_get_ufs_version() 146 */ 147 static inline u32 ufshci_version(u32 major, u32 minor) 148 { 149 return (major << 8) + (minor << 4); 150 } 151 152 /* 153 * HCDDID - Host Controller Identification Descriptor 154 * - Device ID and Device Class 10h 155 */ 156 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0) 157 #define DEVICE_ID UFS_MASK(0xFF, 24) 158 159 /* 160 * HCPMID - Host Controller Identification Descriptor 161 * - Product/Manufacturer ID 14h 162 */ 163 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) 164 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) 165 166 /* AHIT - Auto-Hibernate Idle Timer */ 167 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0) 168 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10) 169 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10 170 #define UFSHCI_AHIBERN8_MAX (1023 * 100000) 171 172 /* 173 * IS - Interrupt Status - 20h 174 */ 175 #define UTP_TRANSFER_REQ_COMPL 0x1 176 #define UIC_DME_END_PT_RESET 0x2 177 #define UIC_ERROR 0x4 178 #define UIC_TEST_MODE 0x8 179 #define UIC_POWER_MODE 0x10 180 #define UIC_HIBERNATE_EXIT 0x20 181 #define UIC_HIBERNATE_ENTER 0x40 182 #define UIC_LINK_LOST 0x80 183 #define UIC_LINK_STARTUP 0x100 184 #define UTP_TASK_REQ_COMPL 0x200 185 #define UIC_COMMAND_COMPL 0x400 186 #define DEVICE_FATAL_ERROR 0x800 187 #define UTP_ERROR 0x1000 188 #define CONTROLLER_FATAL_ERROR 0x10000 189 #define SYSTEM_BUS_FATAL_ERROR 0x20000 190 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000 191 #define MCQ_CQ_EVENT_STATUS 0x100000 192 #define MCQ_IAG_EVENT_STATUS 0x200000 193 194 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\ 195 UIC_HIBERNATE_EXIT) 196 197 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\ 198 UIC_POWER_MODE) 199 200 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK) 201 202 #define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS) 203 204 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ 205 CONTROLLER_FATAL_ERROR |\ 206 SYSTEM_BUS_FATAL_ERROR |\ 207 CRYPTO_ENGINE_FATAL_ERROR |\ 208 UIC_LINK_LOST |\ 209 UTP_ERROR) 210 211 /* HCS - Host Controller Status 30h */ 212 #define DEVICE_PRESENT 0x1 213 #define UTP_TRANSFER_REQ_LIST_READY 0x2 214 #define UTP_TASK_REQ_LIST_READY 0x4 215 #define UIC_COMMAND_READY 0x8 216 #define HOST_ERROR_INDICATOR 0x10 217 #define DEVICE_ERROR_INDICATOR 0x20 218 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) 219 220 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ 221 UTP_TASK_REQ_LIST_READY |\ 222 UIC_COMMAND_READY) 223 224 enum { 225 PWR_OK = 0x0, 226 PWR_LOCAL = 0x01, 227 PWR_REMOTE = 0x02, 228 PWR_BUSY = 0x03, 229 PWR_ERROR_CAP = 0x04, 230 PWR_FATAL_ERROR = 0x05, 231 }; 232 233 /* HCE - Host Controller Enable 34h */ 234 #define CONTROLLER_ENABLE 0x1 235 #define CONTROLLER_DISABLE 0x0 236 #define CRYPTO_GENERAL_ENABLE 0x2 237 238 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ 239 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000 240 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F 241 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF 242 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10 243 244 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */ 245 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000 246 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF 247 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2 248 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4 249 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8 250 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20 251 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 252 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001 253 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002 254 255 /* UECN - Host UIC Error Code Network Layer 40h */ 256 #define UIC_NETWORK_LAYER_ERROR 0x80000000 257 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7 258 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1 259 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2 260 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4 261 262 /* UECT - Host UIC Error Code Transport Layer 44h */ 263 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000 264 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F 265 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1 266 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2 267 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4 268 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8 269 #define UIC_TRANSPORT_BAD_TC 0x10 270 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20 271 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40 272 273 /* UECDME - Host UIC Error Code DME 48h */ 274 #define UIC_DME_ERROR 0x80000000 275 #define UIC_DME_ERROR_CODE_MASK 0x1 276 #define UIC_DME_QOS_MASK 0xE 277 278 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */ 279 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF 280 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8) 281 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000 282 #define INT_AGGR_STATUS_BIT 0x100000 283 #define INT_AGGR_PARAM_WRITE 0x1000000 284 #define INT_AGGR_ENABLE 0x80000000 285 286 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ 287 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 288 289 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ 290 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 291 292 /* REG_UFS_MEM_CFG - Global Config Registers 300h */ 293 #define MCQ_MODE_SELECT BIT(0) 294 #define ESI_ENABLE BIT(1) 295 296 /* CQISy - CQ y Interrupt Status Register */ 297 #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1 298 299 /* UICCMD - UIC Command */ 300 #define COMMAND_OPCODE_MASK 0xFF 301 #define GEN_SELECTOR_INDEX_MASK 0xFFFF 302 303 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) 304 #define RESET_LEVEL 0xFF 305 306 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) 307 #define CONFIG_RESULT_CODE_MASK 0xFF 308 #define GENERIC_ERROR_CODE_MASK 0xFF 309 310 /* GenSelectorIndex calculation macros for M-PHY attributes */ 311 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) 312 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) 313 314 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ 315 ((sel) & 0xFFFF)) 316 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) 317 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) 318 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) 319 320 /* Link Status*/ 321 enum link_status { 322 UFSHCD_LINK_IS_DOWN = 1, 323 UFSHCD_LINK_IS_UP = 2, 324 }; 325 326 /* UIC Commands */ 327 enum uic_cmd_dme { 328 UIC_CMD_DME_GET = 0x01, 329 UIC_CMD_DME_SET = 0x02, 330 UIC_CMD_DME_PEER_GET = 0x03, 331 UIC_CMD_DME_PEER_SET = 0x04, 332 UIC_CMD_DME_POWERON = 0x10, 333 UIC_CMD_DME_POWEROFF = 0x11, 334 UIC_CMD_DME_ENABLE = 0x12, 335 UIC_CMD_DME_RESET = 0x14, 336 UIC_CMD_DME_END_PT_RST = 0x15, 337 UIC_CMD_DME_LINK_STARTUP = 0x16, 338 UIC_CMD_DME_HIBER_ENTER = 0x17, 339 UIC_CMD_DME_HIBER_EXIT = 0x18, 340 UIC_CMD_DME_TEST_MODE = 0x1A, 341 }; 342 343 /* UIC Config result code / Generic error code */ 344 enum { 345 UIC_CMD_RESULT_SUCCESS = 0x00, 346 UIC_CMD_RESULT_INVALID_ATTR = 0x01, 347 UIC_CMD_RESULT_FAILURE = 0x01, 348 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, 349 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, 350 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, 351 UIC_CMD_RESULT_BAD_INDEX = 0x05, 352 UIC_CMD_RESULT_LOCKED_ATTR = 0x06, 353 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, 354 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, 355 UIC_CMD_RESULT_BUSY = 0x09, 356 UIC_CMD_RESULT_DME_FAILURE = 0x0A, 357 }; 358 359 #define MASK_UIC_COMMAND_RESULT 0xFF 360 361 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8) 362 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0) 363 364 /* Interrupt disable masks */ 365 enum { 366 /* Interrupt disable mask for UFSHCI v1.1 */ 367 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, 368 369 /* Interrupt disable mask for UFSHCI v2.1 */ 370 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, 371 }; 372 373 /* CCAP - Crypto Capability 100h */ 374 union ufs_crypto_capabilities { 375 __le32 reg_val; 376 struct { 377 u8 num_crypto_cap; 378 u8 config_count; 379 u8 reserved; 380 u8 config_array_ptr; 381 }; 382 }; 383 384 enum ufs_crypto_key_size { 385 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0, 386 UFS_CRYPTO_KEY_SIZE_128 = 0x1, 387 UFS_CRYPTO_KEY_SIZE_192 = 0x2, 388 UFS_CRYPTO_KEY_SIZE_256 = 0x3, 389 UFS_CRYPTO_KEY_SIZE_512 = 0x4, 390 }; 391 392 enum ufs_crypto_alg { 393 UFS_CRYPTO_ALG_AES_XTS = 0x0, 394 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, 395 UFS_CRYPTO_ALG_AES_ECB = 0x2, 396 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, 397 }; 398 399 /* x-CRYPTOCAP - Crypto Capability X */ 400 union ufs_crypto_cap_entry { 401 __le32 reg_val; 402 struct { 403 u8 algorithm_id; 404 u8 sdus_mask; /* Supported data unit size mask */ 405 u8 key_size; 406 u8 reserved; 407 }; 408 }; 409 410 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7) 411 #define UFS_CRYPTO_KEY_MAX_SIZE 64 412 /* x-CRYPTOCFG - Crypto Configuration X */ 413 union ufs_crypto_cfg_entry { 414 __le32 reg_val[32]; 415 struct { 416 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE]; 417 u8 data_unit_size; 418 u8 crypto_cap_idx; 419 u8 reserved_1; 420 u8 config_enable; 421 u8 reserved_multi_host; 422 u8 reserved_2; 423 u8 vsb[2]; 424 u8 reserved_3[56]; 425 }; 426 }; 427 428 /* 429 * Request Descriptor Definitions 430 */ 431 432 /* To accommodate UFS2.0 required Command type */ 433 enum { 434 UTP_CMD_TYPE_UFS_STORAGE = 0x1, 435 }; 436 437 enum { 438 UTP_SCSI_COMMAND = 0x00000000, 439 UTP_NATIVE_UFS_COMMAND = 0x10000000, 440 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, 441 }; 442 443 /* UTP Transfer Request Data Direction (DD) */ 444 enum utp_data_direction { 445 UTP_NO_DATA_TRANSFER = 0, 446 UTP_HOST_TO_DEVICE = 1, 447 UTP_DEVICE_TO_HOST = 2, 448 }; 449 450 /* Overall command status values */ 451 enum utp_ocs { 452 OCS_SUCCESS = 0x0, 453 OCS_INVALID_CMD_TABLE_ATTR = 0x1, 454 OCS_INVALID_PRDT_ATTR = 0x2, 455 OCS_MISMATCH_DATA_BUF_SIZE = 0x3, 456 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, 457 OCS_PEER_COMM_FAILURE = 0x5, 458 OCS_ABORTED = 0x6, 459 OCS_FATAL_ERROR = 0x7, 460 OCS_DEVICE_FATAL_ERROR = 0x8, 461 OCS_INVALID_CRYPTO_CONFIG = 0x9, 462 OCS_GENERAL_CRYPTO_ERROR = 0xA, 463 OCS_INVALID_COMMAND_STATUS = 0x0F, 464 }; 465 466 enum { 467 MASK_OCS = 0x0F, 468 }; 469 470 /* The maximum length of the data byte count field in the PRDT is 256KB */ 471 #define PRDT_DATA_BYTE_COUNT_MAX SZ_256K 472 /* The granularity of the data byte count field in the PRDT is 32-bit */ 473 #define PRDT_DATA_BYTE_COUNT_PAD 4 474 475 /** 476 * struct ufshcd_sg_entry - UFSHCI PRD Entry 477 * @addr: Physical address; DW-0 and DW-1. 478 * @reserved: Reserved for future use DW-2 479 * @size: size of physical segment DW-3 480 */ 481 struct ufshcd_sg_entry { 482 __le64 addr; 483 __le32 reserved; 484 __le32 size; 485 /* 486 * followed by variant-specific fields if 487 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined. 488 */ 489 }; 490 491 /** 492 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD) 493 * @command_upiu: Command UPIU Frame address 494 * @response_upiu: Response UPIU Frame address 495 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct 496 * ufshcd_sg_entry's. Variant-specific fields may be present after each. 497 */ 498 struct utp_transfer_cmd_desc { 499 u8 command_upiu[ALIGNED_UPIU_SIZE]; 500 u8 response_upiu[ALIGNED_UPIU_SIZE]; 501 u8 prd_table[]; 502 }; 503 504 /** 505 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD 506 */ 507 struct request_desc_header { 508 u8 cci; 509 u8 ehs_length; 510 #if defined(__BIG_ENDIAN) 511 u8 enable_crypto:1; 512 u8 reserved2:7; 513 514 u8 command_type:4; 515 u8 reserved1:1; 516 u8 data_direction:2; 517 u8 interrupt:1; 518 #elif defined(__LITTLE_ENDIAN) 519 u8 reserved2:7; 520 u8 enable_crypto:1; 521 522 u8 interrupt:1; 523 u8 data_direction:2; 524 u8 reserved1:1; 525 u8 command_type:4; 526 #else 527 #error 528 #endif 529 530 __le32 dunl; 531 u8 ocs; 532 u8 cds; 533 __le16 ldbc; 534 __le32 dunu; 535 }; 536 537 static_assert(sizeof(struct request_desc_header) == 16); 538 539 /** 540 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD) 541 * @header: UTRD header DW-0 to DW-3 542 * @command_desc_base_addr: UCD base address DW 4-5 543 * @response_upiu_length: response UPIU length DW-6 544 * @response_upiu_offset: response UPIU offset DW-6 545 * @prd_table_length: Physical region descriptor length DW-7 546 * @prd_table_offset: Physical region descriptor offset DW-7 547 */ 548 struct utp_transfer_req_desc { 549 550 /* DW 0-3 */ 551 struct request_desc_header header; 552 553 /* DW 4-5*/ 554 __le64 command_desc_base_addr; 555 556 /* DW 6 */ 557 __le16 response_upiu_length; 558 __le16 response_upiu_offset; 559 560 /* DW 7 */ 561 __le16 prd_table_length; 562 __le16 prd_table_offset; 563 }; 564 565 /* MCQ Completion Queue Entry */ 566 struct cq_entry { 567 /* DW 0-1 */ 568 __le64 command_desc_base_addr; 569 570 /* DW 2 */ 571 __le16 response_upiu_length; 572 __le16 response_upiu_offset; 573 574 /* DW 3 */ 575 __le16 prd_table_length; 576 __le16 prd_table_offset; 577 578 /* DW 4 */ 579 u8 overall_status; 580 u8 extended_error_code; 581 __le16 reserved_1; 582 583 /* DW 5 */ 584 u8 task_tag; 585 u8 lun; 586 #if defined(__BIG_ENDIAN) 587 u8 ext_iid:4; 588 u8 iid:4; 589 #elif defined(__LITTLE_ENDIAN) 590 u8 iid:4; 591 u8 ext_iid:4; 592 #else 593 #error 594 #endif 595 u8 reserved_2; 596 597 /* DW 6-7 */ 598 __le32 reserved_3[2]; 599 }; 600 601 static_assert(sizeof(struct cq_entry) == 32); 602 603 /* 604 * UTMRD structure. 605 */ 606 struct utp_task_req_desc { 607 /* DW 0-3 */ 608 struct request_desc_header header; 609 610 /* DW 4-11 - Task request UPIU structure */ 611 struct { 612 struct utp_upiu_header req_header; 613 __be32 input_param1; 614 __be32 input_param2; 615 __be32 input_param3; 616 __be32 __reserved1[2]; 617 } upiu_req; 618 619 /* DW 12-19 - Task Management Response UPIU structure */ 620 struct { 621 struct utp_upiu_header rsp_header; 622 __be32 output_param1; 623 __be32 output_param2; 624 __be32 __reserved2[3]; 625 } upiu_rsp; 626 }; 627 628 #endif /* End of Header */ 629