1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #ifndef _UFSHCD_H 13 #define _UFSHCD_H 14 15 #include <linux/bitfield.h> 16 #include <linux/blk-crypto-profile.h> 17 #include <linux/blk-mq.h> 18 #include <linux/devfreq.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/dma-direction.h> 21 #include <scsi/scsi_device.h> 22 #include <ufs/unipro.h> 23 #include <ufs/ufs.h> 24 #include <ufs/ufs_quirks.h> 25 #include <ufs/ufshci.h> 26 27 #define UFSHCD "ufshcd" 28 29 struct ufs_hba; 30 31 enum dev_cmd_type { 32 DEV_CMD_TYPE_NOP = 0x0, 33 DEV_CMD_TYPE_QUERY = 0x1, 34 DEV_CMD_TYPE_RPMB = 0x2, 35 }; 36 37 enum ufs_event_type { 38 /* uic specific errors */ 39 UFS_EVT_PA_ERR = 0, 40 UFS_EVT_DL_ERR, 41 UFS_EVT_NL_ERR, 42 UFS_EVT_TL_ERR, 43 UFS_EVT_DME_ERR, 44 45 /* fatal errors */ 46 UFS_EVT_AUTO_HIBERN8_ERR, 47 UFS_EVT_FATAL_ERR, 48 UFS_EVT_LINK_STARTUP_FAIL, 49 UFS_EVT_RESUME_ERR, 50 UFS_EVT_SUSPEND_ERR, 51 UFS_EVT_WL_SUSP_ERR, 52 UFS_EVT_WL_RES_ERR, 53 54 /* abnormal events */ 55 UFS_EVT_DEV_RESET, 56 UFS_EVT_HOST_RESET, 57 UFS_EVT_ABORT, 58 59 UFS_EVT_CNT, 60 }; 61 62 /** 63 * struct uic_command - UIC command structure 64 * @command: UIC command 65 * @argument1: UIC command argument 1 66 * @argument2: UIC command argument 2 67 * @argument3: UIC command argument 3 68 * @cmd_active: Indicate if UIC command is outstanding 69 * @done: UIC command completion 70 */ 71 struct uic_command { 72 u32 command; 73 u32 argument1; 74 u32 argument2; 75 u32 argument3; 76 int cmd_active; 77 struct completion done; 78 }; 79 80 /* Used to differentiate the power management options */ 81 enum ufs_pm_op { 82 UFS_RUNTIME_PM, 83 UFS_SYSTEM_PM, 84 UFS_SHUTDOWN_PM, 85 }; 86 87 /* Host <-> Device UniPro Link state */ 88 enum uic_link_state { 89 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 90 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 91 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 92 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ 93 }; 94 95 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) 96 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ 97 UIC_LINK_ACTIVE_STATE) 98 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ 99 UIC_LINK_HIBERN8_STATE) 100 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ 101 UIC_LINK_BROKEN_STATE) 102 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) 103 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ 104 UIC_LINK_ACTIVE_STATE) 105 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ 106 UIC_LINK_HIBERN8_STATE) 107 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ 108 UIC_LINK_BROKEN_STATE) 109 110 #define ufshcd_set_ufs_dev_active(h) \ 111 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) 112 #define ufshcd_set_ufs_dev_sleep(h) \ 113 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) 114 #define ufshcd_set_ufs_dev_poweroff(h) \ 115 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) 116 #define ufshcd_set_ufs_dev_deepsleep(h) \ 117 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) 118 #define ufshcd_is_ufs_dev_active(h) \ 119 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) 120 #define ufshcd_is_ufs_dev_sleep(h) \ 121 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) 122 #define ufshcd_is_ufs_dev_poweroff(h) \ 123 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) 124 #define ufshcd_is_ufs_dev_deepsleep(h) \ 125 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) 126 127 /* 128 * UFS Power management levels. 129 * Each level is in increasing order of power savings, except DeepSleep 130 * which is lower than PowerDown with power on but not PowerDown with 131 * power off. 132 */ 133 enum ufs_pm_level { 134 UFS_PM_LVL_0, 135 UFS_PM_LVL_1, 136 UFS_PM_LVL_2, 137 UFS_PM_LVL_3, 138 UFS_PM_LVL_4, 139 UFS_PM_LVL_5, 140 UFS_PM_LVL_6, 141 UFS_PM_LVL_MAX 142 }; 143 144 struct ufs_pm_lvl_states { 145 enum ufs_dev_pwr_mode dev_state; 146 enum uic_link_state link_state; 147 }; 148 149 /** 150 * struct ufshcd_lrb - local reference block 151 * @utr_descriptor_ptr: UTRD address of the command 152 * @ucd_req_ptr: UCD address of the command 153 * @ucd_rsp_ptr: Response UPIU address for this command 154 * @ucd_prdt_ptr: PRDT address of the command 155 * @utrd_dma_addr: UTRD dma address for debug 156 * @ucd_prdt_dma_addr: PRDT dma address for debug 157 * @ucd_rsp_dma_addr: UPIU response dma address for debug 158 * @ucd_req_dma_addr: UPIU request dma address for debug 159 * @cmd: pointer to SCSI command 160 * @scsi_status: SCSI status of the command 161 * @command_type: SCSI, UFS, Query. 162 * @task_tag: Task tag of the command 163 * @lun: LUN of the command 164 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) 165 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) 166 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) 167 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) 168 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) 169 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) 170 * @data_unit_num: the data unit number for the first block for inline crypto 171 * @req_abort_skip: skip request abort task flag 172 */ 173 struct ufshcd_lrb { 174 struct utp_transfer_req_desc *utr_descriptor_ptr; 175 struct utp_upiu_req *ucd_req_ptr; 176 struct utp_upiu_rsp *ucd_rsp_ptr; 177 struct ufshcd_sg_entry *ucd_prdt_ptr; 178 179 dma_addr_t utrd_dma_addr; 180 dma_addr_t ucd_req_dma_addr; 181 dma_addr_t ucd_rsp_dma_addr; 182 dma_addr_t ucd_prdt_dma_addr; 183 184 struct scsi_cmnd *cmd; 185 int scsi_status; 186 187 int command_type; 188 int task_tag; 189 u8 lun; /* UPIU LUN id field is only 8-bit wide */ 190 bool intr_cmd; 191 ktime_t issue_time_stamp; 192 u64 issue_time_stamp_local_clock; 193 ktime_t compl_time_stamp; 194 u64 compl_time_stamp_local_clock; 195 #ifdef CONFIG_SCSI_UFS_CRYPTO 196 int crypto_key_slot; 197 u64 data_unit_num; 198 #endif 199 200 bool req_abort_skip; 201 }; 202 203 /** 204 * struct ufs_query - holds relevant data structures for query request 205 * @request: request upiu and function 206 * @descriptor: buffer for sending/receiving descriptor 207 * @response: response upiu and response 208 */ 209 struct ufs_query { 210 struct ufs_query_req request; 211 u8 *descriptor; 212 struct ufs_query_res response; 213 }; 214 215 /** 216 * struct ufs_dev_cmd - all assosiated fields with device management commands 217 * @type: device management command type - Query, NOP OUT 218 * @lock: lock to allow one command at a time 219 * @complete: internal commands completion 220 * @query: Device management query information 221 */ 222 struct ufs_dev_cmd { 223 enum dev_cmd_type type; 224 struct mutex lock; 225 struct completion *complete; 226 struct ufs_query query; 227 }; 228 229 /** 230 * struct ufs_clk_info - UFS clock related info 231 * @list: list headed by hba->clk_list_head 232 * @clk: clock node 233 * @name: clock name 234 * @max_freq: maximum frequency supported by the clock 235 * @min_freq: min frequency that can be used for clock scaling 236 * @curr_freq: indicates the current frequency that it is set to 237 * @keep_link_active: indicates that the clk should not be disabled if 238 * link is active 239 * @enabled: variable to check against multiple enable/disable 240 */ 241 struct ufs_clk_info { 242 struct list_head list; 243 struct clk *clk; 244 const char *name; 245 u32 max_freq; 246 u32 min_freq; 247 u32 curr_freq; 248 bool keep_link_active; 249 bool enabled; 250 }; 251 252 enum ufs_notify_change_status { 253 PRE_CHANGE, 254 POST_CHANGE, 255 }; 256 257 struct ufs_pa_layer_attr { 258 u32 gear_rx; 259 u32 gear_tx; 260 u32 lane_rx; 261 u32 lane_tx; 262 u32 pwr_rx; 263 u32 pwr_tx; 264 u32 hs_rate; 265 }; 266 267 struct ufs_pwr_mode_info { 268 bool is_valid; 269 struct ufs_pa_layer_attr info; 270 }; 271 272 /** 273 * struct ufs_hba_variant_ops - variant specific callbacks 274 * @name: variant name 275 * @init: called when the driver is initialized 276 * @exit: called to cleanup everything done in init 277 * @get_ufs_hci_version: called to get UFS HCI version 278 * @clk_scale_notify: notifies that clks are scaled up/down 279 * @setup_clocks: called before touching any of the controller registers 280 * @hce_enable_notify: called before and after HCE enable bit is set to allow 281 * variant specific Uni-Pro initialization. 282 * @link_startup_notify: called before and after Link startup is carried out 283 * to allow variant specific Uni-Pro initialization. 284 * @pwr_change_notify: called before and after a power mode change 285 * is carried out to allow vendor spesific capabilities 286 * to be set. 287 * @setup_xfer_req: called before any transfer request is issued 288 * to set some things 289 * @setup_task_mgmt: called before any task management request is issued 290 * to set some things 291 * @hibern8_notify: called around hibern8 enter/exit 292 * @apply_dev_quirks: called to apply device specific quirks 293 * @fixup_dev_quirks: called to modify device specific quirks 294 * @suspend: called during host controller PM callback 295 * @resume: called during host controller PM callback 296 * @dbg_register_dump: used to dump controller debug information 297 * @phy_initialization: used to initialize phys 298 * @device_reset: called to issue a reset pulse on the UFS device 299 * @config_scaling_param: called to configure clock scaling parameters 300 * @program_key: program or evict an inline encryption key 301 * @event_notify: called to notify important events 302 * @reinit_notify: called to notify reinit of UFSHCD during max gear switch 303 */ 304 struct ufs_hba_variant_ops { 305 const char *name; 306 int (*init)(struct ufs_hba *); 307 void (*exit)(struct ufs_hba *); 308 u32 (*get_ufs_hci_version)(struct ufs_hba *); 309 int (*clk_scale_notify)(struct ufs_hba *, bool, 310 enum ufs_notify_change_status); 311 int (*setup_clocks)(struct ufs_hba *, bool, 312 enum ufs_notify_change_status); 313 int (*hce_enable_notify)(struct ufs_hba *, 314 enum ufs_notify_change_status); 315 int (*link_startup_notify)(struct ufs_hba *, 316 enum ufs_notify_change_status); 317 int (*pwr_change_notify)(struct ufs_hba *, 318 enum ufs_notify_change_status status, 319 struct ufs_pa_layer_attr *, 320 struct ufs_pa_layer_attr *); 321 void (*setup_xfer_req)(struct ufs_hba *hba, int tag, 322 bool is_scsi_cmd); 323 void (*setup_task_mgmt)(struct ufs_hba *, int, u8); 324 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, 325 enum ufs_notify_change_status); 326 int (*apply_dev_quirks)(struct ufs_hba *hba); 327 void (*fixup_dev_quirks)(struct ufs_hba *hba); 328 int (*suspend)(struct ufs_hba *, enum ufs_pm_op, 329 enum ufs_notify_change_status); 330 int (*resume)(struct ufs_hba *, enum ufs_pm_op); 331 void (*dbg_register_dump)(struct ufs_hba *hba); 332 int (*phy_initialization)(struct ufs_hba *); 333 int (*device_reset)(struct ufs_hba *hba); 334 void (*config_scaling_param)(struct ufs_hba *hba, 335 struct devfreq_dev_profile *profile, 336 struct devfreq_simple_ondemand_data *data); 337 int (*program_key)(struct ufs_hba *hba, 338 const union ufs_crypto_cfg_entry *cfg, int slot); 339 void (*event_notify)(struct ufs_hba *hba, 340 enum ufs_event_type evt, void *data); 341 void (*reinit_notify)(struct ufs_hba *); 342 }; 343 344 /* clock gating state */ 345 enum clk_gating_state { 346 CLKS_OFF, 347 CLKS_ON, 348 REQ_CLKS_OFF, 349 REQ_CLKS_ON, 350 }; 351 352 /** 353 * struct ufs_clk_gating - UFS clock gating related info 354 * @gate_work: worker to turn off clocks after some delay as specified in 355 * delay_ms 356 * @ungate_work: worker to turn on clocks that will be used in case of 357 * interrupt context 358 * @state: the current clocks state 359 * @delay_ms: gating delay in ms 360 * @is_suspended: clk gating is suspended when set to 1 which can be used 361 * during suspend/resume 362 * @delay_attr: sysfs attribute to control delay_attr 363 * @enable_attr: sysfs attribute to enable/disable clock gating 364 * @is_enabled: Indicates the current status of clock gating 365 * @is_initialized: Indicates whether clock gating is initialized or not 366 * @active_reqs: number of requests that are pending and should be waited for 367 * completion before gating clocks. 368 * @clk_gating_workq: workqueue for clock gating work. 369 */ 370 struct ufs_clk_gating { 371 struct delayed_work gate_work; 372 struct work_struct ungate_work; 373 enum clk_gating_state state; 374 unsigned long delay_ms; 375 bool is_suspended; 376 struct device_attribute delay_attr; 377 struct device_attribute enable_attr; 378 bool is_enabled; 379 bool is_initialized; 380 int active_reqs; 381 struct workqueue_struct *clk_gating_workq; 382 }; 383 384 struct ufs_saved_pwr_info { 385 struct ufs_pa_layer_attr info; 386 bool is_valid; 387 }; 388 389 /** 390 * struct ufs_clk_scaling - UFS clock scaling related data 391 * @active_reqs: number of requests that are pending. If this is zero when 392 * devfreq ->target() function is called then schedule "suspend_work" to 393 * suspend devfreq. 394 * @tot_busy_t: Total busy time in current polling window 395 * @window_start_t: Start time (in jiffies) of the current polling window 396 * @busy_start_t: Start time of current busy period 397 * @enable_attr: sysfs attribute to enable/disable clock scaling 398 * @saved_pwr_info: UFS power mode may also be changed during scaling and this 399 * one keeps track of previous power mode. 400 * @workq: workqueue to schedule devfreq suspend/resume work 401 * @suspend_work: worker to suspend devfreq 402 * @resume_work: worker to resume devfreq 403 * @min_gear: lowest HS gear to scale down to 404 * @is_enabled: tracks if scaling is currently enabled or not, controlled by 405 * clkscale_enable sysfs node 406 * @is_allowed: tracks if scaling is currently allowed or not, used to block 407 * clock scaling which is not invoked from devfreq governor 408 * @is_initialized: Indicates whether clock scaling is initialized or not 409 * @is_busy_started: tracks if busy period has started or not 410 * @is_suspended: tracks if devfreq is suspended or not 411 */ 412 struct ufs_clk_scaling { 413 int active_reqs; 414 unsigned long tot_busy_t; 415 ktime_t window_start_t; 416 ktime_t busy_start_t; 417 struct device_attribute enable_attr; 418 struct ufs_saved_pwr_info saved_pwr_info; 419 struct workqueue_struct *workq; 420 struct work_struct suspend_work; 421 struct work_struct resume_work; 422 u32 min_gear; 423 bool is_enabled; 424 bool is_allowed; 425 bool is_initialized; 426 bool is_busy_started; 427 bool is_suspended; 428 }; 429 430 #define UFS_EVENT_HIST_LENGTH 8 431 /** 432 * struct ufs_event_hist - keeps history of errors 433 * @pos: index to indicate cyclic buffer position 434 * @val: cyclic buffer for registers value 435 * @tstamp: cyclic buffer for time stamp 436 * @cnt: error counter 437 */ 438 struct ufs_event_hist { 439 int pos; 440 u32 val[UFS_EVENT_HIST_LENGTH]; 441 u64 tstamp[UFS_EVENT_HIST_LENGTH]; 442 unsigned long long cnt; 443 }; 444 445 /** 446 * struct ufs_stats - keeps usage/err statistics 447 * @last_intr_status: record the last interrupt status. 448 * @last_intr_ts: record the last interrupt timestamp. 449 * @hibern8_exit_cnt: Counter to keep track of number of exits, 450 * reset this after link-startup. 451 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. 452 * Clear after the first successful command completion. 453 * @event: array with event history. 454 */ 455 struct ufs_stats { 456 u32 last_intr_status; 457 u64 last_intr_ts; 458 459 u32 hibern8_exit_cnt; 460 u64 last_hibern8_exit_tstamp; 461 struct ufs_event_hist event[UFS_EVT_CNT]; 462 }; 463 464 /** 465 * enum ufshcd_state - UFS host controller state 466 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command 467 * processing. 468 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process 469 * SCSI commands. 470 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. 471 * SCSI commands may be submitted to the controller. 472 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail 473 * newly submitted SCSI commands with error code DID_BAD_TARGET. 474 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery 475 * failed. Fail all SCSI commands with error code DID_ERROR. 476 */ 477 enum ufshcd_state { 478 UFSHCD_STATE_RESET, 479 UFSHCD_STATE_OPERATIONAL, 480 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, 481 UFSHCD_STATE_EH_SCHEDULED_FATAL, 482 UFSHCD_STATE_ERROR, 483 }; 484 485 enum ufshcd_quirks { 486 /* Interrupt aggregation support is broken */ 487 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, 488 489 /* 490 * delay before each dme command is required as the unipro 491 * layer has shown instabilities 492 */ 493 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, 494 495 /* 496 * If UFS host controller is having issue in processing LCC (Line 497 * Control Command) coming from device then enable this quirk. 498 * When this quirk is enabled, host controller driver should disable 499 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 500 * attribute of device to 0). 501 */ 502 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, 503 504 /* 505 * The attribute PA_RXHSUNTERMCAP specifies whether or not the 506 * inbound Link supports unterminated line in HS mode. Setting this 507 * attribute to 1 fixes moving to HS gear. 508 */ 509 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, 510 511 /* 512 * This quirk needs to be enabled if the host controller only allows 513 * accessing the peer dme attributes in AUTO mode (FAST AUTO or 514 * SLOW AUTO). 515 */ 516 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, 517 518 /* 519 * This quirk needs to be enabled if the host controller doesn't 520 * advertise the correct version in UFS_VER register. If this quirk 521 * is enabled, standard UFS host driver will call the vendor specific 522 * ops (get_ufs_hci_version) to get the correct version. 523 */ 524 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, 525 526 /* 527 * Clear handling for transfer/task request list is just opposite. 528 */ 529 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, 530 531 /* 532 * This quirk needs to be enabled if host controller doesn't allow 533 * that the interrupt aggregation timer and counter are reset by s/w. 534 */ 535 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, 536 537 /* 538 * This quirks needs to be enabled if host controller cannot be 539 * enabled via HCE register. 540 */ 541 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, 542 543 /* 544 * This quirk needs to be enabled if the host controller regards 545 * resolution of the values of PRDTO and PRDTL in UTRD as byte. 546 */ 547 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, 548 549 /* 550 * This quirk needs to be enabled if the host controller reports 551 * OCS FATAL ERROR with device error through sense data 552 */ 553 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, 554 555 /* 556 * This quirk needs to be enabled if the host controller has 557 * auto-hibernate capability but it doesn't work. 558 */ 559 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, 560 561 /* 562 * This quirk needs to disable manual flush for write booster 563 */ 564 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, 565 566 /* 567 * This quirk needs to disable unipro timeout values 568 * before power mode change 569 */ 570 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, 571 572 /* 573 * This quirk allows only sg entries aligned with page size. 574 */ 575 UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 14, 576 577 /* 578 * This quirk needs to be enabled if the host controller does not 579 * support UIC command 580 */ 581 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, 582 583 /* 584 * This quirk needs to be enabled if the host controller cannot 585 * support physical host configuration. 586 */ 587 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, 588 589 /* 590 * This quirk needs to be enabled if the host controller has 591 * 64-bit addressing supported capability but it doesn't work. 592 */ 593 UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, 594 595 /* 596 * This quirk needs to be enabled if the host controller has 597 * auto-hibernate capability but it's FASTAUTO only. 598 */ 599 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, 600 601 /* 602 * This quirk needs to be enabled if the host controller needs 603 * to reinit the device after switching to maximum gear. 604 */ 605 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, 606 }; 607 608 enum ufshcd_caps { 609 /* Allow dynamic clk gating */ 610 UFSHCD_CAP_CLK_GATING = 1 << 0, 611 612 /* Allow hiberb8 with clk gating */ 613 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, 614 615 /* Allow dynamic clk scaling */ 616 UFSHCD_CAP_CLK_SCALING = 1 << 2, 617 618 /* Allow auto bkops to enabled during runtime suspend */ 619 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, 620 621 /* 622 * This capability allows host controller driver to use the UFS HCI's 623 * interrupt aggregation capability. 624 * CAUTION: Enabling this might reduce overall UFS throughput. 625 */ 626 UFSHCD_CAP_INTR_AGGR = 1 << 4, 627 628 /* 629 * This capability allows the device auto-bkops to be always enabled 630 * except during suspend (both runtime and suspend). 631 * Enabling this capability means that device will always be allowed 632 * to do background operation when it's active but it might degrade 633 * the performance of ongoing read/write operations. 634 */ 635 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, 636 637 /* 638 * This capability allows host controller driver to automatically 639 * enable runtime power management by itself instead of waiting 640 * for userspace to control the power management. 641 */ 642 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, 643 644 /* 645 * This capability allows the host controller driver to turn-on 646 * WriteBooster, if the underlying device supports it and is 647 * provisioned to be used. This would increase the write performance. 648 */ 649 UFSHCD_CAP_WB_EN = 1 << 7, 650 651 /* 652 * This capability allows the host controller driver to use the 653 * inline crypto engine, if it is present 654 */ 655 UFSHCD_CAP_CRYPTO = 1 << 8, 656 657 /* 658 * This capability allows the controller regulators to be put into 659 * lpm mode aggressively during clock gating. 660 * This would increase power savings. 661 */ 662 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, 663 664 /* 665 * This capability allows the host controller driver to use DeepSleep, 666 * if it is supported by the UFS device. The host controller driver must 667 * support device hardware reset via the hba->device_reset() callback, 668 * in order to exit DeepSleep state. 669 */ 670 UFSHCD_CAP_DEEPSLEEP = 1 << 10, 671 672 /* 673 * This capability allows the host controller driver to use temperature 674 * notification if it is supported by the UFS device. 675 */ 676 UFSHCD_CAP_TEMP_NOTIF = 1 << 11, 677 678 /* 679 * Enable WriteBooster when scaling up the clock and disable 680 * WriteBooster when scaling the clock down. 681 */ 682 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, 683 }; 684 685 struct ufs_hba_variant_params { 686 struct devfreq_dev_profile devfreq_profile; 687 struct devfreq_simple_ondemand_data ondemand_data; 688 u16 hba_enable_delay_us; 689 u32 wb_flush_threshold; 690 }; 691 692 #ifdef CONFIG_SCSI_UFS_HPB 693 /** 694 * struct ufshpb_dev_info - UFSHPB device related info 695 * @num_lu: the number of user logical unit to check whether all lu finished 696 * initialization 697 * @rgn_size: device reported HPB region size 698 * @srgn_size: device reported HPB sub-region size 699 * @slave_conf_cnt: counter to check all lu finished initialization 700 * @hpb_disabled: flag to check if HPB is disabled 701 * @max_hpb_single_cmd: device reported bMAX_DATA_SIZE_FOR_SINGLE_CMD value 702 * @is_legacy: flag to check HPB 1.0 703 * @control_mode: either host or device 704 */ 705 struct ufshpb_dev_info { 706 int num_lu; 707 int rgn_size; 708 int srgn_size; 709 atomic_t slave_conf_cnt; 710 bool hpb_disabled; 711 u8 max_hpb_single_cmd; 712 bool is_legacy; 713 u8 control_mode; 714 }; 715 #endif 716 717 struct ufs_hba_monitor { 718 unsigned long chunk_size; 719 720 unsigned long nr_sec_rw[2]; 721 ktime_t total_busy[2]; 722 723 unsigned long nr_req[2]; 724 /* latencies*/ 725 ktime_t lat_sum[2]; 726 ktime_t lat_max[2]; 727 ktime_t lat_min[2]; 728 729 u32 nr_queued[2]; 730 ktime_t busy_start_ts[2]; 731 732 ktime_t enabled_ts; 733 bool enabled; 734 }; 735 736 /** 737 * struct ufs_hba - per adapter private structure 738 * @mmio_base: UFSHCI base register address 739 * @ucdl_base_addr: UFS Command Descriptor base address 740 * @utrdl_base_addr: UTP Transfer Request Descriptor base address 741 * @utmrdl_base_addr: UTP Task Management Descriptor base address 742 * @ucdl_dma_addr: UFS Command Descriptor DMA address 743 * @utrdl_dma_addr: UTRDL DMA address 744 * @utmrdl_dma_addr: UTMRDL DMA address 745 * @host: Scsi_Host instance of the driver 746 * @dev: device handle 747 * @ufs_device_wlun: WLUN that controls the entire UFS device. 748 * @hwmon_device: device instance registered with the hwmon core. 749 * @curr_dev_pwr_mode: active UFS device power mode. 750 * @uic_link_state: active state of the link to the UFS device. 751 * @rpm_lvl: desired UFS power management level during runtime PM. 752 * @spm_lvl: desired UFS power management level during system PM. 753 * @pm_op_in_progress: whether or not a PM operation is in progress. 754 * @ahit: value of Auto-Hibernate Idle Timer register. 755 * @lrb: local reference block 756 * @outstanding_tasks: Bits representing outstanding task requests 757 * @outstanding_lock: Protects @outstanding_reqs. 758 * @outstanding_reqs: Bits representing outstanding transfer requests 759 * @capabilities: UFS Controller Capabilities 760 * @nutrs: Transfer Request Queue depth supported by controller 761 * @nutmrs: Task Management Queue depth supported by controller 762 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. 763 * @ufs_version: UFS Version to which controller complies 764 * @vops: pointer to variant specific operations 765 * @vps: pointer to variant specific parameters 766 * @priv: pointer to variant specific private data 767 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) 768 * @irq: Irq number of the controller 769 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. 770 * @dev_ref_clk_freq: reference clock frequency 771 * @quirks: bitmask with information about deviations from the UFSHCI standard. 772 * @dev_quirks: bitmask with information about deviations from the UFS standard. 773 * @tmf_tag_set: TMF tag set. 774 * @tmf_queue: Used to allocate TMF tags. 775 * @tmf_rqs: array with pointers to TMF requests while these are in progress. 776 * @active_uic_cmd: handle of active UIC command 777 * @uic_cmd_mutex: mutex for UIC command 778 * @uic_async_done: completion used during UIC processing 779 * @ufshcd_state: UFSHCD state 780 * @eh_flags: Error handling flags 781 * @intr_mask: Interrupt Mask Bits 782 * @ee_ctrl_mask: Exception event control mask 783 * @ee_drv_mask: Exception event mask for driver 784 * @ee_usr_mask: Exception event mask for user (set via debugfs) 785 * @ee_ctrl_mutex: Used to serialize exception event information. 786 * @is_powered: flag to check if HBA is powered 787 * @shutting_down: flag to check if shutdown has been invoked 788 * @host_sem: semaphore used to serialize concurrent contexts 789 * @eh_wq: Workqueue that eh_work works on 790 * @eh_work: Worker to handle UFS errors that require s/w attention 791 * @eeh_work: Worker to handle exception events 792 * @errors: HBA errors 793 * @uic_error: UFS interconnect layer error status 794 * @saved_err: sticky error mask 795 * @saved_uic_err: sticky UIC error mask 796 * @ufs_stats: various error counters 797 * @force_reset: flag to force eh_work perform a full reset 798 * @force_pmc: flag to force a power mode change 799 * @silence_err_logs: flag to silence error logs 800 * @dev_cmd: ufs device management command information 801 * @last_dme_cmd_tstamp: time stamp of the last completed DME command 802 * @nop_out_timeout: NOP OUT timeout value 803 * @dev_info: information about the UFS device 804 * @auto_bkops_enabled: to track whether bkops is enabled in device 805 * @vreg_info: UFS device voltage regulator information 806 * @clk_list_head: UFS host controller clocks list node head 807 * @req_abort_count: number of times ufshcd_abort() has been called 808 * @lanes_per_direction: number of lanes per data direction between the UFS 809 * controller and the UFS device. 810 * @pwr_info: holds current power mode 811 * @max_pwr_info: keeps the device max valid pwm 812 * @clk_gating: information related to clock gating 813 * @caps: bitmask with information about UFS controller capabilities 814 * @devfreq: frequency scaling information owned by the devfreq core 815 * @clk_scaling: frequency scaling information owned by the UFS driver 816 * @system_suspending: system suspend has been started and system resume has 817 * not yet finished. 818 * @is_sys_suspended: UFS device has been suspended because of system suspend 819 * @urgent_bkops_lvl: keeps track of urgent bkops level for device 820 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for 821 * device is known or not. 822 * @clk_scaling_lock: used to serialize device commands and clock scaling 823 * @desc_size: descriptor sizes reported by device 824 * @scsi_block_reqs_cnt: reference counting for scsi block requests 825 * @bsg_dev: struct device associated with the BSG queue 826 * @bsg_queue: BSG queue associated with the UFS controller 827 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power 828 * management) after the UFS device has finished a WriteBooster buffer 829 * flush or auto BKOP. 830 * @ufshpb_dev: information related to HPB (Host Performance Booster). 831 * @monitor: statistics about UFS commands 832 * @crypto_capabilities: Content of crypto capabilities register (0x100) 833 * @crypto_cap_array: Array of crypto capabilities 834 * @crypto_cfg_register: Start of the crypto cfg array 835 * @crypto_profile: the crypto profile of this hba (if applicable) 836 * @debugfs_root: UFS controller debugfs root directory 837 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay 838 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore 839 * ee_ctrl_mask 840 * @luns_avail: number of regular and well known LUNs supported by the UFS 841 * device 842 * @complete_put: whether or not to call ufshcd_rpm_put() from inside 843 * ufshcd_resume_complete() 844 */ 845 struct ufs_hba { 846 void __iomem *mmio_base; 847 848 /* Virtual memory reference */ 849 struct utp_transfer_cmd_desc *ucdl_base_addr; 850 struct utp_transfer_req_desc *utrdl_base_addr; 851 struct utp_task_req_desc *utmrdl_base_addr; 852 853 /* DMA memory reference */ 854 dma_addr_t ucdl_dma_addr; 855 dma_addr_t utrdl_dma_addr; 856 dma_addr_t utmrdl_dma_addr; 857 858 struct Scsi_Host *host; 859 struct device *dev; 860 struct scsi_device *ufs_device_wlun; 861 862 #ifdef CONFIG_SCSI_UFS_HWMON 863 struct device *hwmon_device; 864 #endif 865 866 enum ufs_dev_pwr_mode curr_dev_pwr_mode; 867 enum uic_link_state uic_link_state; 868 /* Desired UFS power management level during runtime PM */ 869 enum ufs_pm_level rpm_lvl; 870 /* Desired UFS power management level during system PM */ 871 enum ufs_pm_level spm_lvl; 872 int pm_op_in_progress; 873 874 /* Auto-Hibernate Idle Timer register value */ 875 u32 ahit; 876 877 struct ufshcd_lrb *lrb; 878 879 unsigned long outstanding_tasks; 880 spinlock_t outstanding_lock; 881 unsigned long outstanding_reqs; 882 883 u32 capabilities; 884 int nutrs; 885 int nutmrs; 886 u32 reserved_slot; 887 u32 ufs_version; 888 const struct ufs_hba_variant_ops *vops; 889 struct ufs_hba_variant_params *vps; 890 void *priv; 891 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 892 size_t sg_entry_size; 893 #endif 894 unsigned int irq; 895 bool is_irq_enabled; 896 enum ufs_ref_clk_freq dev_ref_clk_freq; 897 898 unsigned int quirks; /* Deviations from standard UFSHCI spec. */ 899 900 /* Device deviations from standard UFS device spec. */ 901 unsigned int dev_quirks; 902 903 struct blk_mq_tag_set tmf_tag_set; 904 struct request_queue *tmf_queue; 905 struct request **tmf_rqs; 906 907 struct uic_command *active_uic_cmd; 908 struct mutex uic_cmd_mutex; 909 struct completion *uic_async_done; 910 911 enum ufshcd_state ufshcd_state; 912 u32 eh_flags; 913 u32 intr_mask; 914 u16 ee_ctrl_mask; 915 u16 ee_drv_mask; 916 u16 ee_usr_mask; 917 struct mutex ee_ctrl_mutex; 918 bool is_powered; 919 bool shutting_down; 920 struct semaphore host_sem; 921 922 /* Work Queues */ 923 struct workqueue_struct *eh_wq; 924 struct work_struct eh_work; 925 struct work_struct eeh_work; 926 927 /* HBA Errors */ 928 u32 errors; 929 u32 uic_error; 930 u32 saved_err; 931 u32 saved_uic_err; 932 struct ufs_stats ufs_stats; 933 bool force_reset; 934 bool force_pmc; 935 bool silence_err_logs; 936 937 /* Device management request data */ 938 struct ufs_dev_cmd dev_cmd; 939 ktime_t last_dme_cmd_tstamp; 940 int nop_out_timeout; 941 942 /* Keeps information of the UFS device connected to this host */ 943 struct ufs_dev_info dev_info; 944 bool auto_bkops_enabled; 945 struct ufs_vreg_info vreg_info; 946 struct list_head clk_list_head; 947 948 /* Number of requests aborts */ 949 int req_abort_count; 950 951 /* Number of lanes available (1 or 2) for Rx/Tx */ 952 u32 lanes_per_direction; 953 struct ufs_pa_layer_attr pwr_info; 954 struct ufs_pwr_mode_info max_pwr_info; 955 956 struct ufs_clk_gating clk_gating; 957 /* Control to enable/disable host capabilities */ 958 u32 caps; 959 960 struct devfreq *devfreq; 961 struct ufs_clk_scaling clk_scaling; 962 bool system_suspending; 963 bool is_sys_suspended; 964 965 enum bkops_status urgent_bkops_lvl; 966 bool is_urgent_bkops_lvl_checked; 967 968 struct rw_semaphore clk_scaling_lock; 969 atomic_t scsi_block_reqs_cnt; 970 971 struct device bsg_dev; 972 struct request_queue *bsg_queue; 973 struct delayed_work rpm_dev_flush_recheck_work; 974 975 #ifdef CONFIG_SCSI_UFS_HPB 976 struct ufshpb_dev_info ufshpb_dev; 977 #endif 978 979 struct ufs_hba_monitor monitor; 980 981 #ifdef CONFIG_SCSI_UFS_CRYPTO 982 union ufs_crypto_capabilities crypto_capabilities; 983 union ufs_crypto_cap_entry *crypto_cap_array; 984 u32 crypto_cfg_register; 985 struct blk_crypto_profile crypto_profile; 986 #endif 987 #ifdef CONFIG_DEBUG_FS 988 struct dentry *debugfs_root; 989 struct delayed_work debugfs_ee_work; 990 u32 debugfs_ee_rate_limit_ms; 991 #endif 992 u32 luns_avail; 993 bool complete_put; 994 }; 995 996 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 997 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 998 { 999 return hba->sg_entry_size; 1000 } 1001 1002 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) 1003 { 1004 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); 1005 hba->sg_entry_size = sg_entry_size; 1006 } 1007 #else 1008 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1009 { 1010 return sizeof(struct ufshcd_sg_entry); 1011 } 1012 1013 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ 1014 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) 1015 #endif 1016 1017 static inline size_t sizeof_utp_transfer_cmd_desc(const struct ufs_hba *hba) 1018 { 1019 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); 1020 } 1021 1022 /* Returns true if clocks can be gated. Otherwise false */ 1023 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) 1024 { 1025 return hba->caps & UFSHCD_CAP_CLK_GATING; 1026 } 1027 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) 1028 { 1029 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1030 } 1031 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) 1032 { 1033 return hba->caps & UFSHCD_CAP_CLK_SCALING; 1034 } 1035 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 1036 { 1037 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1038 } 1039 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) 1040 { 1041 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; 1042 } 1043 1044 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) 1045 { 1046 return (hba->caps & UFSHCD_CAP_INTR_AGGR) && 1047 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); 1048 } 1049 1050 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) 1051 { 1052 return !!(ufshcd_is_link_hibern8(hba) && 1053 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); 1054 } 1055 1056 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) 1057 { 1058 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && 1059 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); 1060 } 1061 1062 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) 1063 { 1064 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); 1065 } 1066 1067 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) 1068 { 1069 return hba->caps & UFSHCD_CAP_WB_EN; 1070 } 1071 1072 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) 1073 { 1074 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; 1075 } 1076 1077 #define ufshcd_writel(hba, val, reg) \ 1078 writel((val), (hba)->mmio_base + (reg)) 1079 #define ufshcd_readl(hba, reg) \ 1080 readl((hba)->mmio_base + (reg)) 1081 1082 /** 1083 * ufshcd_rmwl - perform read/modify/write for a controller register 1084 * @hba: per adapter instance 1085 * @mask: mask to apply on read value 1086 * @val: actual value to write 1087 * @reg: register address 1088 */ 1089 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 1090 { 1091 u32 tmp; 1092 1093 tmp = ufshcd_readl(hba, reg); 1094 tmp &= ~mask; 1095 tmp |= (val & mask); 1096 ufshcd_writel(hba, tmp, reg); 1097 } 1098 1099 int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1100 void ufshcd_dealloc_host(struct ufs_hba *); 1101 int ufshcd_hba_enable(struct ufs_hba *hba); 1102 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); 1103 int ufshcd_link_recovery(struct ufs_hba *hba); 1104 int ufshcd_make_hba_operational(struct ufs_hba *hba); 1105 void ufshcd_remove(struct ufs_hba *); 1106 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); 1107 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); 1108 void ufshcd_delay_us(unsigned long us, unsigned long tolerance); 1109 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); 1110 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); 1111 void ufshcd_hba_stop(struct ufs_hba *hba); 1112 void ufshcd_schedule_eh_work(struct ufs_hba *hba); 1113 1114 /** 1115 * ufshcd_set_variant - set variant specific data to the hba 1116 * @hba: per adapter instance 1117 * @variant: pointer to variant specific data 1118 */ 1119 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) 1120 { 1121 BUG_ON(!hba); 1122 hba->priv = variant; 1123 } 1124 1125 /** 1126 * ufshcd_get_variant - get variant specific data from the hba 1127 * @hba: per adapter instance 1128 */ 1129 static inline void *ufshcd_get_variant(struct ufs_hba *hba) 1130 { 1131 BUG_ON(!hba); 1132 return hba->priv; 1133 } 1134 1135 #ifdef CONFIG_PM 1136 extern int ufshcd_runtime_suspend(struct device *dev); 1137 extern int ufshcd_runtime_resume(struct device *dev); 1138 #endif 1139 #ifdef CONFIG_PM_SLEEP 1140 extern int ufshcd_system_suspend(struct device *dev); 1141 extern int ufshcd_system_resume(struct device *dev); 1142 #endif 1143 extern int ufshcd_shutdown(struct ufs_hba *hba); 1144 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 1145 int agreed_gear, 1146 int adapt_val); 1147 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 1148 u8 attr_set, u32 mib_val, u8 peer); 1149 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 1150 u32 *mib_val, u8 peer); 1151 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, 1152 struct ufs_pa_layer_attr *desired_pwr_mode); 1153 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); 1154 1155 /* UIC command interfaces for DME primitives */ 1156 #define DME_LOCAL 0 1157 #define DME_PEER 1 1158 #define ATTR_SET_NOR 0 /* NORMAL */ 1159 #define ATTR_SET_ST 1 /* STATIC */ 1160 1161 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 1162 u32 mib_val) 1163 { 1164 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1165 mib_val, DME_LOCAL); 1166 } 1167 1168 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, 1169 u32 mib_val) 1170 { 1171 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1172 mib_val, DME_LOCAL); 1173 } 1174 1175 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 1176 u32 mib_val) 1177 { 1178 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1179 mib_val, DME_PEER); 1180 } 1181 1182 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, 1183 u32 mib_val) 1184 { 1185 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1186 mib_val, DME_PEER); 1187 } 1188 1189 static inline int ufshcd_dme_get(struct ufs_hba *hba, 1190 u32 attr_sel, u32 *mib_val) 1191 { 1192 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 1193 } 1194 1195 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 1196 u32 attr_sel, u32 *mib_val) 1197 { 1198 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 1199 } 1200 1201 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) 1202 { 1203 return (pwr_info->pwr_rx == FAST_MODE || 1204 pwr_info->pwr_rx == FASTAUTO_MODE) && 1205 (pwr_info->pwr_tx == FAST_MODE || 1206 pwr_info->pwr_tx == FASTAUTO_MODE); 1207 } 1208 1209 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) 1210 { 1211 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); 1212 } 1213 1214 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); 1215 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); 1216 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 1217 const struct ufs_dev_quirk *fixups); 1218 #define SD_ASCII_STD true 1219 #define SD_RAW false 1220 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 1221 u8 **buf, bool ascii); 1222 1223 int ufshcd_hold(struct ufs_hba *hba, bool async); 1224 void ufshcd_release(struct ufs_hba *hba); 1225 1226 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); 1227 1228 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); 1229 1230 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); 1231 1232 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); 1233 1234 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 1235 struct utp_upiu_req *req_upiu, 1236 struct utp_upiu_req *rsp_upiu, 1237 int msgcode, 1238 u8 *desc_buff, int *buff_len, 1239 enum query_opcode desc_op); 1240 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 1241 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, 1242 struct ufs_ehs *ehs_rsp, int sg_cnt, 1243 struct scatterlist *sg_list, enum dma_data_direction dir); 1244 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); 1245 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); 1246 int ufshcd_suspend_prepare(struct device *dev); 1247 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); 1248 void ufshcd_resume_complete(struct device *dev); 1249 1250 /* Wrapper functions for safely calling variant operations */ 1251 static inline int ufshcd_vops_init(struct ufs_hba *hba) 1252 { 1253 if (hba->vops && hba->vops->init) 1254 return hba->vops->init(hba); 1255 1256 return 0; 1257 } 1258 1259 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) 1260 { 1261 if (hba->vops && hba->vops->phy_initialization) 1262 return hba->vops->phy_initialization(hba); 1263 1264 return 0; 1265 } 1266 1267 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; 1268 1269 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1270 const char *prefix); 1271 1272 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); 1273 int ufshcd_write_ee_control(struct ufs_hba *hba); 1274 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 1275 const u16 *other_mask, u16 set, u16 clr); 1276 1277 #endif /* End of Header */ 1278