1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #ifndef _UFSHCD_H 13 #define _UFSHCD_H 14 15 #include <linux/bitfield.h> 16 #include <linux/blk-crypto-profile.h> 17 #include <linux/blk-mq.h> 18 #include <linux/devfreq.h> 19 #include <linux/fault-inject.h> 20 #include <linux/msi.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/dma-direction.h> 23 #include <scsi/scsi_device.h> 24 #include <scsi/scsi_host.h> 25 #include <ufs/unipro.h> 26 #include <ufs/ufs.h> 27 #include <ufs/ufs_quirks.h> 28 #include <ufs/ufshci.h> 29 30 #define UFSHCD "ufshcd" 31 32 struct scsi_device; 33 struct ufs_hba; 34 35 enum dev_cmd_type { 36 DEV_CMD_TYPE_NOP = 0x0, 37 DEV_CMD_TYPE_QUERY = 0x1, 38 DEV_CMD_TYPE_RPMB = 0x2, 39 }; 40 41 enum ufs_event_type { 42 /* uic specific errors */ 43 UFS_EVT_PA_ERR = 0, 44 UFS_EVT_DL_ERR, 45 UFS_EVT_NL_ERR, 46 UFS_EVT_TL_ERR, 47 UFS_EVT_DME_ERR, 48 49 /* fatal errors */ 50 UFS_EVT_AUTO_HIBERN8_ERR, 51 UFS_EVT_FATAL_ERR, 52 UFS_EVT_LINK_STARTUP_FAIL, 53 UFS_EVT_RESUME_ERR, 54 UFS_EVT_SUSPEND_ERR, 55 UFS_EVT_WL_SUSP_ERR, 56 UFS_EVT_WL_RES_ERR, 57 58 /* abnormal events */ 59 UFS_EVT_DEV_RESET, 60 UFS_EVT_HOST_RESET, 61 UFS_EVT_ABORT, 62 63 UFS_EVT_CNT, 64 }; 65 66 /** 67 * struct uic_command - UIC command structure 68 * @command: UIC command 69 * @argument1: UIC command argument 1 70 * @argument2: UIC command argument 2 71 * @argument3: UIC command argument 3 72 * @cmd_active: Indicate if UIC command is outstanding 73 * @done: UIC command completion 74 */ 75 struct uic_command { 76 u32 command; 77 u32 argument1; 78 u32 argument2; 79 u32 argument3; 80 int cmd_active; 81 struct completion done; 82 }; 83 84 /* Used to differentiate the power management options */ 85 enum ufs_pm_op { 86 UFS_RUNTIME_PM, 87 UFS_SYSTEM_PM, 88 UFS_SHUTDOWN_PM, 89 }; 90 91 /* Host <-> Device UniPro Link state */ 92 enum uic_link_state { 93 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 94 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 95 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 96 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ 97 }; 98 99 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) 100 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ 101 UIC_LINK_ACTIVE_STATE) 102 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ 103 UIC_LINK_HIBERN8_STATE) 104 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ 105 UIC_LINK_BROKEN_STATE) 106 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) 107 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ 108 UIC_LINK_ACTIVE_STATE) 109 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ 110 UIC_LINK_HIBERN8_STATE) 111 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ 112 UIC_LINK_BROKEN_STATE) 113 114 #define ufshcd_set_ufs_dev_active(h) \ 115 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) 116 #define ufshcd_set_ufs_dev_sleep(h) \ 117 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) 118 #define ufshcd_set_ufs_dev_poweroff(h) \ 119 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) 120 #define ufshcd_set_ufs_dev_deepsleep(h) \ 121 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) 122 #define ufshcd_is_ufs_dev_active(h) \ 123 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) 124 #define ufshcd_is_ufs_dev_sleep(h) \ 125 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) 126 #define ufshcd_is_ufs_dev_poweroff(h) \ 127 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) 128 #define ufshcd_is_ufs_dev_deepsleep(h) \ 129 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) 130 131 /* 132 * UFS Power management levels. 133 * Each level is in increasing order of power savings, except DeepSleep 134 * which is lower than PowerDown with power on but not PowerDown with 135 * power off. 136 */ 137 enum ufs_pm_level { 138 UFS_PM_LVL_0, 139 UFS_PM_LVL_1, 140 UFS_PM_LVL_2, 141 UFS_PM_LVL_3, 142 UFS_PM_LVL_4, 143 UFS_PM_LVL_5, 144 UFS_PM_LVL_6, 145 UFS_PM_LVL_MAX 146 }; 147 148 struct ufs_pm_lvl_states { 149 enum ufs_dev_pwr_mode dev_state; 150 enum uic_link_state link_state; 151 }; 152 153 /** 154 * struct ufshcd_lrb - local reference block 155 * @utr_descriptor_ptr: UTRD address of the command 156 * @ucd_req_ptr: UCD address of the command 157 * @ucd_rsp_ptr: Response UPIU address for this command 158 * @ucd_prdt_ptr: PRDT address of the command 159 * @utrd_dma_addr: UTRD dma address for debug 160 * @ucd_prdt_dma_addr: PRDT dma address for debug 161 * @ucd_rsp_dma_addr: UPIU response dma address for debug 162 * @ucd_req_dma_addr: UPIU request dma address for debug 163 * @cmd: pointer to SCSI command 164 * @scsi_status: SCSI status of the command 165 * @command_type: SCSI, UFS, Query. 166 * @task_tag: Task tag of the command 167 * @lun: LUN of the command 168 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) 169 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) 170 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) 171 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) 172 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) 173 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) 174 * @data_unit_num: the data unit number for the first block for inline crypto 175 * @req_abort_skip: skip request abort task flag 176 */ 177 struct ufshcd_lrb { 178 struct utp_transfer_req_desc *utr_descriptor_ptr; 179 struct utp_upiu_req *ucd_req_ptr; 180 struct utp_upiu_rsp *ucd_rsp_ptr; 181 struct ufshcd_sg_entry *ucd_prdt_ptr; 182 183 dma_addr_t utrd_dma_addr; 184 dma_addr_t ucd_req_dma_addr; 185 dma_addr_t ucd_rsp_dma_addr; 186 dma_addr_t ucd_prdt_dma_addr; 187 188 struct scsi_cmnd *cmd; 189 int scsi_status; 190 191 int command_type; 192 int task_tag; 193 u8 lun; /* UPIU LUN id field is only 8-bit wide */ 194 bool intr_cmd; 195 ktime_t issue_time_stamp; 196 u64 issue_time_stamp_local_clock; 197 ktime_t compl_time_stamp; 198 u64 compl_time_stamp_local_clock; 199 #ifdef CONFIG_SCSI_UFS_CRYPTO 200 int crypto_key_slot; 201 u64 data_unit_num; 202 #endif 203 204 bool req_abort_skip; 205 }; 206 207 /** 208 * struct ufs_query_req - parameters for building a query request 209 * @query_func: UPIU header query function 210 * @upiu_req: the query request data 211 */ 212 struct ufs_query_req { 213 u8 query_func; 214 struct utp_upiu_query upiu_req; 215 }; 216 217 /** 218 * struct ufs_query_resp - UPIU QUERY 219 * @response: device response code 220 * @upiu_res: query response data 221 */ 222 struct ufs_query_res { 223 struct utp_upiu_query upiu_res; 224 }; 225 226 /** 227 * struct ufs_query - holds relevant data structures for query request 228 * @request: request upiu and function 229 * @descriptor: buffer for sending/receiving descriptor 230 * @response: response upiu and response 231 */ 232 struct ufs_query { 233 struct ufs_query_req request; 234 u8 *descriptor; 235 struct ufs_query_res response; 236 }; 237 238 /** 239 * struct ufs_dev_cmd - all assosiated fields with device management commands 240 * @type: device management command type - Query, NOP OUT 241 * @lock: lock to allow one command at a time 242 * @complete: internal commands completion 243 * @query: Device management query information 244 */ 245 struct ufs_dev_cmd { 246 enum dev_cmd_type type; 247 struct mutex lock; 248 struct completion *complete; 249 struct ufs_query query; 250 }; 251 252 /** 253 * struct ufs_clk_info - UFS clock related info 254 * @list: list headed by hba->clk_list_head 255 * @clk: clock node 256 * @name: clock name 257 * @max_freq: maximum frequency supported by the clock 258 * @min_freq: min frequency that can be used for clock scaling 259 * @curr_freq: indicates the current frequency that it is set to 260 * @keep_link_active: indicates that the clk should not be disabled if 261 * link is active 262 * @enabled: variable to check against multiple enable/disable 263 */ 264 struct ufs_clk_info { 265 struct list_head list; 266 struct clk *clk; 267 const char *name; 268 u32 max_freq; 269 u32 min_freq; 270 u32 curr_freq; 271 bool keep_link_active; 272 bool enabled; 273 }; 274 275 enum ufs_notify_change_status { 276 PRE_CHANGE, 277 POST_CHANGE, 278 }; 279 280 struct ufs_pa_layer_attr { 281 u32 gear_rx; 282 u32 gear_tx; 283 u32 lane_rx; 284 u32 lane_tx; 285 u32 pwr_rx; 286 u32 pwr_tx; 287 u32 hs_rate; 288 }; 289 290 struct ufs_pwr_mode_info { 291 bool is_valid; 292 struct ufs_pa_layer_attr info; 293 }; 294 295 /** 296 * struct ufs_hba_variant_ops - variant specific callbacks 297 * @name: variant name 298 * @init: called when the driver is initialized 299 * @exit: called to cleanup everything done in init 300 * @get_ufs_hci_version: called to get UFS HCI version 301 * @clk_scale_notify: notifies that clks are scaled up/down 302 * @setup_clocks: called before touching any of the controller registers 303 * @hce_enable_notify: called before and after HCE enable bit is set to allow 304 * variant specific Uni-Pro initialization. 305 * @link_startup_notify: called before and after Link startup is carried out 306 * to allow variant specific Uni-Pro initialization. 307 * @pwr_change_notify: called before and after a power mode change 308 * is carried out to allow vendor spesific capabilities 309 * to be set. 310 * @setup_xfer_req: called before any transfer request is issued 311 * to set some things 312 * @setup_task_mgmt: called before any task management request is issued 313 * to set some things 314 * @hibern8_notify: called around hibern8 enter/exit 315 * @apply_dev_quirks: called to apply device specific quirks 316 * @fixup_dev_quirks: called to modify device specific quirks 317 * @suspend: called during host controller PM callback 318 * @resume: called during host controller PM callback 319 * @dbg_register_dump: used to dump controller debug information 320 * @phy_initialization: used to initialize phys 321 * @device_reset: called to issue a reset pulse on the UFS device 322 * @config_scaling_param: called to configure clock scaling parameters 323 * @program_key: program or evict an inline encryption key 324 * @event_notify: called to notify important events 325 * @reinit_notify: called to notify reinit of UFSHCD during max gear switch 326 * @mcq_config_resource: called to configure MCQ platform resources 327 * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode 328 * @op_runtime_config: called to config Operation and runtime regs Pointers 329 * @get_outstanding_cqs: called to get outstanding completion queues 330 * @config_esi: called to config Event Specific Interrupt 331 * @config_scsi_dev: called to configure SCSI device parameters 332 */ 333 struct ufs_hba_variant_ops { 334 const char *name; 335 int (*init)(struct ufs_hba *); 336 void (*exit)(struct ufs_hba *); 337 u32 (*get_ufs_hci_version)(struct ufs_hba *); 338 int (*clk_scale_notify)(struct ufs_hba *, bool, 339 enum ufs_notify_change_status); 340 int (*setup_clocks)(struct ufs_hba *, bool, 341 enum ufs_notify_change_status); 342 int (*hce_enable_notify)(struct ufs_hba *, 343 enum ufs_notify_change_status); 344 int (*link_startup_notify)(struct ufs_hba *, 345 enum ufs_notify_change_status); 346 int (*pwr_change_notify)(struct ufs_hba *, 347 enum ufs_notify_change_status status, 348 struct ufs_pa_layer_attr *, 349 struct ufs_pa_layer_attr *); 350 void (*setup_xfer_req)(struct ufs_hba *hba, int tag, 351 bool is_scsi_cmd); 352 void (*setup_task_mgmt)(struct ufs_hba *, int, u8); 353 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, 354 enum ufs_notify_change_status); 355 int (*apply_dev_quirks)(struct ufs_hba *hba); 356 void (*fixup_dev_quirks)(struct ufs_hba *hba); 357 int (*suspend)(struct ufs_hba *, enum ufs_pm_op, 358 enum ufs_notify_change_status); 359 int (*resume)(struct ufs_hba *, enum ufs_pm_op); 360 void (*dbg_register_dump)(struct ufs_hba *hba); 361 int (*phy_initialization)(struct ufs_hba *); 362 int (*device_reset)(struct ufs_hba *hba); 363 void (*config_scaling_param)(struct ufs_hba *hba, 364 struct devfreq_dev_profile *profile, 365 struct devfreq_simple_ondemand_data *data); 366 int (*program_key)(struct ufs_hba *hba, 367 const union ufs_crypto_cfg_entry *cfg, int slot); 368 void (*event_notify)(struct ufs_hba *hba, 369 enum ufs_event_type evt, void *data); 370 void (*reinit_notify)(struct ufs_hba *); 371 int (*mcq_config_resource)(struct ufs_hba *hba); 372 int (*get_hba_mac)(struct ufs_hba *hba); 373 int (*op_runtime_config)(struct ufs_hba *hba); 374 int (*get_outstanding_cqs)(struct ufs_hba *hba, 375 unsigned long *ocqs); 376 int (*config_esi)(struct ufs_hba *hba); 377 void (*config_scsi_dev)(struct scsi_device *sdev); 378 }; 379 380 /* clock gating state */ 381 enum clk_gating_state { 382 CLKS_OFF, 383 CLKS_ON, 384 REQ_CLKS_OFF, 385 REQ_CLKS_ON, 386 }; 387 388 /** 389 * struct ufs_clk_gating - UFS clock gating related info 390 * @gate_work: worker to turn off clocks after some delay as specified in 391 * delay_ms 392 * @ungate_work: worker to turn on clocks that will be used in case of 393 * interrupt context 394 * @state: the current clocks state 395 * @delay_ms: gating delay in ms 396 * @is_suspended: clk gating is suspended when set to 1 which can be used 397 * during suspend/resume 398 * @delay_attr: sysfs attribute to control delay_attr 399 * @enable_attr: sysfs attribute to enable/disable clock gating 400 * @is_enabled: Indicates the current status of clock gating 401 * @is_initialized: Indicates whether clock gating is initialized or not 402 * @active_reqs: number of requests that are pending and should be waited for 403 * completion before gating clocks. 404 * @clk_gating_workq: workqueue for clock gating work. 405 */ 406 struct ufs_clk_gating { 407 struct delayed_work gate_work; 408 struct work_struct ungate_work; 409 enum clk_gating_state state; 410 unsigned long delay_ms; 411 bool is_suspended; 412 struct device_attribute delay_attr; 413 struct device_attribute enable_attr; 414 bool is_enabled; 415 bool is_initialized; 416 int active_reqs; 417 struct workqueue_struct *clk_gating_workq; 418 }; 419 420 /** 421 * struct ufs_clk_scaling - UFS clock scaling related data 422 * @active_reqs: number of requests that are pending. If this is zero when 423 * devfreq ->target() function is called then schedule "suspend_work" to 424 * suspend devfreq. 425 * @tot_busy_t: Total busy time in current polling window 426 * @window_start_t: Start time (in jiffies) of the current polling window 427 * @busy_start_t: Start time of current busy period 428 * @enable_attr: sysfs attribute to enable/disable clock scaling 429 * @saved_pwr_info: UFS power mode may also be changed during scaling and this 430 * one keeps track of previous power mode. 431 * @workq: workqueue to schedule devfreq suspend/resume work 432 * @suspend_work: worker to suspend devfreq 433 * @resume_work: worker to resume devfreq 434 * @target_freq: frequency requested by devfreq framework 435 * @min_gear: lowest HS gear to scale down to 436 * @is_enabled: tracks if scaling is currently enabled or not, controlled by 437 * clkscale_enable sysfs node 438 * @is_allowed: tracks if scaling is currently allowed or not, used to block 439 * clock scaling which is not invoked from devfreq governor 440 * @is_initialized: Indicates whether clock scaling is initialized or not 441 * @is_busy_started: tracks if busy period has started or not 442 * @is_suspended: tracks if devfreq is suspended or not 443 */ 444 struct ufs_clk_scaling { 445 int active_reqs; 446 unsigned long tot_busy_t; 447 ktime_t window_start_t; 448 ktime_t busy_start_t; 449 struct device_attribute enable_attr; 450 struct ufs_pa_layer_attr saved_pwr_info; 451 struct workqueue_struct *workq; 452 struct work_struct suspend_work; 453 struct work_struct resume_work; 454 unsigned long target_freq; 455 u32 min_gear; 456 bool is_enabled; 457 bool is_allowed; 458 bool is_initialized; 459 bool is_busy_started; 460 bool is_suspended; 461 }; 462 463 #define UFS_EVENT_HIST_LENGTH 8 464 /** 465 * struct ufs_event_hist - keeps history of errors 466 * @pos: index to indicate cyclic buffer position 467 * @val: cyclic buffer for registers value 468 * @tstamp: cyclic buffer for time stamp 469 * @cnt: error counter 470 */ 471 struct ufs_event_hist { 472 int pos; 473 u32 val[UFS_EVENT_HIST_LENGTH]; 474 u64 tstamp[UFS_EVENT_HIST_LENGTH]; 475 unsigned long long cnt; 476 }; 477 478 /** 479 * struct ufs_stats - keeps usage/err statistics 480 * @last_intr_status: record the last interrupt status. 481 * @last_intr_ts: record the last interrupt timestamp. 482 * @hibern8_exit_cnt: Counter to keep track of number of exits, 483 * reset this after link-startup. 484 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. 485 * Clear after the first successful command completion. 486 * @event: array with event history. 487 */ 488 struct ufs_stats { 489 u32 last_intr_status; 490 u64 last_intr_ts; 491 492 u32 hibern8_exit_cnt; 493 u64 last_hibern8_exit_tstamp; 494 struct ufs_event_hist event[UFS_EVT_CNT]; 495 }; 496 497 /** 498 * enum ufshcd_state - UFS host controller state 499 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command 500 * processing. 501 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process 502 * SCSI commands. 503 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. 504 * SCSI commands may be submitted to the controller. 505 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail 506 * newly submitted SCSI commands with error code DID_BAD_TARGET. 507 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery 508 * failed. Fail all SCSI commands with error code DID_ERROR. 509 */ 510 enum ufshcd_state { 511 UFSHCD_STATE_RESET, 512 UFSHCD_STATE_OPERATIONAL, 513 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, 514 UFSHCD_STATE_EH_SCHEDULED_FATAL, 515 UFSHCD_STATE_ERROR, 516 }; 517 518 enum ufshcd_quirks { 519 /* Interrupt aggregation support is broken */ 520 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, 521 522 /* 523 * delay before each dme command is required as the unipro 524 * layer has shown instabilities 525 */ 526 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, 527 528 /* 529 * If UFS host controller is having issue in processing LCC (Line 530 * Control Command) coming from device then enable this quirk. 531 * When this quirk is enabled, host controller driver should disable 532 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 533 * attribute of device to 0). 534 */ 535 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, 536 537 /* 538 * The attribute PA_RXHSUNTERMCAP specifies whether or not the 539 * inbound Link supports unterminated line in HS mode. Setting this 540 * attribute to 1 fixes moving to HS gear. 541 */ 542 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, 543 544 /* 545 * This quirk needs to be enabled if the host controller only allows 546 * accessing the peer dme attributes in AUTO mode (FAST AUTO or 547 * SLOW AUTO). 548 */ 549 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, 550 551 /* 552 * This quirk needs to be enabled if the host controller doesn't 553 * advertise the correct version in UFS_VER register. If this quirk 554 * is enabled, standard UFS host driver will call the vendor specific 555 * ops (get_ufs_hci_version) to get the correct version. 556 */ 557 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, 558 559 /* 560 * Clear handling for transfer/task request list is just opposite. 561 */ 562 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, 563 564 /* 565 * This quirk needs to be enabled if host controller doesn't allow 566 * that the interrupt aggregation timer and counter are reset by s/w. 567 */ 568 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, 569 570 /* 571 * This quirks needs to be enabled if host controller cannot be 572 * enabled via HCE register. 573 */ 574 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, 575 576 /* 577 * This quirk needs to be enabled if the host controller regards 578 * resolution of the values of PRDTO and PRDTL in UTRD as byte. 579 */ 580 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, 581 582 /* 583 * This quirk needs to be enabled if the host controller reports 584 * OCS FATAL ERROR with device error through sense data 585 */ 586 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, 587 588 /* 589 * This quirk needs to be enabled if the host controller has 590 * auto-hibernate capability but it doesn't work. 591 */ 592 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, 593 594 /* 595 * This quirk needs to disable manual flush for write booster 596 */ 597 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, 598 599 /* 600 * This quirk needs to disable unipro timeout values 601 * before power mode change 602 */ 603 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, 604 605 /* 606 * This quirk needs to be enabled if the host controller does not 607 * support UIC command 608 */ 609 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, 610 611 /* 612 * This quirk needs to be enabled if the host controller cannot 613 * support physical host configuration. 614 */ 615 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, 616 617 /* 618 * This quirk needs to be enabled if the host controller has 619 * 64-bit addressing supported capability but it doesn't work. 620 */ 621 UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, 622 623 /* 624 * This quirk needs to be enabled if the host controller has 625 * auto-hibernate capability but it's FASTAUTO only. 626 */ 627 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, 628 629 /* 630 * This quirk needs to be enabled if the host controller needs 631 * to reinit the device after switching to maximum gear. 632 */ 633 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, 634 635 /* 636 * Some host raises interrupt (per queue) in addition to 637 * CQES (traditional) when ESI is disabled. 638 * Enable this quirk will disable CQES and use per queue interrupt. 639 */ 640 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20, 641 642 /* 643 * Some host does not implement SQ Run Time Command (SQRTC) register 644 * thus need this quirk to skip related flow. 645 */ 646 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21, 647 }; 648 649 enum ufshcd_caps { 650 /* Allow dynamic clk gating */ 651 UFSHCD_CAP_CLK_GATING = 1 << 0, 652 653 /* Allow hiberb8 with clk gating */ 654 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, 655 656 /* Allow dynamic clk scaling */ 657 UFSHCD_CAP_CLK_SCALING = 1 << 2, 658 659 /* Allow auto bkops to enabled during runtime suspend */ 660 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, 661 662 /* 663 * This capability allows host controller driver to use the UFS HCI's 664 * interrupt aggregation capability. 665 * CAUTION: Enabling this might reduce overall UFS throughput. 666 */ 667 UFSHCD_CAP_INTR_AGGR = 1 << 4, 668 669 /* 670 * This capability allows the device auto-bkops to be always enabled 671 * except during suspend (both runtime and suspend). 672 * Enabling this capability means that device will always be allowed 673 * to do background operation when it's active but it might degrade 674 * the performance of ongoing read/write operations. 675 */ 676 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, 677 678 /* 679 * This capability allows host controller driver to automatically 680 * enable runtime power management by itself instead of waiting 681 * for userspace to control the power management. 682 */ 683 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, 684 685 /* 686 * This capability allows the host controller driver to turn-on 687 * WriteBooster, if the underlying device supports it and is 688 * provisioned to be used. This would increase the write performance. 689 */ 690 UFSHCD_CAP_WB_EN = 1 << 7, 691 692 /* 693 * This capability allows the host controller driver to use the 694 * inline crypto engine, if it is present 695 */ 696 UFSHCD_CAP_CRYPTO = 1 << 8, 697 698 /* 699 * This capability allows the controller regulators to be put into 700 * lpm mode aggressively during clock gating. 701 * This would increase power savings. 702 */ 703 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, 704 705 /* 706 * This capability allows the host controller driver to use DeepSleep, 707 * if it is supported by the UFS device. The host controller driver must 708 * support device hardware reset via the hba->device_reset() callback, 709 * in order to exit DeepSleep state. 710 */ 711 UFSHCD_CAP_DEEPSLEEP = 1 << 10, 712 713 /* 714 * This capability allows the host controller driver to use temperature 715 * notification if it is supported by the UFS device. 716 */ 717 UFSHCD_CAP_TEMP_NOTIF = 1 << 11, 718 719 /* 720 * Enable WriteBooster when scaling up the clock and disable 721 * WriteBooster when scaling the clock down. 722 */ 723 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, 724 }; 725 726 struct ufs_hba_variant_params { 727 struct devfreq_dev_profile devfreq_profile; 728 struct devfreq_simple_ondemand_data ondemand_data; 729 u16 hba_enable_delay_us; 730 u32 wb_flush_threshold; 731 }; 732 733 struct ufs_hba_monitor { 734 unsigned long chunk_size; 735 736 unsigned long nr_sec_rw[2]; 737 ktime_t total_busy[2]; 738 739 unsigned long nr_req[2]; 740 /* latencies*/ 741 ktime_t lat_sum[2]; 742 ktime_t lat_max[2]; 743 ktime_t lat_min[2]; 744 745 u32 nr_queued[2]; 746 ktime_t busy_start_ts[2]; 747 748 ktime_t enabled_ts; 749 bool enabled; 750 }; 751 752 /** 753 * struct ufshcd_res_info_t - MCQ related resource regions 754 * 755 * @name: resource name 756 * @resource: pointer to resource region 757 * @base: register base address 758 */ 759 struct ufshcd_res_info { 760 const char *name; 761 struct resource *resource; 762 void __iomem *base; 763 }; 764 765 enum ufshcd_res { 766 RES_UFS, 767 RES_MCQ, 768 RES_MCQ_SQD, 769 RES_MCQ_SQIS, 770 RES_MCQ_CQD, 771 RES_MCQ_CQIS, 772 RES_MCQ_VS, 773 RES_MAX, 774 }; 775 776 /** 777 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers 778 * 779 * @offset: Doorbell Address Offset 780 * @stride: Steps proportional to queue [0...31] 781 * @base: base address 782 */ 783 struct ufshcd_mcq_opr_info_t { 784 unsigned long offset; 785 unsigned long stride; 786 void __iomem *base; 787 }; 788 789 enum ufshcd_mcq_opr { 790 OPR_SQD, 791 OPR_SQIS, 792 OPR_CQD, 793 OPR_CQIS, 794 OPR_MAX, 795 }; 796 797 /** 798 * struct ufs_hba - per adapter private structure 799 * @mmio_base: UFSHCI base register address 800 * @ucdl_base_addr: UFS Command Descriptor base address 801 * @utrdl_base_addr: UTP Transfer Request Descriptor base address 802 * @utmrdl_base_addr: UTP Task Management Descriptor base address 803 * @ucdl_dma_addr: UFS Command Descriptor DMA address 804 * @utrdl_dma_addr: UTRDL DMA address 805 * @utmrdl_dma_addr: UTMRDL DMA address 806 * @host: Scsi_Host instance of the driver 807 * @dev: device handle 808 * @ufs_device_wlun: WLUN that controls the entire UFS device. 809 * @hwmon_device: device instance registered with the hwmon core. 810 * @curr_dev_pwr_mode: active UFS device power mode. 811 * @uic_link_state: active state of the link to the UFS device. 812 * @rpm_lvl: desired UFS power management level during runtime PM. 813 * @spm_lvl: desired UFS power management level during system PM. 814 * @pm_op_in_progress: whether or not a PM operation is in progress. 815 * @ahit: value of Auto-Hibernate Idle Timer register. 816 * @lrb: local reference block 817 * @outstanding_tasks: Bits representing outstanding task requests 818 * @outstanding_lock: Protects @outstanding_reqs. 819 * @outstanding_reqs: Bits representing outstanding transfer requests 820 * @capabilities: UFS Controller Capabilities 821 * @mcq_capabilities: UFS Multi Circular Queue capabilities 822 * @nutrs: Transfer Request Queue depth supported by controller 823 * @nutmrs: Task Management Queue depth supported by controller 824 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. 825 * @ufs_version: UFS Version to which controller complies 826 * @vops: pointer to variant specific operations 827 * @vps: pointer to variant specific parameters 828 * @priv: pointer to variant specific private data 829 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) 830 * @irq: Irq number of the controller 831 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. 832 * @dev_ref_clk_freq: reference clock frequency 833 * @quirks: bitmask with information about deviations from the UFSHCI standard. 834 * @dev_quirks: bitmask with information about deviations from the UFS standard. 835 * @tmf_tag_set: TMF tag set. 836 * @tmf_queue: Used to allocate TMF tags. 837 * @tmf_rqs: array with pointers to TMF requests while these are in progress. 838 * @active_uic_cmd: handle of active UIC command 839 * @uic_cmd_mutex: mutex for UIC command 840 * @uic_async_done: completion used during UIC processing 841 * @ufshcd_state: UFSHCD state 842 * @eh_flags: Error handling flags 843 * @intr_mask: Interrupt Mask Bits 844 * @ee_ctrl_mask: Exception event control mask 845 * @ee_drv_mask: Exception event mask for driver 846 * @ee_usr_mask: Exception event mask for user (set via debugfs) 847 * @ee_ctrl_mutex: Used to serialize exception event information. 848 * @is_powered: flag to check if HBA is powered 849 * @shutting_down: flag to check if shutdown has been invoked 850 * @host_sem: semaphore used to serialize concurrent contexts 851 * @eh_wq: Workqueue that eh_work works on 852 * @eh_work: Worker to handle UFS errors that require s/w attention 853 * @eeh_work: Worker to handle exception events 854 * @errors: HBA errors 855 * @uic_error: UFS interconnect layer error status 856 * @saved_err: sticky error mask 857 * @saved_uic_err: sticky UIC error mask 858 * @ufs_stats: various error counters 859 * @force_reset: flag to force eh_work perform a full reset 860 * @force_pmc: flag to force a power mode change 861 * @silence_err_logs: flag to silence error logs 862 * @dev_cmd: ufs device management command information 863 * @last_dme_cmd_tstamp: time stamp of the last completed DME command 864 * @nop_out_timeout: NOP OUT timeout value 865 * @dev_info: information about the UFS device 866 * @auto_bkops_enabled: to track whether bkops is enabled in device 867 * @vreg_info: UFS device voltage regulator information 868 * @clk_list_head: UFS host controller clocks list node head 869 * @use_pm_opp: Indicates whether OPP based scaling is used or not 870 * @req_abort_count: number of times ufshcd_abort() has been called 871 * @lanes_per_direction: number of lanes per data direction between the UFS 872 * controller and the UFS device. 873 * @pwr_info: holds current power mode 874 * @max_pwr_info: keeps the device max valid pwm 875 * @clk_gating: information related to clock gating 876 * @caps: bitmask with information about UFS controller capabilities 877 * @devfreq: frequency scaling information owned by the devfreq core 878 * @clk_scaling: frequency scaling information owned by the UFS driver 879 * @system_suspending: system suspend has been started and system resume has 880 * not yet finished. 881 * @is_sys_suspended: UFS device has been suspended because of system suspend 882 * @urgent_bkops_lvl: keeps track of urgent bkops level for device 883 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for 884 * device is known or not. 885 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling 886 * @clk_scaling_lock: used to serialize device commands and clock scaling 887 * @desc_size: descriptor sizes reported by device 888 * @scsi_block_reqs_cnt: reference counting for scsi block requests 889 * @bsg_dev: struct device associated with the BSG queue 890 * @bsg_queue: BSG queue associated with the UFS controller 891 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power 892 * management) after the UFS device has finished a WriteBooster buffer 893 * flush or auto BKOP. 894 * @monitor: statistics about UFS commands 895 * @crypto_capabilities: Content of crypto capabilities register (0x100) 896 * @crypto_cap_array: Array of crypto capabilities 897 * @crypto_cfg_register: Start of the crypto cfg array 898 * @crypto_profile: the crypto profile of this hba (if applicable) 899 * @debugfs_root: UFS controller debugfs root directory 900 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay 901 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore 902 * ee_ctrl_mask 903 * @luns_avail: number of regular and well known LUNs supported by the UFS 904 * device 905 * @nr_hw_queues: number of hardware queues configured 906 * @nr_queues: number of Queues of different queue types 907 * @complete_put: whether or not to call ufshcd_rpm_put() from inside 908 * ufshcd_resume_complete() 909 * @ext_iid_sup: is EXT_IID is supported by UFSHC 910 * @mcq_sup: is mcq supported by UFSHC 911 * @mcq_enabled: is mcq ready to accept requests 912 * @res: array of resource info of MCQ registers 913 * @mcq_base: Multi circular queue registers base address 914 * @uhq: array of supported hardware queues 915 * @dev_cmd_queue: Queue for issuing device management commands 916 * @mcq_opr: MCQ operation and runtime registers 917 * @ufs_rtc_update_work: A work for UFS RTC periodic update 918 * @pm_qos_req: PM QoS request handle 919 * @pm_qos_enabled: flag to check if pm qos is enabled 920 */ 921 struct ufs_hba { 922 void __iomem *mmio_base; 923 924 /* Virtual memory reference */ 925 struct utp_transfer_cmd_desc *ucdl_base_addr; 926 struct utp_transfer_req_desc *utrdl_base_addr; 927 struct utp_task_req_desc *utmrdl_base_addr; 928 929 /* DMA memory reference */ 930 dma_addr_t ucdl_dma_addr; 931 dma_addr_t utrdl_dma_addr; 932 dma_addr_t utmrdl_dma_addr; 933 934 struct Scsi_Host *host; 935 struct device *dev; 936 struct scsi_device *ufs_device_wlun; 937 938 #ifdef CONFIG_SCSI_UFS_HWMON 939 struct device *hwmon_device; 940 #endif 941 942 enum ufs_dev_pwr_mode curr_dev_pwr_mode; 943 enum uic_link_state uic_link_state; 944 /* Desired UFS power management level during runtime PM */ 945 enum ufs_pm_level rpm_lvl; 946 /* Desired UFS power management level during system PM */ 947 enum ufs_pm_level spm_lvl; 948 int pm_op_in_progress; 949 950 /* Auto-Hibernate Idle Timer register value */ 951 u32 ahit; 952 953 struct ufshcd_lrb *lrb; 954 955 unsigned long outstanding_tasks; 956 spinlock_t outstanding_lock; 957 unsigned long outstanding_reqs; 958 959 u32 capabilities; 960 int nutrs; 961 u32 mcq_capabilities; 962 int nutmrs; 963 u32 reserved_slot; 964 u32 ufs_version; 965 const struct ufs_hba_variant_ops *vops; 966 struct ufs_hba_variant_params *vps; 967 void *priv; 968 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 969 size_t sg_entry_size; 970 #endif 971 unsigned int irq; 972 bool is_irq_enabled; 973 enum ufs_ref_clk_freq dev_ref_clk_freq; 974 975 unsigned int quirks; /* Deviations from standard UFSHCI spec. */ 976 977 /* Device deviations from standard UFS device spec. */ 978 unsigned int dev_quirks; 979 980 struct blk_mq_tag_set tmf_tag_set; 981 struct request_queue *tmf_queue; 982 struct request **tmf_rqs; 983 984 struct uic_command *active_uic_cmd; 985 struct mutex uic_cmd_mutex; 986 struct completion *uic_async_done; 987 988 enum ufshcd_state ufshcd_state; 989 u32 eh_flags; 990 u32 intr_mask; 991 u16 ee_ctrl_mask; 992 u16 ee_drv_mask; 993 u16 ee_usr_mask; 994 struct mutex ee_ctrl_mutex; 995 bool is_powered; 996 bool shutting_down; 997 struct semaphore host_sem; 998 999 /* Work Queues */ 1000 struct workqueue_struct *eh_wq; 1001 struct work_struct eh_work; 1002 struct work_struct eeh_work; 1003 1004 /* HBA Errors */ 1005 u32 errors; 1006 u32 uic_error; 1007 u32 saved_err; 1008 u32 saved_uic_err; 1009 struct ufs_stats ufs_stats; 1010 bool force_reset; 1011 bool force_pmc; 1012 bool silence_err_logs; 1013 1014 /* Device management request data */ 1015 struct ufs_dev_cmd dev_cmd; 1016 ktime_t last_dme_cmd_tstamp; 1017 int nop_out_timeout; 1018 1019 /* Keeps information of the UFS device connected to this host */ 1020 struct ufs_dev_info dev_info; 1021 bool auto_bkops_enabled; 1022 struct ufs_vreg_info vreg_info; 1023 struct list_head clk_list_head; 1024 bool use_pm_opp; 1025 1026 /* Number of requests aborts */ 1027 int req_abort_count; 1028 1029 /* Number of lanes available (1 or 2) for Rx/Tx */ 1030 u32 lanes_per_direction; 1031 struct ufs_pa_layer_attr pwr_info; 1032 struct ufs_pwr_mode_info max_pwr_info; 1033 1034 struct ufs_clk_gating clk_gating; 1035 /* Control to enable/disable host capabilities */ 1036 u32 caps; 1037 1038 struct devfreq *devfreq; 1039 struct ufs_clk_scaling clk_scaling; 1040 bool system_suspending; 1041 bool is_sys_suspended; 1042 1043 enum bkops_status urgent_bkops_lvl; 1044 bool is_urgent_bkops_lvl_checked; 1045 1046 struct mutex wb_mutex; 1047 struct rw_semaphore clk_scaling_lock; 1048 atomic_t scsi_block_reqs_cnt; 1049 1050 struct device bsg_dev; 1051 struct request_queue *bsg_queue; 1052 struct delayed_work rpm_dev_flush_recheck_work; 1053 1054 struct ufs_hba_monitor monitor; 1055 1056 #ifdef CONFIG_SCSI_UFS_CRYPTO 1057 union ufs_crypto_capabilities crypto_capabilities; 1058 union ufs_crypto_cap_entry *crypto_cap_array; 1059 u32 crypto_cfg_register; 1060 struct blk_crypto_profile crypto_profile; 1061 #endif 1062 #ifdef CONFIG_DEBUG_FS 1063 struct dentry *debugfs_root; 1064 struct delayed_work debugfs_ee_work; 1065 u32 debugfs_ee_rate_limit_ms; 1066 #endif 1067 #ifdef CONFIG_SCSI_UFS_FAULT_INJECTION 1068 struct fault_attr trigger_eh_attr; 1069 struct fault_attr timeout_attr; 1070 #endif 1071 u32 luns_avail; 1072 unsigned int nr_hw_queues; 1073 unsigned int nr_queues[HCTX_MAX_TYPES]; 1074 bool complete_put; 1075 bool ext_iid_sup; 1076 bool scsi_host_added; 1077 bool mcq_sup; 1078 bool mcq_enabled; 1079 struct ufshcd_res_info res[RES_MAX]; 1080 void __iomem *mcq_base; 1081 struct ufs_hw_queue *uhq; 1082 struct ufs_hw_queue *dev_cmd_queue; 1083 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX]; 1084 1085 struct delayed_work ufs_rtc_update_work; 1086 struct pm_qos_request pm_qos_req; 1087 bool pm_qos_enabled; 1088 }; 1089 1090 /** 1091 * struct ufs_hw_queue - per hardware queue structure 1092 * @mcq_sq_head: base address of submission queue head pointer 1093 * @mcq_sq_tail: base address of submission queue tail pointer 1094 * @mcq_cq_head: base address of completion queue head pointer 1095 * @mcq_cq_tail: base address of completion queue tail pointer 1096 * @sqe_base_addr: submission queue entry base address 1097 * @sqe_dma_addr: submission queue dma address 1098 * @cqe_base_addr: completion queue base address 1099 * @cqe_dma_addr: completion queue dma address 1100 * @max_entries: max number of slots in this hardware queue 1101 * @id: hardware queue ID 1102 * @sq_tp_slot: current slot to which SQ tail pointer is pointing 1103 * @sq_lock: serialize submission queue access 1104 * @cq_tail_slot: current slot to which CQ tail pointer is pointing 1105 * @cq_head_slot: current slot to which CQ head pointer is pointing 1106 * @cq_lock: Synchronize between multiple polling instances 1107 * @sq_mutex: prevent submission queue concurrent access 1108 */ 1109 struct ufs_hw_queue { 1110 void __iomem *mcq_sq_head; 1111 void __iomem *mcq_sq_tail; 1112 void __iomem *mcq_cq_head; 1113 void __iomem *mcq_cq_tail; 1114 1115 struct utp_transfer_req_desc *sqe_base_addr; 1116 dma_addr_t sqe_dma_addr; 1117 struct cq_entry *cqe_base_addr; 1118 dma_addr_t cqe_dma_addr; 1119 u32 max_entries; 1120 u32 id; 1121 u32 sq_tail_slot; 1122 spinlock_t sq_lock; 1123 u32 cq_tail_slot; 1124 u32 cq_head_slot; 1125 spinlock_t cq_lock; 1126 /* prevent concurrent access to submission queue */ 1127 struct mutex sq_mutex; 1128 }; 1129 1130 static inline bool is_mcq_enabled(struct ufs_hba *hba) 1131 { 1132 return hba->mcq_enabled; 1133 } 1134 1135 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 1136 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1137 { 1138 return hba->sg_entry_size; 1139 } 1140 1141 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) 1142 { 1143 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); 1144 hba->sg_entry_size = sg_entry_size; 1145 } 1146 #else 1147 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1148 { 1149 return sizeof(struct ufshcd_sg_entry); 1150 } 1151 1152 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ 1153 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) 1154 #endif 1155 1156 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba) 1157 { 1158 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); 1159 } 1160 1161 /* Returns true if clocks can be gated. Otherwise false */ 1162 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) 1163 { 1164 return hba->caps & UFSHCD_CAP_CLK_GATING; 1165 } 1166 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) 1167 { 1168 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1169 } 1170 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) 1171 { 1172 return hba->caps & UFSHCD_CAP_CLK_SCALING; 1173 } 1174 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 1175 { 1176 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1177 } 1178 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) 1179 { 1180 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; 1181 } 1182 1183 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) 1184 { 1185 return (hba->caps & UFSHCD_CAP_INTR_AGGR) && 1186 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); 1187 } 1188 1189 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) 1190 { 1191 return !!(ufshcd_is_link_hibern8(hba) && 1192 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); 1193 } 1194 1195 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) 1196 { 1197 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && 1198 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); 1199 } 1200 1201 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) 1202 { 1203 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); 1204 } 1205 1206 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) 1207 { 1208 return hba->caps & UFSHCD_CAP_WB_EN; 1209 } 1210 1211 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) 1212 { 1213 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; 1214 } 1215 1216 #define ufsmcq_writel(hba, val, reg) \ 1217 writel((val), (hba)->mcq_base + (reg)) 1218 #define ufsmcq_readl(hba, reg) \ 1219 readl((hba)->mcq_base + (reg)) 1220 1221 #define ufsmcq_writelx(hba, val, reg) \ 1222 writel_relaxed((val), (hba)->mcq_base + (reg)) 1223 #define ufsmcq_readlx(hba, reg) \ 1224 readl_relaxed((hba)->mcq_base + (reg)) 1225 1226 #define ufshcd_writel(hba, val, reg) \ 1227 writel((val), (hba)->mmio_base + (reg)) 1228 #define ufshcd_readl(hba, reg) \ 1229 readl((hba)->mmio_base + (reg)) 1230 1231 /** 1232 * ufshcd_rmwl - perform read/modify/write for a controller register 1233 * @hba: per adapter instance 1234 * @mask: mask to apply on read value 1235 * @val: actual value to write 1236 * @reg: register address 1237 */ 1238 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 1239 { 1240 u32 tmp; 1241 1242 tmp = ufshcd_readl(hba, reg); 1243 tmp &= ~mask; 1244 tmp |= (val & mask); 1245 ufshcd_writel(hba, tmp, reg); 1246 } 1247 1248 void ufshcd_enable_irq(struct ufs_hba *hba); 1249 void ufshcd_disable_irq(struct ufs_hba *hba); 1250 int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1251 void ufshcd_dealloc_host(struct ufs_hba *); 1252 int ufshcd_hba_enable(struct ufs_hba *hba); 1253 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); 1254 int ufshcd_link_recovery(struct ufs_hba *hba); 1255 int ufshcd_make_hba_operational(struct ufs_hba *hba); 1256 void ufshcd_remove(struct ufs_hba *); 1257 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); 1258 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); 1259 void ufshcd_delay_us(unsigned long us, unsigned long tolerance); 1260 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); 1261 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); 1262 void ufshcd_hba_stop(struct ufs_hba *hba); 1263 void ufshcd_schedule_eh_work(struct ufs_hba *hba); 1264 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); 1265 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); 1266 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); 1267 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, 1268 struct ufs_hw_queue *hwq); 1269 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); 1270 void ufshcd_mcq_enable_esi(struct ufs_hba *hba); 1271 void ufshcd_mcq_enable(struct ufs_hba *hba); 1272 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); 1273 1274 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1275 struct dev_pm_opp *opp, void *data, 1276 bool scaling_down); 1277 /** 1278 * ufshcd_set_variant - set variant specific data to the hba 1279 * @hba: per adapter instance 1280 * @variant: pointer to variant specific data 1281 */ 1282 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) 1283 { 1284 BUG_ON(!hba); 1285 hba->priv = variant; 1286 } 1287 1288 /** 1289 * ufshcd_get_variant - get variant specific data from the hba 1290 * @hba: per adapter instance 1291 */ 1292 static inline void *ufshcd_get_variant(struct ufs_hba *hba) 1293 { 1294 BUG_ON(!hba); 1295 return hba->priv; 1296 } 1297 1298 #ifdef CONFIG_PM 1299 extern int ufshcd_runtime_suspend(struct device *dev); 1300 extern int ufshcd_runtime_resume(struct device *dev); 1301 #endif 1302 #ifdef CONFIG_PM_SLEEP 1303 extern int ufshcd_system_suspend(struct device *dev); 1304 extern int ufshcd_system_resume(struct device *dev); 1305 extern int ufshcd_system_freeze(struct device *dev); 1306 extern int ufshcd_system_thaw(struct device *dev); 1307 extern int ufshcd_system_restore(struct device *dev); 1308 #endif 1309 1310 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 1311 int agreed_gear, 1312 int adapt_val); 1313 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 1314 u8 attr_set, u32 mib_val, u8 peer); 1315 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 1316 u32 *mib_val, u8 peer); 1317 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, 1318 struct ufs_pa_layer_attr *desired_pwr_mode); 1319 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); 1320 1321 /* UIC command interfaces for DME primitives */ 1322 #define DME_LOCAL 0 1323 #define DME_PEER 1 1324 #define ATTR_SET_NOR 0 /* NORMAL */ 1325 #define ATTR_SET_ST 1 /* STATIC */ 1326 1327 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 1328 u32 mib_val) 1329 { 1330 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1331 mib_val, DME_LOCAL); 1332 } 1333 1334 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, 1335 u32 mib_val) 1336 { 1337 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1338 mib_val, DME_LOCAL); 1339 } 1340 1341 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 1342 u32 mib_val) 1343 { 1344 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1345 mib_val, DME_PEER); 1346 } 1347 1348 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, 1349 u32 mib_val) 1350 { 1351 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1352 mib_val, DME_PEER); 1353 } 1354 1355 static inline int ufshcd_dme_get(struct ufs_hba *hba, 1356 u32 attr_sel, u32 *mib_val) 1357 { 1358 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 1359 } 1360 1361 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 1362 u32 attr_sel, u32 *mib_val) 1363 { 1364 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 1365 } 1366 1367 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) 1368 { 1369 return (pwr_info->pwr_rx == FAST_MODE || 1370 pwr_info->pwr_rx == FASTAUTO_MODE) && 1371 (pwr_info->pwr_tx == FAST_MODE || 1372 pwr_info->pwr_tx == FASTAUTO_MODE); 1373 } 1374 1375 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) 1376 { 1377 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); 1378 } 1379 1380 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); 1381 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 1382 const struct ufs_dev_quirk *fixups); 1383 #define SD_ASCII_STD true 1384 #define SD_RAW false 1385 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 1386 u8 **buf, bool ascii); 1387 1388 void ufshcd_hold(struct ufs_hba *hba); 1389 void ufshcd_release(struct ufs_hba *hba); 1390 1391 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); 1392 1393 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); 1394 1395 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); 1396 1397 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); 1398 1399 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 1400 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, 1401 struct ufs_ehs *ehs_rsp, int sg_cnt, 1402 struct scatterlist *sg_list, enum dma_data_direction dir); 1403 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); 1404 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); 1405 int ufshcd_suspend_prepare(struct device *dev); 1406 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); 1407 void ufshcd_resume_complete(struct device *dev); 1408 bool ufshcd_is_hba_active(struct ufs_hba *hba); 1409 void ufshcd_pm_qos_init(struct ufs_hba *hba); 1410 void ufshcd_pm_qos_exit(struct ufs_hba *hba); 1411 1412 /* Wrapper functions for safely calling variant operations */ 1413 static inline int ufshcd_vops_init(struct ufs_hba *hba) 1414 { 1415 if (hba->vops && hba->vops->init) 1416 return hba->vops->init(hba); 1417 1418 return 0; 1419 } 1420 1421 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) 1422 { 1423 if (hba->vops && hba->vops->phy_initialization) 1424 return hba->vops->phy_initialization(hba); 1425 1426 return 0; 1427 } 1428 1429 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; 1430 1431 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1432 const char *prefix); 1433 1434 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); 1435 int ufshcd_write_ee_control(struct ufs_hba *hba); 1436 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 1437 const u16 *other_mask, u16 set, u16 clr); 1438 1439 #endif /* End of Header */ 1440