1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #ifndef _UFSHCD_H 13 #define _UFSHCD_H 14 15 #include <linux/bitfield.h> 16 #include <linux/blk-crypto-profile.h> 17 #include <linux/blk-mq.h> 18 #include <linux/devfreq.h> 19 #include <linux/fault-inject.h> 20 #include <linux/msi.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/dma-direction.h> 23 #include <scsi/scsi_device.h> 24 #include <scsi/scsi_host.h> 25 #include <ufs/unipro.h> 26 #include <ufs/ufs.h> 27 #include <ufs/ufs_quirks.h> 28 #include <ufs/ufshci.h> 29 30 #define UFSHCD "ufshcd" 31 32 struct scsi_device; 33 struct ufs_hba; 34 35 enum dev_cmd_type { 36 DEV_CMD_TYPE_NOP = 0x0, 37 DEV_CMD_TYPE_QUERY = 0x1, 38 DEV_CMD_TYPE_RPMB = 0x2, 39 }; 40 41 enum ufs_event_type { 42 /* uic specific errors */ 43 UFS_EVT_PA_ERR = 0, 44 UFS_EVT_DL_ERR, 45 UFS_EVT_NL_ERR, 46 UFS_EVT_TL_ERR, 47 UFS_EVT_DME_ERR, 48 49 /* fatal errors */ 50 UFS_EVT_AUTO_HIBERN8_ERR, 51 UFS_EVT_FATAL_ERR, 52 UFS_EVT_LINK_STARTUP_FAIL, 53 UFS_EVT_RESUME_ERR, 54 UFS_EVT_SUSPEND_ERR, 55 UFS_EVT_WL_SUSP_ERR, 56 UFS_EVT_WL_RES_ERR, 57 58 /* abnormal events */ 59 UFS_EVT_DEV_RESET, 60 UFS_EVT_HOST_RESET, 61 UFS_EVT_ABORT, 62 63 UFS_EVT_CNT, 64 }; 65 66 /** 67 * struct uic_command - UIC command structure 68 * @command: UIC command 69 * @argument1: UIC command argument 1 70 * @argument2: UIC command argument 2 71 * @argument3: UIC command argument 3 72 * @cmd_active: Indicate if UIC command is outstanding 73 * @done: UIC command completion 74 */ 75 struct uic_command { 76 u32 command; 77 u32 argument1; 78 u32 argument2; 79 u32 argument3; 80 int cmd_active; 81 struct completion done; 82 }; 83 84 /* Used to differentiate the power management options */ 85 enum ufs_pm_op { 86 UFS_RUNTIME_PM, 87 UFS_SYSTEM_PM, 88 UFS_SHUTDOWN_PM, 89 }; 90 91 /* Host <-> Device UniPro Link state */ 92 enum uic_link_state { 93 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 94 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 95 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 96 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ 97 }; 98 99 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) 100 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ 101 UIC_LINK_ACTIVE_STATE) 102 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ 103 UIC_LINK_HIBERN8_STATE) 104 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ 105 UIC_LINK_BROKEN_STATE) 106 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) 107 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ 108 UIC_LINK_ACTIVE_STATE) 109 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ 110 UIC_LINK_HIBERN8_STATE) 111 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ 112 UIC_LINK_BROKEN_STATE) 113 114 #define ufshcd_set_ufs_dev_active(h) \ 115 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) 116 #define ufshcd_set_ufs_dev_sleep(h) \ 117 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) 118 #define ufshcd_set_ufs_dev_poweroff(h) \ 119 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) 120 #define ufshcd_set_ufs_dev_deepsleep(h) \ 121 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) 122 #define ufshcd_is_ufs_dev_active(h) \ 123 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) 124 #define ufshcd_is_ufs_dev_sleep(h) \ 125 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) 126 #define ufshcd_is_ufs_dev_poweroff(h) \ 127 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) 128 #define ufshcd_is_ufs_dev_deepsleep(h) \ 129 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) 130 131 /* 132 * UFS Power management levels. 133 * Each level is in increasing order of power savings, except DeepSleep 134 * which is lower than PowerDown with power on but not PowerDown with 135 * power off. 136 */ 137 enum ufs_pm_level { 138 UFS_PM_LVL_0, 139 UFS_PM_LVL_1, 140 UFS_PM_LVL_2, 141 UFS_PM_LVL_3, 142 UFS_PM_LVL_4, 143 UFS_PM_LVL_5, 144 UFS_PM_LVL_6, 145 UFS_PM_LVL_MAX 146 }; 147 148 struct ufs_pm_lvl_states { 149 enum ufs_dev_pwr_mode dev_state; 150 enum uic_link_state link_state; 151 }; 152 153 /** 154 * struct ufshcd_lrb - local reference block 155 * @utr_descriptor_ptr: UTRD address of the command 156 * @ucd_req_ptr: UCD address of the command 157 * @ucd_rsp_ptr: Response UPIU address for this command 158 * @ucd_prdt_ptr: PRDT address of the command 159 * @utrd_dma_addr: UTRD dma address for debug 160 * @ucd_prdt_dma_addr: PRDT dma address for debug 161 * @ucd_rsp_dma_addr: UPIU response dma address for debug 162 * @ucd_req_dma_addr: UPIU request dma address for debug 163 * @cmd: pointer to SCSI command 164 * @scsi_status: SCSI status of the command 165 * @command_type: SCSI, UFS, Query. 166 * @task_tag: Task tag of the command 167 * @lun: LUN of the command 168 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) 169 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) 170 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) 171 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) 172 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) 173 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) 174 * @data_unit_num: the data unit number for the first block for inline crypto 175 * @req_abort_skip: skip request abort task flag 176 */ 177 struct ufshcd_lrb { 178 struct utp_transfer_req_desc *utr_descriptor_ptr; 179 struct utp_upiu_req *ucd_req_ptr; 180 struct utp_upiu_rsp *ucd_rsp_ptr; 181 struct ufshcd_sg_entry *ucd_prdt_ptr; 182 183 dma_addr_t utrd_dma_addr; 184 dma_addr_t ucd_req_dma_addr; 185 dma_addr_t ucd_rsp_dma_addr; 186 dma_addr_t ucd_prdt_dma_addr; 187 188 struct scsi_cmnd *cmd; 189 int scsi_status; 190 191 int command_type; 192 int task_tag; 193 u8 lun; /* UPIU LUN id field is only 8-bit wide */ 194 bool intr_cmd; 195 ktime_t issue_time_stamp; 196 u64 issue_time_stamp_local_clock; 197 ktime_t compl_time_stamp; 198 u64 compl_time_stamp_local_clock; 199 #ifdef CONFIG_SCSI_UFS_CRYPTO 200 int crypto_key_slot; 201 u64 data_unit_num; 202 #endif 203 204 bool req_abort_skip; 205 }; 206 207 /** 208 * struct ufs_query_req - parameters for building a query request 209 * @query_func: UPIU header query function 210 * @upiu_req: the query request data 211 */ 212 struct ufs_query_req { 213 u8 query_func; 214 struct utp_upiu_query upiu_req; 215 }; 216 217 /** 218 * struct ufs_query_resp - UPIU QUERY 219 * @response: device response code 220 * @upiu_res: query response data 221 */ 222 struct ufs_query_res { 223 struct utp_upiu_query upiu_res; 224 }; 225 226 /** 227 * struct ufs_query - holds relevant data structures for query request 228 * @request: request upiu and function 229 * @descriptor: buffer for sending/receiving descriptor 230 * @response: response upiu and response 231 */ 232 struct ufs_query { 233 struct ufs_query_req request; 234 u8 *descriptor; 235 struct ufs_query_res response; 236 }; 237 238 /** 239 * struct ufs_dev_cmd - all assosiated fields with device management commands 240 * @type: device management command type - Query, NOP OUT 241 * @lock: lock to allow one command at a time 242 * @complete: internal commands completion 243 * @query: Device management query information 244 */ 245 struct ufs_dev_cmd { 246 enum dev_cmd_type type; 247 struct mutex lock; 248 struct completion *complete; 249 struct ufs_query query; 250 }; 251 252 /** 253 * struct ufs_clk_info - UFS clock related info 254 * @list: list headed by hba->clk_list_head 255 * @clk: clock node 256 * @name: clock name 257 * @max_freq: maximum frequency supported by the clock 258 * @min_freq: min frequency that can be used for clock scaling 259 * @curr_freq: indicates the current frequency that it is set to 260 * @keep_link_active: indicates that the clk should not be disabled if 261 * link is active 262 * @enabled: variable to check against multiple enable/disable 263 */ 264 struct ufs_clk_info { 265 struct list_head list; 266 struct clk *clk; 267 const char *name; 268 u32 max_freq; 269 u32 min_freq; 270 u32 curr_freq; 271 bool keep_link_active; 272 bool enabled; 273 }; 274 275 enum ufs_notify_change_status { 276 PRE_CHANGE, 277 POST_CHANGE, 278 }; 279 280 struct ufs_pa_layer_attr { 281 u32 gear_rx; 282 u32 gear_tx; 283 u32 lane_rx; 284 u32 lane_tx; 285 u32 pwr_rx; 286 u32 pwr_tx; 287 u32 hs_rate; 288 }; 289 290 struct ufs_pwr_mode_info { 291 bool is_valid; 292 struct ufs_pa_layer_attr info; 293 }; 294 295 /** 296 * struct ufs_hba_variant_ops - variant specific callbacks 297 * @name: variant name 298 * @init: called when the driver is initialized 299 * @exit: called to cleanup everything done in init 300 * @get_ufs_hci_version: called to get UFS HCI version 301 * @clk_scale_notify: notifies that clks are scaled up/down 302 * @setup_clocks: called before touching any of the controller registers 303 * @hce_enable_notify: called before and after HCE enable bit is set to allow 304 * variant specific Uni-Pro initialization. 305 * @link_startup_notify: called before and after Link startup is carried out 306 * to allow variant specific Uni-Pro initialization. 307 * @pwr_change_notify: called before and after a power mode change 308 * is carried out to allow vendor spesific capabilities 309 * to be set. 310 * @setup_xfer_req: called before any transfer request is issued 311 * to set some things 312 * @setup_task_mgmt: called before any task management request is issued 313 * to set some things 314 * @hibern8_notify: called around hibern8 enter/exit 315 * @apply_dev_quirks: called to apply device specific quirks 316 * @fixup_dev_quirks: called to modify device specific quirks 317 * @suspend: called during host controller PM callback 318 * @resume: called during host controller PM callback 319 * @dbg_register_dump: used to dump controller debug information 320 * @phy_initialization: used to initialize phys 321 * @device_reset: called to issue a reset pulse on the UFS device 322 * @config_scaling_param: called to configure clock scaling parameters 323 * @program_key: program or evict an inline encryption key 324 * @event_notify: called to notify important events 325 * @reinit_notify: called to notify reinit of UFSHCD during max gear switch 326 * @mcq_config_resource: called to configure MCQ platform resources 327 * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode 328 * @op_runtime_config: called to config Operation and runtime regs Pointers 329 * @get_outstanding_cqs: called to get outstanding completion queues 330 * @config_esi: called to config Event Specific Interrupt 331 */ 332 struct ufs_hba_variant_ops { 333 const char *name; 334 int (*init)(struct ufs_hba *); 335 void (*exit)(struct ufs_hba *); 336 u32 (*get_ufs_hci_version)(struct ufs_hba *); 337 int (*clk_scale_notify)(struct ufs_hba *, bool, 338 enum ufs_notify_change_status); 339 int (*setup_clocks)(struct ufs_hba *, bool, 340 enum ufs_notify_change_status); 341 int (*hce_enable_notify)(struct ufs_hba *, 342 enum ufs_notify_change_status); 343 int (*link_startup_notify)(struct ufs_hba *, 344 enum ufs_notify_change_status); 345 int (*pwr_change_notify)(struct ufs_hba *, 346 enum ufs_notify_change_status status, 347 struct ufs_pa_layer_attr *, 348 struct ufs_pa_layer_attr *); 349 void (*setup_xfer_req)(struct ufs_hba *hba, int tag, 350 bool is_scsi_cmd); 351 void (*setup_task_mgmt)(struct ufs_hba *, int, u8); 352 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, 353 enum ufs_notify_change_status); 354 int (*apply_dev_quirks)(struct ufs_hba *hba); 355 void (*fixup_dev_quirks)(struct ufs_hba *hba); 356 int (*suspend)(struct ufs_hba *, enum ufs_pm_op, 357 enum ufs_notify_change_status); 358 int (*resume)(struct ufs_hba *, enum ufs_pm_op); 359 void (*dbg_register_dump)(struct ufs_hba *hba); 360 int (*phy_initialization)(struct ufs_hba *); 361 int (*device_reset)(struct ufs_hba *hba); 362 void (*config_scaling_param)(struct ufs_hba *hba, 363 struct devfreq_dev_profile *profile, 364 struct devfreq_simple_ondemand_data *data); 365 int (*program_key)(struct ufs_hba *hba, 366 const union ufs_crypto_cfg_entry *cfg, int slot); 367 void (*event_notify)(struct ufs_hba *hba, 368 enum ufs_event_type evt, void *data); 369 void (*reinit_notify)(struct ufs_hba *); 370 int (*mcq_config_resource)(struct ufs_hba *hba); 371 int (*get_hba_mac)(struct ufs_hba *hba); 372 int (*op_runtime_config)(struct ufs_hba *hba); 373 int (*get_outstanding_cqs)(struct ufs_hba *hba, 374 unsigned long *ocqs); 375 int (*config_esi)(struct ufs_hba *hba); 376 void (*config_scsi_dev)(struct scsi_device *sdev); 377 }; 378 379 /* clock gating state */ 380 enum clk_gating_state { 381 CLKS_OFF, 382 CLKS_ON, 383 REQ_CLKS_OFF, 384 REQ_CLKS_ON, 385 }; 386 387 /** 388 * struct ufs_clk_gating - UFS clock gating related info 389 * @gate_work: worker to turn off clocks after some delay as specified in 390 * delay_ms 391 * @ungate_work: worker to turn on clocks that will be used in case of 392 * interrupt context 393 * @state: the current clocks state 394 * @delay_ms: gating delay in ms 395 * @is_suspended: clk gating is suspended when set to 1 which can be used 396 * during suspend/resume 397 * @delay_attr: sysfs attribute to control delay_attr 398 * @enable_attr: sysfs attribute to enable/disable clock gating 399 * @is_enabled: Indicates the current status of clock gating 400 * @is_initialized: Indicates whether clock gating is initialized or not 401 * @active_reqs: number of requests that are pending and should be waited for 402 * completion before gating clocks. 403 * @clk_gating_workq: workqueue for clock gating work. 404 */ 405 struct ufs_clk_gating { 406 struct delayed_work gate_work; 407 struct work_struct ungate_work; 408 enum clk_gating_state state; 409 unsigned long delay_ms; 410 bool is_suspended; 411 struct device_attribute delay_attr; 412 struct device_attribute enable_attr; 413 bool is_enabled; 414 bool is_initialized; 415 int active_reqs; 416 struct workqueue_struct *clk_gating_workq; 417 }; 418 419 /** 420 * struct ufs_clk_scaling - UFS clock scaling related data 421 * @active_reqs: number of requests that are pending. If this is zero when 422 * devfreq ->target() function is called then schedule "suspend_work" to 423 * suspend devfreq. 424 * @tot_busy_t: Total busy time in current polling window 425 * @window_start_t: Start time (in jiffies) of the current polling window 426 * @busy_start_t: Start time of current busy period 427 * @enable_attr: sysfs attribute to enable/disable clock scaling 428 * @saved_pwr_info: UFS power mode may also be changed during scaling and this 429 * one keeps track of previous power mode. 430 * @workq: workqueue to schedule devfreq suspend/resume work 431 * @suspend_work: worker to suspend devfreq 432 * @resume_work: worker to resume devfreq 433 * @target_freq: frequency requested by devfreq framework 434 * @min_gear: lowest HS gear to scale down to 435 * @is_enabled: tracks if scaling is currently enabled or not, controlled by 436 * clkscale_enable sysfs node 437 * @is_allowed: tracks if scaling is currently allowed or not, used to block 438 * clock scaling which is not invoked from devfreq governor 439 * @is_initialized: Indicates whether clock scaling is initialized or not 440 * @is_busy_started: tracks if busy period has started or not 441 * @is_suspended: tracks if devfreq is suspended or not 442 */ 443 struct ufs_clk_scaling { 444 int active_reqs; 445 unsigned long tot_busy_t; 446 ktime_t window_start_t; 447 ktime_t busy_start_t; 448 struct device_attribute enable_attr; 449 struct ufs_pa_layer_attr saved_pwr_info; 450 struct workqueue_struct *workq; 451 struct work_struct suspend_work; 452 struct work_struct resume_work; 453 unsigned long target_freq; 454 u32 min_gear; 455 bool is_enabled; 456 bool is_allowed; 457 bool is_initialized; 458 bool is_busy_started; 459 bool is_suspended; 460 }; 461 462 #define UFS_EVENT_HIST_LENGTH 8 463 /** 464 * struct ufs_event_hist - keeps history of errors 465 * @pos: index to indicate cyclic buffer position 466 * @val: cyclic buffer for registers value 467 * @tstamp: cyclic buffer for time stamp 468 * @cnt: error counter 469 */ 470 struct ufs_event_hist { 471 int pos; 472 u32 val[UFS_EVENT_HIST_LENGTH]; 473 u64 tstamp[UFS_EVENT_HIST_LENGTH]; 474 unsigned long long cnt; 475 }; 476 477 /** 478 * struct ufs_stats - keeps usage/err statistics 479 * @last_intr_status: record the last interrupt status. 480 * @last_intr_ts: record the last interrupt timestamp. 481 * @hibern8_exit_cnt: Counter to keep track of number of exits, 482 * reset this after link-startup. 483 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. 484 * Clear after the first successful command completion. 485 * @event: array with event history. 486 */ 487 struct ufs_stats { 488 u32 last_intr_status; 489 u64 last_intr_ts; 490 491 u32 hibern8_exit_cnt; 492 u64 last_hibern8_exit_tstamp; 493 struct ufs_event_hist event[UFS_EVT_CNT]; 494 }; 495 496 /** 497 * enum ufshcd_state - UFS host controller state 498 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command 499 * processing. 500 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process 501 * SCSI commands. 502 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. 503 * SCSI commands may be submitted to the controller. 504 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail 505 * newly submitted SCSI commands with error code DID_BAD_TARGET. 506 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery 507 * failed. Fail all SCSI commands with error code DID_ERROR. 508 */ 509 enum ufshcd_state { 510 UFSHCD_STATE_RESET, 511 UFSHCD_STATE_OPERATIONAL, 512 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, 513 UFSHCD_STATE_EH_SCHEDULED_FATAL, 514 UFSHCD_STATE_ERROR, 515 }; 516 517 enum ufshcd_quirks { 518 /* Interrupt aggregation support is broken */ 519 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, 520 521 /* 522 * delay before each dme command is required as the unipro 523 * layer has shown instabilities 524 */ 525 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, 526 527 /* 528 * If UFS host controller is having issue in processing LCC (Line 529 * Control Command) coming from device then enable this quirk. 530 * When this quirk is enabled, host controller driver should disable 531 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 532 * attribute of device to 0). 533 */ 534 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, 535 536 /* 537 * The attribute PA_RXHSUNTERMCAP specifies whether or not the 538 * inbound Link supports unterminated line in HS mode. Setting this 539 * attribute to 1 fixes moving to HS gear. 540 */ 541 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, 542 543 /* 544 * This quirk needs to be enabled if the host controller only allows 545 * accessing the peer dme attributes in AUTO mode (FAST AUTO or 546 * SLOW AUTO). 547 */ 548 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, 549 550 /* 551 * This quirk needs to be enabled if the host controller doesn't 552 * advertise the correct version in UFS_VER register. If this quirk 553 * is enabled, standard UFS host driver will call the vendor specific 554 * ops (get_ufs_hci_version) to get the correct version. 555 */ 556 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, 557 558 /* 559 * Clear handling for transfer/task request list is just opposite. 560 */ 561 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, 562 563 /* 564 * This quirk needs to be enabled if host controller doesn't allow 565 * that the interrupt aggregation timer and counter are reset by s/w. 566 */ 567 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, 568 569 /* 570 * This quirks needs to be enabled if host controller cannot be 571 * enabled via HCE register. 572 */ 573 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, 574 575 /* 576 * This quirk needs to be enabled if the host controller regards 577 * resolution of the values of PRDTO and PRDTL in UTRD as byte. 578 */ 579 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, 580 581 /* 582 * This quirk needs to be enabled if the host controller reports 583 * OCS FATAL ERROR with device error through sense data 584 */ 585 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, 586 587 /* 588 * This quirk needs to be enabled if the host controller has 589 * auto-hibernate capability but it doesn't work. 590 */ 591 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, 592 593 /* 594 * This quirk needs to disable manual flush for write booster 595 */ 596 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, 597 598 /* 599 * This quirk needs to disable unipro timeout values 600 * before power mode change 601 */ 602 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, 603 604 /* 605 * This quirk needs to be enabled if the host controller does not 606 * support UIC command 607 */ 608 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, 609 610 /* 611 * This quirk needs to be enabled if the host controller cannot 612 * support physical host configuration. 613 */ 614 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, 615 616 /* 617 * This quirk needs to be enabled if the host controller has 618 * 64-bit addressing supported capability but it doesn't work. 619 */ 620 UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, 621 622 /* 623 * This quirk needs to be enabled if the host controller has 624 * auto-hibernate capability but it's FASTAUTO only. 625 */ 626 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, 627 628 /* 629 * This quirk needs to be enabled if the host controller needs 630 * to reinit the device after switching to maximum gear. 631 */ 632 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, 633 634 /* 635 * Some host raises interrupt (per queue) in addition to 636 * CQES (traditional) when ESI is disabled. 637 * Enable this quirk will disable CQES and use per queue interrupt. 638 */ 639 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20, 640 641 /* 642 * Some host does not implement SQ Run Time Command (SQRTC) register 643 * thus need this quirk to skip related flow. 644 */ 645 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21, 646 }; 647 648 enum ufshcd_caps { 649 /* Allow dynamic clk gating */ 650 UFSHCD_CAP_CLK_GATING = 1 << 0, 651 652 /* Allow hiberb8 with clk gating */ 653 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, 654 655 /* Allow dynamic clk scaling */ 656 UFSHCD_CAP_CLK_SCALING = 1 << 2, 657 658 /* Allow auto bkops to enabled during runtime suspend */ 659 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, 660 661 /* 662 * This capability allows host controller driver to use the UFS HCI's 663 * interrupt aggregation capability. 664 * CAUTION: Enabling this might reduce overall UFS throughput. 665 */ 666 UFSHCD_CAP_INTR_AGGR = 1 << 4, 667 668 /* 669 * This capability allows the device auto-bkops to be always enabled 670 * except during suspend (both runtime and suspend). 671 * Enabling this capability means that device will always be allowed 672 * to do background operation when it's active but it might degrade 673 * the performance of ongoing read/write operations. 674 */ 675 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, 676 677 /* 678 * This capability allows host controller driver to automatically 679 * enable runtime power management by itself instead of waiting 680 * for userspace to control the power management. 681 */ 682 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, 683 684 /* 685 * This capability allows the host controller driver to turn-on 686 * WriteBooster, if the underlying device supports it and is 687 * provisioned to be used. This would increase the write performance. 688 */ 689 UFSHCD_CAP_WB_EN = 1 << 7, 690 691 /* 692 * This capability allows the host controller driver to use the 693 * inline crypto engine, if it is present 694 */ 695 UFSHCD_CAP_CRYPTO = 1 << 8, 696 697 /* 698 * This capability allows the controller regulators to be put into 699 * lpm mode aggressively during clock gating. 700 * This would increase power savings. 701 */ 702 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, 703 704 /* 705 * This capability allows the host controller driver to use DeepSleep, 706 * if it is supported by the UFS device. The host controller driver must 707 * support device hardware reset via the hba->device_reset() callback, 708 * in order to exit DeepSleep state. 709 */ 710 UFSHCD_CAP_DEEPSLEEP = 1 << 10, 711 712 /* 713 * This capability allows the host controller driver to use temperature 714 * notification if it is supported by the UFS device. 715 */ 716 UFSHCD_CAP_TEMP_NOTIF = 1 << 11, 717 718 /* 719 * Enable WriteBooster when scaling up the clock and disable 720 * WriteBooster when scaling the clock down. 721 */ 722 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, 723 }; 724 725 struct ufs_hba_variant_params { 726 struct devfreq_dev_profile devfreq_profile; 727 struct devfreq_simple_ondemand_data ondemand_data; 728 u16 hba_enable_delay_us; 729 u32 wb_flush_threshold; 730 }; 731 732 struct ufs_hba_monitor { 733 unsigned long chunk_size; 734 735 unsigned long nr_sec_rw[2]; 736 ktime_t total_busy[2]; 737 738 unsigned long nr_req[2]; 739 /* latencies*/ 740 ktime_t lat_sum[2]; 741 ktime_t lat_max[2]; 742 ktime_t lat_min[2]; 743 744 u32 nr_queued[2]; 745 ktime_t busy_start_ts[2]; 746 747 ktime_t enabled_ts; 748 bool enabled; 749 }; 750 751 /** 752 * struct ufshcd_res_info_t - MCQ related resource regions 753 * 754 * @name: resource name 755 * @resource: pointer to resource region 756 * @base: register base address 757 */ 758 struct ufshcd_res_info { 759 const char *name; 760 struct resource *resource; 761 void __iomem *base; 762 }; 763 764 enum ufshcd_res { 765 RES_UFS, 766 RES_MCQ, 767 RES_MCQ_SQD, 768 RES_MCQ_SQIS, 769 RES_MCQ_CQD, 770 RES_MCQ_CQIS, 771 RES_MCQ_VS, 772 RES_MAX, 773 }; 774 775 /** 776 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers 777 * 778 * @offset: Doorbell Address Offset 779 * @stride: Steps proportional to queue [0...31] 780 * @base: base address 781 */ 782 struct ufshcd_mcq_opr_info_t { 783 unsigned long offset; 784 unsigned long stride; 785 void __iomem *base; 786 }; 787 788 enum ufshcd_mcq_opr { 789 OPR_SQD, 790 OPR_SQIS, 791 OPR_CQD, 792 OPR_CQIS, 793 OPR_MAX, 794 }; 795 796 /** 797 * struct ufs_hba - per adapter private structure 798 * @mmio_base: UFSHCI base register address 799 * @ucdl_base_addr: UFS Command Descriptor base address 800 * @utrdl_base_addr: UTP Transfer Request Descriptor base address 801 * @utmrdl_base_addr: UTP Task Management Descriptor base address 802 * @ucdl_dma_addr: UFS Command Descriptor DMA address 803 * @utrdl_dma_addr: UTRDL DMA address 804 * @utmrdl_dma_addr: UTMRDL DMA address 805 * @host: Scsi_Host instance of the driver 806 * @dev: device handle 807 * @ufs_device_wlun: WLUN that controls the entire UFS device. 808 * @hwmon_device: device instance registered with the hwmon core. 809 * @curr_dev_pwr_mode: active UFS device power mode. 810 * @uic_link_state: active state of the link to the UFS device. 811 * @rpm_lvl: desired UFS power management level during runtime PM. 812 * @spm_lvl: desired UFS power management level during system PM. 813 * @pm_op_in_progress: whether or not a PM operation is in progress. 814 * @ahit: value of Auto-Hibernate Idle Timer register. 815 * @lrb: local reference block 816 * @outstanding_tasks: Bits representing outstanding task requests 817 * @outstanding_lock: Protects @outstanding_reqs. 818 * @outstanding_reqs: Bits representing outstanding transfer requests 819 * @capabilities: UFS Controller Capabilities 820 * @mcq_capabilities: UFS Multi Circular Queue capabilities 821 * @nutrs: Transfer Request Queue depth supported by controller 822 * @nutmrs: Task Management Queue depth supported by controller 823 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. 824 * @ufs_version: UFS Version to which controller complies 825 * @vops: pointer to variant specific operations 826 * @vps: pointer to variant specific parameters 827 * @priv: pointer to variant specific private data 828 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) 829 * @irq: Irq number of the controller 830 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. 831 * @dev_ref_clk_freq: reference clock frequency 832 * @quirks: bitmask with information about deviations from the UFSHCI standard. 833 * @dev_quirks: bitmask with information about deviations from the UFS standard. 834 * @tmf_tag_set: TMF tag set. 835 * @tmf_queue: Used to allocate TMF tags. 836 * @tmf_rqs: array with pointers to TMF requests while these are in progress. 837 * @active_uic_cmd: handle of active UIC command 838 * @uic_cmd_mutex: mutex for UIC command 839 * @uic_async_done: completion used during UIC processing 840 * @ufshcd_state: UFSHCD state 841 * @eh_flags: Error handling flags 842 * @intr_mask: Interrupt Mask Bits 843 * @ee_ctrl_mask: Exception event control mask 844 * @ee_drv_mask: Exception event mask for driver 845 * @ee_usr_mask: Exception event mask for user (set via debugfs) 846 * @ee_ctrl_mutex: Used to serialize exception event information. 847 * @is_powered: flag to check if HBA is powered 848 * @shutting_down: flag to check if shutdown has been invoked 849 * @host_sem: semaphore used to serialize concurrent contexts 850 * @eh_wq: Workqueue that eh_work works on 851 * @eh_work: Worker to handle UFS errors that require s/w attention 852 * @eeh_work: Worker to handle exception events 853 * @errors: HBA errors 854 * @uic_error: UFS interconnect layer error status 855 * @saved_err: sticky error mask 856 * @saved_uic_err: sticky UIC error mask 857 * @ufs_stats: various error counters 858 * @force_reset: flag to force eh_work perform a full reset 859 * @force_pmc: flag to force a power mode change 860 * @silence_err_logs: flag to silence error logs 861 * @dev_cmd: ufs device management command information 862 * @last_dme_cmd_tstamp: time stamp of the last completed DME command 863 * @nop_out_timeout: NOP OUT timeout value 864 * @dev_info: information about the UFS device 865 * @auto_bkops_enabled: to track whether bkops is enabled in device 866 * @vreg_info: UFS device voltage regulator information 867 * @clk_list_head: UFS host controller clocks list node head 868 * @use_pm_opp: Indicates whether OPP based scaling is used or not 869 * @req_abort_count: number of times ufshcd_abort() has been called 870 * @lanes_per_direction: number of lanes per data direction between the UFS 871 * controller and the UFS device. 872 * @pwr_info: holds current power mode 873 * @max_pwr_info: keeps the device max valid pwm 874 * @clk_gating: information related to clock gating 875 * @caps: bitmask with information about UFS controller capabilities 876 * @devfreq: frequency scaling information owned by the devfreq core 877 * @clk_scaling: frequency scaling information owned by the UFS driver 878 * @system_suspending: system suspend has been started and system resume has 879 * not yet finished. 880 * @is_sys_suspended: UFS device has been suspended because of system suspend 881 * @urgent_bkops_lvl: keeps track of urgent bkops level for device 882 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for 883 * device is known or not. 884 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling 885 * @clk_scaling_lock: used to serialize device commands and clock scaling 886 * @desc_size: descriptor sizes reported by device 887 * @scsi_block_reqs_cnt: reference counting for scsi block requests 888 * @bsg_dev: struct device associated with the BSG queue 889 * @bsg_queue: BSG queue associated with the UFS controller 890 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power 891 * management) after the UFS device has finished a WriteBooster buffer 892 * flush or auto BKOP. 893 * @monitor: statistics about UFS commands 894 * @crypto_capabilities: Content of crypto capabilities register (0x100) 895 * @crypto_cap_array: Array of crypto capabilities 896 * @crypto_cfg_register: Start of the crypto cfg array 897 * @crypto_profile: the crypto profile of this hba (if applicable) 898 * @debugfs_root: UFS controller debugfs root directory 899 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay 900 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore 901 * ee_ctrl_mask 902 * @luns_avail: number of regular and well known LUNs supported by the UFS 903 * device 904 * @nr_hw_queues: number of hardware queues configured 905 * @nr_queues: number of Queues of different queue types 906 * @complete_put: whether or not to call ufshcd_rpm_put() from inside 907 * ufshcd_resume_complete() 908 * @ext_iid_sup: is EXT_IID is supported by UFSHC 909 * @mcq_sup: is mcq supported by UFSHC 910 * @mcq_enabled: is mcq ready to accept requests 911 * @res: array of resource info of MCQ registers 912 * @mcq_base: Multi circular queue registers base address 913 * @uhq: array of supported hardware queues 914 * @dev_cmd_queue: Queue for issuing device management commands 915 * @mcq_opr: MCQ operation and runtime registers 916 * @ufs_rtc_update_work: A work for UFS RTC periodic update 917 */ 918 struct ufs_hba { 919 void __iomem *mmio_base; 920 921 /* Virtual memory reference */ 922 struct utp_transfer_cmd_desc *ucdl_base_addr; 923 struct utp_transfer_req_desc *utrdl_base_addr; 924 struct utp_task_req_desc *utmrdl_base_addr; 925 926 /* DMA memory reference */ 927 dma_addr_t ucdl_dma_addr; 928 dma_addr_t utrdl_dma_addr; 929 dma_addr_t utmrdl_dma_addr; 930 931 struct Scsi_Host *host; 932 struct device *dev; 933 struct scsi_device *ufs_device_wlun; 934 935 #ifdef CONFIG_SCSI_UFS_HWMON 936 struct device *hwmon_device; 937 #endif 938 939 enum ufs_dev_pwr_mode curr_dev_pwr_mode; 940 enum uic_link_state uic_link_state; 941 /* Desired UFS power management level during runtime PM */ 942 enum ufs_pm_level rpm_lvl; 943 /* Desired UFS power management level during system PM */ 944 enum ufs_pm_level spm_lvl; 945 int pm_op_in_progress; 946 947 /* Auto-Hibernate Idle Timer register value */ 948 u32 ahit; 949 950 struct ufshcd_lrb *lrb; 951 952 unsigned long outstanding_tasks; 953 spinlock_t outstanding_lock; 954 unsigned long outstanding_reqs; 955 956 u32 capabilities; 957 int nutrs; 958 u32 mcq_capabilities; 959 int nutmrs; 960 u32 reserved_slot; 961 u32 ufs_version; 962 const struct ufs_hba_variant_ops *vops; 963 struct ufs_hba_variant_params *vps; 964 void *priv; 965 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 966 size_t sg_entry_size; 967 #endif 968 unsigned int irq; 969 bool is_irq_enabled; 970 enum ufs_ref_clk_freq dev_ref_clk_freq; 971 972 unsigned int quirks; /* Deviations from standard UFSHCI spec. */ 973 974 /* Device deviations from standard UFS device spec. */ 975 unsigned int dev_quirks; 976 977 struct blk_mq_tag_set tmf_tag_set; 978 struct request_queue *tmf_queue; 979 struct request **tmf_rqs; 980 981 struct uic_command *active_uic_cmd; 982 struct mutex uic_cmd_mutex; 983 struct completion *uic_async_done; 984 985 enum ufshcd_state ufshcd_state; 986 u32 eh_flags; 987 u32 intr_mask; 988 u16 ee_ctrl_mask; 989 u16 ee_drv_mask; 990 u16 ee_usr_mask; 991 struct mutex ee_ctrl_mutex; 992 bool is_powered; 993 bool shutting_down; 994 struct semaphore host_sem; 995 996 /* Work Queues */ 997 struct workqueue_struct *eh_wq; 998 struct work_struct eh_work; 999 struct work_struct eeh_work; 1000 1001 /* HBA Errors */ 1002 u32 errors; 1003 u32 uic_error; 1004 u32 saved_err; 1005 u32 saved_uic_err; 1006 struct ufs_stats ufs_stats; 1007 bool force_reset; 1008 bool force_pmc; 1009 bool silence_err_logs; 1010 1011 /* Device management request data */ 1012 struct ufs_dev_cmd dev_cmd; 1013 ktime_t last_dme_cmd_tstamp; 1014 int nop_out_timeout; 1015 1016 /* Keeps information of the UFS device connected to this host */ 1017 struct ufs_dev_info dev_info; 1018 bool auto_bkops_enabled; 1019 struct ufs_vreg_info vreg_info; 1020 struct list_head clk_list_head; 1021 bool use_pm_opp; 1022 1023 /* Number of requests aborts */ 1024 int req_abort_count; 1025 1026 /* Number of lanes available (1 or 2) for Rx/Tx */ 1027 u32 lanes_per_direction; 1028 struct ufs_pa_layer_attr pwr_info; 1029 struct ufs_pwr_mode_info max_pwr_info; 1030 1031 struct ufs_clk_gating clk_gating; 1032 /* Control to enable/disable host capabilities */ 1033 u32 caps; 1034 1035 struct devfreq *devfreq; 1036 struct ufs_clk_scaling clk_scaling; 1037 bool system_suspending; 1038 bool is_sys_suspended; 1039 1040 enum bkops_status urgent_bkops_lvl; 1041 bool is_urgent_bkops_lvl_checked; 1042 1043 struct mutex wb_mutex; 1044 struct rw_semaphore clk_scaling_lock; 1045 atomic_t scsi_block_reqs_cnt; 1046 1047 struct device bsg_dev; 1048 struct request_queue *bsg_queue; 1049 struct delayed_work rpm_dev_flush_recheck_work; 1050 1051 struct ufs_hba_monitor monitor; 1052 1053 #ifdef CONFIG_SCSI_UFS_CRYPTO 1054 union ufs_crypto_capabilities crypto_capabilities; 1055 union ufs_crypto_cap_entry *crypto_cap_array; 1056 u32 crypto_cfg_register; 1057 struct blk_crypto_profile crypto_profile; 1058 #endif 1059 #ifdef CONFIG_DEBUG_FS 1060 struct dentry *debugfs_root; 1061 struct delayed_work debugfs_ee_work; 1062 u32 debugfs_ee_rate_limit_ms; 1063 #endif 1064 #ifdef CONFIG_SCSI_UFS_FAULT_INJECTION 1065 struct fault_attr trigger_eh_attr; 1066 struct fault_attr timeout_attr; 1067 #endif 1068 u32 luns_avail; 1069 unsigned int nr_hw_queues; 1070 unsigned int nr_queues[HCTX_MAX_TYPES]; 1071 bool complete_put; 1072 bool ext_iid_sup; 1073 bool scsi_host_added; 1074 bool mcq_sup; 1075 bool mcq_enabled; 1076 struct ufshcd_res_info res[RES_MAX]; 1077 void __iomem *mcq_base; 1078 struct ufs_hw_queue *uhq; 1079 struct ufs_hw_queue *dev_cmd_queue; 1080 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX]; 1081 1082 struct delayed_work ufs_rtc_update_work; 1083 }; 1084 1085 /** 1086 * struct ufs_hw_queue - per hardware queue structure 1087 * @mcq_sq_head: base address of submission queue head pointer 1088 * @mcq_sq_tail: base address of submission queue tail pointer 1089 * @mcq_cq_head: base address of completion queue head pointer 1090 * @mcq_cq_tail: base address of completion queue tail pointer 1091 * @sqe_base_addr: submission queue entry base address 1092 * @sqe_dma_addr: submission queue dma address 1093 * @cqe_base_addr: completion queue base address 1094 * @cqe_dma_addr: completion queue dma address 1095 * @max_entries: max number of slots in this hardware queue 1096 * @id: hardware queue ID 1097 * @sq_tp_slot: current slot to which SQ tail pointer is pointing 1098 * @sq_lock: serialize submission queue access 1099 * @cq_tail_slot: current slot to which CQ tail pointer is pointing 1100 * @cq_head_slot: current slot to which CQ head pointer is pointing 1101 * @cq_lock: Synchronize between multiple polling instances 1102 * @sq_mutex: prevent submission queue concurrent access 1103 */ 1104 struct ufs_hw_queue { 1105 void __iomem *mcq_sq_head; 1106 void __iomem *mcq_sq_tail; 1107 void __iomem *mcq_cq_head; 1108 void __iomem *mcq_cq_tail; 1109 1110 struct utp_transfer_req_desc *sqe_base_addr; 1111 dma_addr_t sqe_dma_addr; 1112 struct cq_entry *cqe_base_addr; 1113 dma_addr_t cqe_dma_addr; 1114 u32 max_entries; 1115 u32 id; 1116 u32 sq_tail_slot; 1117 spinlock_t sq_lock; 1118 u32 cq_tail_slot; 1119 u32 cq_head_slot; 1120 spinlock_t cq_lock; 1121 /* prevent concurrent access to submission queue */ 1122 struct mutex sq_mutex; 1123 }; 1124 1125 static inline bool is_mcq_enabled(struct ufs_hba *hba) 1126 { 1127 return hba->mcq_enabled; 1128 } 1129 1130 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 1131 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1132 { 1133 return hba->sg_entry_size; 1134 } 1135 1136 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) 1137 { 1138 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); 1139 hba->sg_entry_size = sg_entry_size; 1140 } 1141 #else 1142 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1143 { 1144 return sizeof(struct ufshcd_sg_entry); 1145 } 1146 1147 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ 1148 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) 1149 #endif 1150 1151 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba) 1152 { 1153 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); 1154 } 1155 1156 /* Returns true if clocks can be gated. Otherwise false */ 1157 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) 1158 { 1159 return hba->caps & UFSHCD_CAP_CLK_GATING; 1160 } 1161 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) 1162 { 1163 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1164 } 1165 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) 1166 { 1167 return hba->caps & UFSHCD_CAP_CLK_SCALING; 1168 } 1169 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 1170 { 1171 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1172 } 1173 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) 1174 { 1175 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; 1176 } 1177 1178 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) 1179 { 1180 return (hba->caps & UFSHCD_CAP_INTR_AGGR) && 1181 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); 1182 } 1183 1184 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) 1185 { 1186 return !!(ufshcd_is_link_hibern8(hba) && 1187 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); 1188 } 1189 1190 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) 1191 { 1192 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && 1193 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); 1194 } 1195 1196 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) 1197 { 1198 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); 1199 } 1200 1201 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) 1202 { 1203 return hba->caps & UFSHCD_CAP_WB_EN; 1204 } 1205 1206 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) 1207 { 1208 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; 1209 } 1210 1211 #define ufsmcq_writel(hba, val, reg) \ 1212 writel((val), (hba)->mcq_base + (reg)) 1213 #define ufsmcq_readl(hba, reg) \ 1214 readl((hba)->mcq_base + (reg)) 1215 1216 #define ufsmcq_writelx(hba, val, reg) \ 1217 writel_relaxed((val), (hba)->mcq_base + (reg)) 1218 #define ufsmcq_readlx(hba, reg) \ 1219 readl_relaxed((hba)->mcq_base + (reg)) 1220 1221 #define ufshcd_writel(hba, val, reg) \ 1222 writel((val), (hba)->mmio_base + (reg)) 1223 #define ufshcd_readl(hba, reg) \ 1224 readl((hba)->mmio_base + (reg)) 1225 1226 /** 1227 * ufshcd_rmwl - perform read/modify/write for a controller register 1228 * @hba: per adapter instance 1229 * @mask: mask to apply on read value 1230 * @val: actual value to write 1231 * @reg: register address 1232 */ 1233 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 1234 { 1235 u32 tmp; 1236 1237 tmp = ufshcd_readl(hba, reg); 1238 tmp &= ~mask; 1239 tmp |= (val & mask); 1240 ufshcd_writel(hba, tmp, reg); 1241 } 1242 1243 void ufshcd_enable_irq(struct ufs_hba *hba); 1244 void ufshcd_disable_irq(struct ufs_hba *hba); 1245 int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1246 void ufshcd_dealloc_host(struct ufs_hba *); 1247 int ufshcd_hba_enable(struct ufs_hba *hba); 1248 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); 1249 int ufshcd_link_recovery(struct ufs_hba *hba); 1250 int ufshcd_make_hba_operational(struct ufs_hba *hba); 1251 void ufshcd_remove(struct ufs_hba *); 1252 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); 1253 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); 1254 void ufshcd_delay_us(unsigned long us, unsigned long tolerance); 1255 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); 1256 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); 1257 void ufshcd_hba_stop(struct ufs_hba *hba); 1258 void ufshcd_schedule_eh_work(struct ufs_hba *hba); 1259 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); 1260 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); 1261 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); 1262 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, 1263 struct ufs_hw_queue *hwq); 1264 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); 1265 void ufshcd_mcq_enable_esi(struct ufs_hba *hba); 1266 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); 1267 1268 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1269 struct dev_pm_opp *opp, void *data, 1270 bool scaling_down); 1271 /** 1272 * ufshcd_set_variant - set variant specific data to the hba 1273 * @hba: per adapter instance 1274 * @variant: pointer to variant specific data 1275 */ 1276 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) 1277 { 1278 BUG_ON(!hba); 1279 hba->priv = variant; 1280 } 1281 1282 /** 1283 * ufshcd_get_variant - get variant specific data from the hba 1284 * @hba: per adapter instance 1285 */ 1286 static inline void *ufshcd_get_variant(struct ufs_hba *hba) 1287 { 1288 BUG_ON(!hba); 1289 return hba->priv; 1290 } 1291 1292 #ifdef CONFIG_PM 1293 extern int ufshcd_runtime_suspend(struct device *dev); 1294 extern int ufshcd_runtime_resume(struct device *dev); 1295 #endif 1296 #ifdef CONFIG_PM_SLEEP 1297 extern int ufshcd_system_suspend(struct device *dev); 1298 extern int ufshcd_system_resume(struct device *dev); 1299 extern int ufshcd_system_freeze(struct device *dev); 1300 extern int ufshcd_system_thaw(struct device *dev); 1301 extern int ufshcd_system_restore(struct device *dev); 1302 #endif 1303 1304 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 1305 int agreed_gear, 1306 int adapt_val); 1307 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 1308 u8 attr_set, u32 mib_val, u8 peer); 1309 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 1310 u32 *mib_val, u8 peer); 1311 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, 1312 struct ufs_pa_layer_attr *desired_pwr_mode); 1313 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); 1314 1315 /* UIC command interfaces for DME primitives */ 1316 #define DME_LOCAL 0 1317 #define DME_PEER 1 1318 #define ATTR_SET_NOR 0 /* NORMAL */ 1319 #define ATTR_SET_ST 1 /* STATIC */ 1320 1321 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 1322 u32 mib_val) 1323 { 1324 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1325 mib_val, DME_LOCAL); 1326 } 1327 1328 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, 1329 u32 mib_val) 1330 { 1331 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1332 mib_val, DME_LOCAL); 1333 } 1334 1335 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 1336 u32 mib_val) 1337 { 1338 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1339 mib_val, DME_PEER); 1340 } 1341 1342 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, 1343 u32 mib_val) 1344 { 1345 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1346 mib_val, DME_PEER); 1347 } 1348 1349 static inline int ufshcd_dme_get(struct ufs_hba *hba, 1350 u32 attr_sel, u32 *mib_val) 1351 { 1352 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 1353 } 1354 1355 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 1356 u32 attr_sel, u32 *mib_val) 1357 { 1358 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 1359 } 1360 1361 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) 1362 { 1363 return (pwr_info->pwr_rx == FAST_MODE || 1364 pwr_info->pwr_rx == FASTAUTO_MODE) && 1365 (pwr_info->pwr_tx == FAST_MODE || 1366 pwr_info->pwr_tx == FASTAUTO_MODE); 1367 } 1368 1369 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) 1370 { 1371 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); 1372 } 1373 1374 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); 1375 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 1376 const struct ufs_dev_quirk *fixups); 1377 #define SD_ASCII_STD true 1378 #define SD_RAW false 1379 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 1380 u8 **buf, bool ascii); 1381 1382 void ufshcd_hold(struct ufs_hba *hba); 1383 void ufshcd_release(struct ufs_hba *hba); 1384 1385 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); 1386 1387 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); 1388 1389 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); 1390 1391 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); 1392 1393 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 1394 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, 1395 struct ufs_ehs *ehs_rsp, int sg_cnt, 1396 struct scatterlist *sg_list, enum dma_data_direction dir); 1397 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); 1398 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); 1399 int ufshcd_suspend_prepare(struct device *dev); 1400 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); 1401 void ufshcd_resume_complete(struct device *dev); 1402 bool ufshcd_is_hba_active(struct ufs_hba *hba); 1403 1404 /* Wrapper functions for safely calling variant operations */ 1405 static inline int ufshcd_vops_init(struct ufs_hba *hba) 1406 { 1407 if (hba->vops && hba->vops->init) 1408 return hba->vops->init(hba); 1409 1410 return 0; 1411 } 1412 1413 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) 1414 { 1415 if (hba->vops && hba->vops->phy_initialization) 1416 return hba->vops->phy_initialization(hba); 1417 1418 return 0; 1419 } 1420 1421 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; 1422 1423 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1424 const char *prefix); 1425 1426 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); 1427 int ufshcd_write_ee_control(struct ufs_hba *hba); 1428 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 1429 const u16 *other_mask, u16 set, u16 clr); 1430 1431 #endif /* End of Header */ 1432