1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #ifndef _UFSHCD_H 13 #define _UFSHCD_H 14 15 #include <linux/bitfield.h> 16 #include <linux/blk-crypto-profile.h> 17 #include <linux/blk-mq.h> 18 #include <linux/devfreq.h> 19 #include <linux/pm_runtime.h> 20 #include <scsi/scsi_device.h> 21 #include <ufs/unipro.h> 22 #include <ufs/ufs.h> 23 #include <ufs/ufs_quirks.h> 24 #include <ufs/ufshci.h> 25 26 #define UFSHCD "ufshcd" 27 28 struct ufs_hba; 29 30 enum dev_cmd_type { 31 DEV_CMD_TYPE_NOP = 0x0, 32 DEV_CMD_TYPE_QUERY = 0x1, 33 DEV_CMD_TYPE_RPMB = 0x2, 34 }; 35 36 enum ufs_event_type { 37 /* uic specific errors */ 38 UFS_EVT_PA_ERR = 0, 39 UFS_EVT_DL_ERR, 40 UFS_EVT_NL_ERR, 41 UFS_EVT_TL_ERR, 42 UFS_EVT_DME_ERR, 43 44 /* fatal errors */ 45 UFS_EVT_AUTO_HIBERN8_ERR, 46 UFS_EVT_FATAL_ERR, 47 UFS_EVT_LINK_STARTUP_FAIL, 48 UFS_EVT_RESUME_ERR, 49 UFS_EVT_SUSPEND_ERR, 50 UFS_EVT_WL_SUSP_ERR, 51 UFS_EVT_WL_RES_ERR, 52 53 /* abnormal events */ 54 UFS_EVT_DEV_RESET, 55 UFS_EVT_HOST_RESET, 56 UFS_EVT_ABORT, 57 58 UFS_EVT_CNT, 59 }; 60 61 /** 62 * struct uic_command - UIC command structure 63 * @command: UIC command 64 * @argument1: UIC command argument 1 65 * @argument2: UIC command argument 2 66 * @argument3: UIC command argument 3 67 * @cmd_active: Indicate if UIC command is outstanding 68 * @done: UIC command completion 69 */ 70 struct uic_command { 71 u32 command; 72 u32 argument1; 73 u32 argument2; 74 u32 argument3; 75 int cmd_active; 76 struct completion done; 77 }; 78 79 /* Used to differentiate the power management options */ 80 enum ufs_pm_op { 81 UFS_RUNTIME_PM, 82 UFS_SYSTEM_PM, 83 UFS_SHUTDOWN_PM, 84 }; 85 86 /* Host <-> Device UniPro Link state */ 87 enum uic_link_state { 88 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 89 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 90 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 91 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ 92 }; 93 94 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) 95 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ 96 UIC_LINK_ACTIVE_STATE) 97 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ 98 UIC_LINK_HIBERN8_STATE) 99 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ 100 UIC_LINK_BROKEN_STATE) 101 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) 102 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ 103 UIC_LINK_ACTIVE_STATE) 104 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ 105 UIC_LINK_HIBERN8_STATE) 106 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ 107 UIC_LINK_BROKEN_STATE) 108 109 #define ufshcd_set_ufs_dev_active(h) \ 110 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) 111 #define ufshcd_set_ufs_dev_sleep(h) \ 112 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) 113 #define ufshcd_set_ufs_dev_poweroff(h) \ 114 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) 115 #define ufshcd_set_ufs_dev_deepsleep(h) \ 116 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) 117 #define ufshcd_is_ufs_dev_active(h) \ 118 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) 119 #define ufshcd_is_ufs_dev_sleep(h) \ 120 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) 121 #define ufshcd_is_ufs_dev_poweroff(h) \ 122 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) 123 #define ufshcd_is_ufs_dev_deepsleep(h) \ 124 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) 125 126 /* 127 * UFS Power management levels. 128 * Each level is in increasing order of power savings, except DeepSleep 129 * which is lower than PowerDown with power on but not PowerDown with 130 * power off. 131 */ 132 enum ufs_pm_level { 133 UFS_PM_LVL_0, 134 UFS_PM_LVL_1, 135 UFS_PM_LVL_2, 136 UFS_PM_LVL_3, 137 UFS_PM_LVL_4, 138 UFS_PM_LVL_5, 139 UFS_PM_LVL_6, 140 UFS_PM_LVL_MAX 141 }; 142 143 struct ufs_pm_lvl_states { 144 enum ufs_dev_pwr_mode dev_state; 145 enum uic_link_state link_state; 146 }; 147 148 /** 149 * struct ufshcd_lrb - local reference block 150 * @utr_descriptor_ptr: UTRD address of the command 151 * @ucd_req_ptr: UCD address of the command 152 * @ucd_rsp_ptr: Response UPIU address for this command 153 * @ucd_prdt_ptr: PRDT address of the command 154 * @utrd_dma_addr: UTRD dma address for debug 155 * @ucd_prdt_dma_addr: PRDT dma address for debug 156 * @ucd_rsp_dma_addr: UPIU response dma address for debug 157 * @ucd_req_dma_addr: UPIU request dma address for debug 158 * @cmd: pointer to SCSI command 159 * @scsi_status: SCSI status of the command 160 * @command_type: SCSI, UFS, Query. 161 * @task_tag: Task tag of the command 162 * @lun: LUN of the command 163 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) 164 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) 165 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) 166 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) 167 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) 168 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) 169 * @data_unit_num: the data unit number for the first block for inline crypto 170 * @req_abort_skip: skip request abort task flag 171 */ 172 struct ufshcd_lrb { 173 struct utp_transfer_req_desc *utr_descriptor_ptr; 174 struct utp_upiu_req *ucd_req_ptr; 175 struct utp_upiu_rsp *ucd_rsp_ptr; 176 struct ufshcd_sg_entry *ucd_prdt_ptr; 177 178 dma_addr_t utrd_dma_addr; 179 dma_addr_t ucd_req_dma_addr; 180 dma_addr_t ucd_rsp_dma_addr; 181 dma_addr_t ucd_prdt_dma_addr; 182 183 struct scsi_cmnd *cmd; 184 int scsi_status; 185 186 int command_type; 187 int task_tag; 188 u8 lun; /* UPIU LUN id field is only 8-bit wide */ 189 bool intr_cmd; 190 ktime_t issue_time_stamp; 191 u64 issue_time_stamp_local_clock; 192 ktime_t compl_time_stamp; 193 u64 compl_time_stamp_local_clock; 194 #ifdef CONFIG_SCSI_UFS_CRYPTO 195 int crypto_key_slot; 196 u64 data_unit_num; 197 #endif 198 199 bool req_abort_skip; 200 }; 201 202 /** 203 * struct ufs_query - holds relevant data structures for query request 204 * @request: request upiu and function 205 * @descriptor: buffer for sending/receiving descriptor 206 * @response: response upiu and response 207 */ 208 struct ufs_query { 209 struct ufs_query_req request; 210 u8 *descriptor; 211 struct ufs_query_res response; 212 }; 213 214 /** 215 * struct ufs_dev_cmd - all assosiated fields with device management commands 216 * @type: device management command type - Query, NOP OUT 217 * @lock: lock to allow one command at a time 218 * @complete: internal commands completion 219 * @query: Device management query information 220 */ 221 struct ufs_dev_cmd { 222 enum dev_cmd_type type; 223 struct mutex lock; 224 struct completion *complete; 225 struct ufs_query query; 226 }; 227 228 /** 229 * struct ufs_clk_info - UFS clock related info 230 * @list: list headed by hba->clk_list_head 231 * @clk: clock node 232 * @name: clock name 233 * @max_freq: maximum frequency supported by the clock 234 * @min_freq: min frequency that can be used for clock scaling 235 * @curr_freq: indicates the current frequency that it is set to 236 * @keep_link_active: indicates that the clk should not be disabled if 237 * link is active 238 * @enabled: variable to check against multiple enable/disable 239 */ 240 struct ufs_clk_info { 241 struct list_head list; 242 struct clk *clk; 243 const char *name; 244 u32 max_freq; 245 u32 min_freq; 246 u32 curr_freq; 247 bool keep_link_active; 248 bool enabled; 249 }; 250 251 enum ufs_notify_change_status { 252 PRE_CHANGE, 253 POST_CHANGE, 254 }; 255 256 struct ufs_pa_layer_attr { 257 u32 gear_rx; 258 u32 gear_tx; 259 u32 lane_rx; 260 u32 lane_tx; 261 u32 pwr_rx; 262 u32 pwr_tx; 263 u32 hs_rate; 264 }; 265 266 struct ufs_pwr_mode_info { 267 bool is_valid; 268 struct ufs_pa_layer_attr info; 269 }; 270 271 /** 272 * struct ufs_hba_variant_ops - variant specific callbacks 273 * @name: variant name 274 * @init: called when the driver is initialized 275 * @exit: called to cleanup everything done in init 276 * @get_ufs_hci_version: called to get UFS HCI version 277 * @clk_scale_notify: notifies that clks are scaled up/down 278 * @setup_clocks: called before touching any of the controller registers 279 * @hce_enable_notify: called before and after HCE enable bit is set to allow 280 * variant specific Uni-Pro initialization. 281 * @link_startup_notify: called before and after Link startup is carried out 282 * to allow variant specific Uni-Pro initialization. 283 * @pwr_change_notify: called before and after a power mode change 284 * is carried out to allow vendor spesific capabilities 285 * to be set. 286 * @setup_xfer_req: called before any transfer request is issued 287 * to set some things 288 * @setup_task_mgmt: called before any task management request is issued 289 * to set some things 290 * @hibern8_notify: called around hibern8 enter/exit 291 * @apply_dev_quirks: called to apply device specific quirks 292 * @fixup_dev_quirks: called to modify device specific quirks 293 * @suspend: called during host controller PM callback 294 * @resume: called during host controller PM callback 295 * @dbg_register_dump: used to dump controller debug information 296 * @phy_initialization: used to initialize phys 297 * @device_reset: called to issue a reset pulse on the UFS device 298 * @config_scaling_param: called to configure clock scaling parameters 299 * @program_key: program or evict an inline encryption key 300 * @event_notify: called to notify important events 301 */ 302 struct ufs_hba_variant_ops { 303 const char *name; 304 int (*init)(struct ufs_hba *); 305 void (*exit)(struct ufs_hba *); 306 u32 (*get_ufs_hci_version)(struct ufs_hba *); 307 int (*clk_scale_notify)(struct ufs_hba *, bool, 308 enum ufs_notify_change_status); 309 int (*setup_clocks)(struct ufs_hba *, bool, 310 enum ufs_notify_change_status); 311 int (*hce_enable_notify)(struct ufs_hba *, 312 enum ufs_notify_change_status); 313 int (*link_startup_notify)(struct ufs_hba *, 314 enum ufs_notify_change_status); 315 int (*pwr_change_notify)(struct ufs_hba *, 316 enum ufs_notify_change_status status, 317 struct ufs_pa_layer_attr *, 318 struct ufs_pa_layer_attr *); 319 void (*setup_xfer_req)(struct ufs_hba *hba, int tag, 320 bool is_scsi_cmd); 321 void (*setup_task_mgmt)(struct ufs_hba *, int, u8); 322 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, 323 enum ufs_notify_change_status); 324 int (*apply_dev_quirks)(struct ufs_hba *hba); 325 void (*fixup_dev_quirks)(struct ufs_hba *hba); 326 int (*suspend)(struct ufs_hba *, enum ufs_pm_op, 327 enum ufs_notify_change_status); 328 int (*resume)(struct ufs_hba *, enum ufs_pm_op); 329 void (*dbg_register_dump)(struct ufs_hba *hba); 330 int (*phy_initialization)(struct ufs_hba *); 331 int (*device_reset)(struct ufs_hba *hba); 332 void (*config_scaling_param)(struct ufs_hba *hba, 333 struct devfreq_dev_profile *profile, 334 struct devfreq_simple_ondemand_data *data); 335 int (*program_key)(struct ufs_hba *hba, 336 const union ufs_crypto_cfg_entry *cfg, int slot); 337 void (*event_notify)(struct ufs_hba *hba, 338 enum ufs_event_type evt, void *data); 339 }; 340 341 /* clock gating state */ 342 enum clk_gating_state { 343 CLKS_OFF, 344 CLKS_ON, 345 REQ_CLKS_OFF, 346 REQ_CLKS_ON, 347 }; 348 349 /** 350 * struct ufs_clk_gating - UFS clock gating related info 351 * @gate_work: worker to turn off clocks after some delay as specified in 352 * delay_ms 353 * @ungate_work: worker to turn on clocks that will be used in case of 354 * interrupt context 355 * @state: the current clocks state 356 * @delay_ms: gating delay in ms 357 * @is_suspended: clk gating is suspended when set to 1 which can be used 358 * during suspend/resume 359 * @delay_attr: sysfs attribute to control delay_attr 360 * @enable_attr: sysfs attribute to enable/disable clock gating 361 * @is_enabled: Indicates the current status of clock gating 362 * @is_initialized: Indicates whether clock gating is initialized or not 363 * @active_reqs: number of requests that are pending and should be waited for 364 * completion before gating clocks. 365 * @clk_gating_workq: workqueue for clock gating work. 366 */ 367 struct ufs_clk_gating { 368 struct delayed_work gate_work; 369 struct work_struct ungate_work; 370 enum clk_gating_state state; 371 unsigned long delay_ms; 372 bool is_suspended; 373 struct device_attribute delay_attr; 374 struct device_attribute enable_attr; 375 bool is_enabled; 376 bool is_initialized; 377 int active_reqs; 378 struct workqueue_struct *clk_gating_workq; 379 }; 380 381 struct ufs_saved_pwr_info { 382 struct ufs_pa_layer_attr info; 383 bool is_valid; 384 }; 385 386 /** 387 * struct ufs_clk_scaling - UFS clock scaling related data 388 * @active_reqs: number of requests that are pending. If this is zero when 389 * devfreq ->target() function is called then schedule "suspend_work" to 390 * suspend devfreq. 391 * @tot_busy_t: Total busy time in current polling window 392 * @window_start_t: Start time (in jiffies) of the current polling window 393 * @busy_start_t: Start time of current busy period 394 * @enable_attr: sysfs attribute to enable/disable clock scaling 395 * @saved_pwr_info: UFS power mode may also be changed during scaling and this 396 * one keeps track of previous power mode. 397 * @workq: workqueue to schedule devfreq suspend/resume work 398 * @suspend_work: worker to suspend devfreq 399 * @resume_work: worker to resume devfreq 400 * @min_gear: lowest HS gear to scale down to 401 * @is_enabled: tracks if scaling is currently enabled or not, controlled by 402 * clkscale_enable sysfs node 403 * @is_allowed: tracks if scaling is currently allowed or not, used to block 404 * clock scaling which is not invoked from devfreq governor 405 * @is_initialized: Indicates whether clock scaling is initialized or not 406 * @is_busy_started: tracks if busy period has started or not 407 * @is_suspended: tracks if devfreq is suspended or not 408 */ 409 struct ufs_clk_scaling { 410 int active_reqs; 411 unsigned long tot_busy_t; 412 ktime_t window_start_t; 413 ktime_t busy_start_t; 414 struct device_attribute enable_attr; 415 struct ufs_saved_pwr_info saved_pwr_info; 416 struct workqueue_struct *workq; 417 struct work_struct suspend_work; 418 struct work_struct resume_work; 419 u32 min_gear; 420 bool is_enabled; 421 bool is_allowed; 422 bool is_initialized; 423 bool is_busy_started; 424 bool is_suspended; 425 }; 426 427 #define UFS_EVENT_HIST_LENGTH 8 428 /** 429 * struct ufs_event_hist - keeps history of errors 430 * @pos: index to indicate cyclic buffer position 431 * @val: cyclic buffer for registers value 432 * @tstamp: cyclic buffer for time stamp 433 * @cnt: error counter 434 */ 435 struct ufs_event_hist { 436 int pos; 437 u32 val[UFS_EVENT_HIST_LENGTH]; 438 u64 tstamp[UFS_EVENT_HIST_LENGTH]; 439 unsigned long long cnt; 440 }; 441 442 /** 443 * struct ufs_stats - keeps usage/err statistics 444 * @last_intr_status: record the last interrupt status. 445 * @last_intr_ts: record the last interrupt timestamp. 446 * @hibern8_exit_cnt: Counter to keep track of number of exits, 447 * reset this after link-startup. 448 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. 449 * Clear after the first successful command completion. 450 * @event: array with event history. 451 */ 452 struct ufs_stats { 453 u32 last_intr_status; 454 u64 last_intr_ts; 455 456 u32 hibern8_exit_cnt; 457 u64 last_hibern8_exit_tstamp; 458 struct ufs_event_hist event[UFS_EVT_CNT]; 459 }; 460 461 /** 462 * enum ufshcd_state - UFS host controller state 463 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command 464 * processing. 465 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process 466 * SCSI commands. 467 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. 468 * SCSI commands may be submitted to the controller. 469 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail 470 * newly submitted SCSI commands with error code DID_BAD_TARGET. 471 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery 472 * failed. Fail all SCSI commands with error code DID_ERROR. 473 */ 474 enum ufshcd_state { 475 UFSHCD_STATE_RESET, 476 UFSHCD_STATE_OPERATIONAL, 477 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, 478 UFSHCD_STATE_EH_SCHEDULED_FATAL, 479 UFSHCD_STATE_ERROR, 480 }; 481 482 enum ufshcd_quirks { 483 /* Interrupt aggregation support is broken */ 484 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, 485 486 /* 487 * delay before each dme command is required as the unipro 488 * layer has shown instabilities 489 */ 490 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, 491 492 /* 493 * If UFS host controller is having issue in processing LCC (Line 494 * Control Command) coming from device then enable this quirk. 495 * When this quirk is enabled, host controller driver should disable 496 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 497 * attribute of device to 0). 498 */ 499 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, 500 501 /* 502 * The attribute PA_RXHSUNTERMCAP specifies whether or not the 503 * inbound Link supports unterminated line in HS mode. Setting this 504 * attribute to 1 fixes moving to HS gear. 505 */ 506 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, 507 508 /* 509 * This quirk needs to be enabled if the host controller only allows 510 * accessing the peer dme attributes in AUTO mode (FAST AUTO or 511 * SLOW AUTO). 512 */ 513 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, 514 515 /* 516 * This quirk needs to be enabled if the host controller doesn't 517 * advertise the correct version in UFS_VER register. If this quirk 518 * is enabled, standard UFS host driver will call the vendor specific 519 * ops (get_ufs_hci_version) to get the correct version. 520 */ 521 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, 522 523 /* 524 * Clear handling for transfer/task request list is just opposite. 525 */ 526 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, 527 528 /* 529 * This quirk needs to be enabled if host controller doesn't allow 530 * that the interrupt aggregation timer and counter are reset by s/w. 531 */ 532 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, 533 534 /* 535 * This quirks needs to be enabled if host controller cannot be 536 * enabled via HCE register. 537 */ 538 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, 539 540 /* 541 * This quirk needs to be enabled if the host controller regards 542 * resolution of the values of PRDTO and PRDTL in UTRD as byte. 543 */ 544 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, 545 546 /* 547 * This quirk needs to be enabled if the host controller reports 548 * OCS FATAL ERROR with device error through sense data 549 */ 550 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, 551 552 /* 553 * This quirk needs to be enabled if the host controller has 554 * auto-hibernate capability but it doesn't work. 555 */ 556 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, 557 558 /* 559 * This quirk needs to disable manual flush for write booster 560 */ 561 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, 562 563 /* 564 * This quirk needs to disable unipro timeout values 565 * before power mode change 566 */ 567 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, 568 569 /* 570 * This quirk allows only sg entries aligned with page size. 571 */ 572 UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 14, 573 574 /* 575 * This quirk needs to be enabled if the host controller does not 576 * support UIC command 577 */ 578 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, 579 580 /* 581 * This quirk needs to be enabled if the host controller cannot 582 * support physical host configuration. 583 */ 584 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, 585 586 /* 587 * This quirk needs to be enabled if the host controller has 588 * 64-bit addressing supported capability but it doesn't work. 589 */ 590 UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, 591 592 /* 593 * This quirk needs to be enabled if the host controller has 594 * auto-hibernate capability but it's FASTAUTO only. 595 */ 596 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, 597 }; 598 599 enum ufshcd_caps { 600 /* Allow dynamic clk gating */ 601 UFSHCD_CAP_CLK_GATING = 1 << 0, 602 603 /* Allow hiberb8 with clk gating */ 604 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, 605 606 /* Allow dynamic clk scaling */ 607 UFSHCD_CAP_CLK_SCALING = 1 << 2, 608 609 /* Allow auto bkops to enabled during runtime suspend */ 610 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, 611 612 /* 613 * This capability allows host controller driver to use the UFS HCI's 614 * interrupt aggregation capability. 615 * CAUTION: Enabling this might reduce overall UFS throughput. 616 */ 617 UFSHCD_CAP_INTR_AGGR = 1 << 4, 618 619 /* 620 * This capability allows the device auto-bkops to be always enabled 621 * except during suspend (both runtime and suspend). 622 * Enabling this capability means that device will always be allowed 623 * to do background operation when it's active but it might degrade 624 * the performance of ongoing read/write operations. 625 */ 626 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, 627 628 /* 629 * This capability allows host controller driver to automatically 630 * enable runtime power management by itself instead of waiting 631 * for userspace to control the power management. 632 */ 633 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, 634 635 /* 636 * This capability allows the host controller driver to turn-on 637 * WriteBooster, if the underlying device supports it and is 638 * provisioned to be used. This would increase the write performance. 639 */ 640 UFSHCD_CAP_WB_EN = 1 << 7, 641 642 /* 643 * This capability allows the host controller driver to use the 644 * inline crypto engine, if it is present 645 */ 646 UFSHCD_CAP_CRYPTO = 1 << 8, 647 648 /* 649 * This capability allows the controller regulators to be put into 650 * lpm mode aggressively during clock gating. 651 * This would increase power savings. 652 */ 653 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, 654 655 /* 656 * This capability allows the host controller driver to use DeepSleep, 657 * if it is supported by the UFS device. The host controller driver must 658 * support device hardware reset via the hba->device_reset() callback, 659 * in order to exit DeepSleep state. 660 */ 661 UFSHCD_CAP_DEEPSLEEP = 1 << 10, 662 663 /* 664 * This capability allows the host controller driver to use temperature 665 * notification if it is supported by the UFS device. 666 */ 667 UFSHCD_CAP_TEMP_NOTIF = 1 << 11, 668 669 /* 670 * Enable WriteBooster when scaling up the clock and disable 671 * WriteBooster when scaling the clock down. 672 */ 673 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, 674 }; 675 676 struct ufs_hba_variant_params { 677 struct devfreq_dev_profile devfreq_profile; 678 struct devfreq_simple_ondemand_data ondemand_data; 679 u16 hba_enable_delay_us; 680 u32 wb_flush_threshold; 681 }; 682 683 #ifdef CONFIG_SCSI_UFS_HPB 684 /** 685 * struct ufshpb_dev_info - UFSHPB device related info 686 * @num_lu: the number of user logical unit to check whether all lu finished 687 * initialization 688 * @rgn_size: device reported HPB region size 689 * @srgn_size: device reported HPB sub-region size 690 * @slave_conf_cnt: counter to check all lu finished initialization 691 * @hpb_disabled: flag to check if HPB is disabled 692 * @max_hpb_single_cmd: device reported bMAX_DATA_SIZE_FOR_SINGLE_CMD value 693 * @is_legacy: flag to check HPB 1.0 694 * @control_mode: either host or device 695 */ 696 struct ufshpb_dev_info { 697 int num_lu; 698 int rgn_size; 699 int srgn_size; 700 atomic_t slave_conf_cnt; 701 bool hpb_disabled; 702 u8 max_hpb_single_cmd; 703 bool is_legacy; 704 u8 control_mode; 705 }; 706 #endif 707 708 struct ufs_hba_monitor { 709 unsigned long chunk_size; 710 711 unsigned long nr_sec_rw[2]; 712 ktime_t total_busy[2]; 713 714 unsigned long nr_req[2]; 715 /* latencies*/ 716 ktime_t lat_sum[2]; 717 ktime_t lat_max[2]; 718 ktime_t lat_min[2]; 719 720 u32 nr_queued[2]; 721 ktime_t busy_start_ts[2]; 722 723 ktime_t enabled_ts; 724 bool enabled; 725 }; 726 727 /** 728 * struct ufs_hba - per adapter private structure 729 * @mmio_base: UFSHCI base register address 730 * @ucdl_base_addr: UFS Command Descriptor base address 731 * @utrdl_base_addr: UTP Transfer Request Descriptor base address 732 * @utmrdl_base_addr: UTP Task Management Descriptor base address 733 * @ucdl_dma_addr: UFS Command Descriptor DMA address 734 * @utrdl_dma_addr: UTRDL DMA address 735 * @utmrdl_dma_addr: UTMRDL DMA address 736 * @host: Scsi_Host instance of the driver 737 * @dev: device handle 738 * @ufs_device_wlun: WLUN that controls the entire UFS device. 739 * @hwmon_device: device instance registered with the hwmon core. 740 * @curr_dev_pwr_mode: active UFS device power mode. 741 * @uic_link_state: active state of the link to the UFS device. 742 * @rpm_lvl: desired UFS power management level during runtime PM. 743 * @spm_lvl: desired UFS power management level during system PM. 744 * @pm_op_in_progress: whether or not a PM operation is in progress. 745 * @ahit: value of Auto-Hibernate Idle Timer register. 746 * @lrb: local reference block 747 * @outstanding_tasks: Bits representing outstanding task requests 748 * @outstanding_lock: Protects @outstanding_reqs. 749 * @outstanding_reqs: Bits representing outstanding transfer requests 750 * @capabilities: UFS Controller Capabilities 751 * @nutrs: Transfer Request Queue depth supported by controller 752 * @nutmrs: Task Management Queue depth supported by controller 753 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. 754 * @ufs_version: UFS Version to which controller complies 755 * @vops: pointer to variant specific operations 756 * @vps: pointer to variant specific parameters 757 * @priv: pointer to variant specific private data 758 * @irq: Irq number of the controller 759 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. 760 * @dev_ref_clk_freq: reference clock frequency 761 * @quirks: bitmask with information about deviations from the UFSHCI standard. 762 * @dev_quirks: bitmask with information about deviations from the UFS standard. 763 * @tmf_tag_set: TMF tag set. 764 * @tmf_queue: Used to allocate TMF tags. 765 * @tmf_rqs: array with pointers to TMF requests while these are in progress. 766 * @active_uic_cmd: handle of active UIC command 767 * @uic_cmd_mutex: mutex for UIC command 768 * @uic_async_done: completion used during UIC processing 769 * @ufshcd_state: UFSHCD state 770 * @eh_flags: Error handling flags 771 * @intr_mask: Interrupt Mask Bits 772 * @ee_ctrl_mask: Exception event control mask 773 * @ee_drv_mask: Exception event mask for driver 774 * @ee_usr_mask: Exception event mask for user (set via debugfs) 775 * @ee_ctrl_mutex: Used to serialize exception event information. 776 * @is_powered: flag to check if HBA is powered 777 * @shutting_down: flag to check if shutdown has been invoked 778 * @host_sem: semaphore used to serialize concurrent contexts 779 * @eh_wq: Workqueue that eh_work works on 780 * @eh_work: Worker to handle UFS errors that require s/w attention 781 * @eeh_work: Worker to handle exception events 782 * @errors: HBA errors 783 * @uic_error: UFS interconnect layer error status 784 * @saved_err: sticky error mask 785 * @saved_uic_err: sticky UIC error mask 786 * @ufs_stats: various error counters 787 * @force_reset: flag to force eh_work perform a full reset 788 * @force_pmc: flag to force a power mode change 789 * @silence_err_logs: flag to silence error logs 790 * @dev_cmd: ufs device management command information 791 * @last_dme_cmd_tstamp: time stamp of the last completed DME command 792 * @nop_out_timeout: NOP OUT timeout value 793 * @dev_info: information about the UFS device 794 * @auto_bkops_enabled: to track whether bkops is enabled in device 795 * @vreg_info: UFS device voltage regulator information 796 * @clk_list_head: UFS host controller clocks list node head 797 * @req_abort_count: number of times ufshcd_abort() has been called 798 * @lanes_per_direction: number of lanes per data direction between the UFS 799 * controller and the UFS device. 800 * @pwr_info: holds current power mode 801 * @max_pwr_info: keeps the device max valid pwm 802 * @clk_gating: information related to clock gating 803 * @caps: bitmask with information about UFS controller capabilities 804 * @devfreq: frequency scaling information owned by the devfreq core 805 * @clk_scaling: frequency scaling information owned by the UFS driver 806 * @system_suspending: system suspend has been started and system resume has 807 * not yet finished. 808 * @is_sys_suspended: UFS device has been suspended because of system suspend 809 * @urgent_bkops_lvl: keeps track of urgent bkops level for device 810 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for 811 * device is known or not. 812 * @clk_scaling_lock: used to serialize device commands and clock scaling 813 * @desc_size: descriptor sizes reported by device 814 * @scsi_block_reqs_cnt: reference counting for scsi block requests 815 * @bsg_dev: struct device associated with the BSG queue 816 * @bsg_queue: BSG queue associated with the UFS controller 817 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power 818 * management) after the UFS device has finished a WriteBooster buffer 819 * flush or auto BKOP. 820 * @ufshpb_dev: information related to HPB (Host Performance Booster). 821 * @monitor: statistics about UFS commands 822 * @crypto_capabilities: Content of crypto capabilities register (0x100) 823 * @crypto_cap_array: Array of crypto capabilities 824 * @crypto_cfg_register: Start of the crypto cfg array 825 * @crypto_profile: the crypto profile of this hba (if applicable) 826 * @debugfs_root: UFS controller debugfs root directory 827 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay 828 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore 829 * ee_ctrl_mask 830 * @luns_avail: number of regular and well known LUNs supported by the UFS 831 * device 832 * @complete_put: whether or not to call ufshcd_rpm_put() from inside 833 * ufshcd_resume_complete() 834 */ 835 struct ufs_hba { 836 void __iomem *mmio_base; 837 838 /* Virtual memory reference */ 839 struct utp_transfer_cmd_desc *ucdl_base_addr; 840 struct utp_transfer_req_desc *utrdl_base_addr; 841 struct utp_task_req_desc *utmrdl_base_addr; 842 843 /* DMA memory reference */ 844 dma_addr_t ucdl_dma_addr; 845 dma_addr_t utrdl_dma_addr; 846 dma_addr_t utmrdl_dma_addr; 847 848 struct Scsi_Host *host; 849 struct device *dev; 850 struct scsi_device *ufs_device_wlun; 851 852 #ifdef CONFIG_SCSI_UFS_HWMON 853 struct device *hwmon_device; 854 #endif 855 856 enum ufs_dev_pwr_mode curr_dev_pwr_mode; 857 enum uic_link_state uic_link_state; 858 /* Desired UFS power management level during runtime PM */ 859 enum ufs_pm_level rpm_lvl; 860 /* Desired UFS power management level during system PM */ 861 enum ufs_pm_level spm_lvl; 862 int pm_op_in_progress; 863 864 /* Auto-Hibernate Idle Timer register value */ 865 u32 ahit; 866 867 struct ufshcd_lrb *lrb; 868 869 unsigned long outstanding_tasks; 870 spinlock_t outstanding_lock; 871 unsigned long outstanding_reqs; 872 873 u32 capabilities; 874 int nutrs; 875 int nutmrs; 876 u32 reserved_slot; 877 u32 ufs_version; 878 const struct ufs_hba_variant_ops *vops; 879 struct ufs_hba_variant_params *vps; 880 void *priv; 881 unsigned int irq; 882 bool is_irq_enabled; 883 enum ufs_ref_clk_freq dev_ref_clk_freq; 884 885 unsigned int quirks; /* Deviations from standard UFSHCI spec. */ 886 887 /* Device deviations from standard UFS device spec. */ 888 unsigned int dev_quirks; 889 890 struct blk_mq_tag_set tmf_tag_set; 891 struct request_queue *tmf_queue; 892 struct request **tmf_rqs; 893 894 struct uic_command *active_uic_cmd; 895 struct mutex uic_cmd_mutex; 896 struct completion *uic_async_done; 897 898 enum ufshcd_state ufshcd_state; 899 u32 eh_flags; 900 u32 intr_mask; 901 u16 ee_ctrl_mask; 902 u16 ee_drv_mask; 903 u16 ee_usr_mask; 904 struct mutex ee_ctrl_mutex; 905 bool is_powered; 906 bool shutting_down; 907 struct semaphore host_sem; 908 909 /* Work Queues */ 910 struct workqueue_struct *eh_wq; 911 struct work_struct eh_work; 912 struct work_struct eeh_work; 913 914 /* HBA Errors */ 915 u32 errors; 916 u32 uic_error; 917 u32 saved_err; 918 u32 saved_uic_err; 919 struct ufs_stats ufs_stats; 920 bool force_reset; 921 bool force_pmc; 922 bool silence_err_logs; 923 924 /* Device management request data */ 925 struct ufs_dev_cmd dev_cmd; 926 ktime_t last_dme_cmd_tstamp; 927 int nop_out_timeout; 928 929 /* Keeps information of the UFS device connected to this host */ 930 struct ufs_dev_info dev_info; 931 bool auto_bkops_enabled; 932 struct ufs_vreg_info vreg_info; 933 struct list_head clk_list_head; 934 935 /* Number of requests aborts */ 936 int req_abort_count; 937 938 /* Number of lanes available (1 or 2) for Rx/Tx */ 939 u32 lanes_per_direction; 940 struct ufs_pa_layer_attr pwr_info; 941 struct ufs_pwr_mode_info max_pwr_info; 942 943 struct ufs_clk_gating clk_gating; 944 /* Control to enable/disable host capabilities */ 945 u32 caps; 946 947 struct devfreq *devfreq; 948 struct ufs_clk_scaling clk_scaling; 949 bool system_suspending; 950 bool is_sys_suspended; 951 952 enum bkops_status urgent_bkops_lvl; 953 bool is_urgent_bkops_lvl_checked; 954 955 struct rw_semaphore clk_scaling_lock; 956 unsigned char desc_size[QUERY_DESC_IDN_MAX]; 957 atomic_t scsi_block_reqs_cnt; 958 959 struct device bsg_dev; 960 struct request_queue *bsg_queue; 961 struct delayed_work rpm_dev_flush_recheck_work; 962 963 #ifdef CONFIG_SCSI_UFS_HPB 964 struct ufshpb_dev_info ufshpb_dev; 965 #endif 966 967 struct ufs_hba_monitor monitor; 968 969 #ifdef CONFIG_SCSI_UFS_CRYPTO 970 union ufs_crypto_capabilities crypto_capabilities; 971 union ufs_crypto_cap_entry *crypto_cap_array; 972 u32 crypto_cfg_register; 973 struct blk_crypto_profile crypto_profile; 974 #endif 975 #ifdef CONFIG_DEBUG_FS 976 struct dentry *debugfs_root; 977 struct delayed_work debugfs_ee_work; 978 u32 debugfs_ee_rate_limit_ms; 979 #endif 980 u32 luns_avail; 981 bool complete_put; 982 }; 983 984 /* Returns true if clocks can be gated. Otherwise false */ 985 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) 986 { 987 return hba->caps & UFSHCD_CAP_CLK_GATING; 988 } 989 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) 990 { 991 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 992 } 993 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) 994 { 995 return hba->caps & UFSHCD_CAP_CLK_SCALING; 996 } 997 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 998 { 999 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1000 } 1001 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) 1002 { 1003 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; 1004 } 1005 1006 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) 1007 { 1008 return (hba->caps & UFSHCD_CAP_INTR_AGGR) && 1009 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); 1010 } 1011 1012 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) 1013 { 1014 return !!(ufshcd_is_link_hibern8(hba) && 1015 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); 1016 } 1017 1018 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) 1019 { 1020 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && 1021 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); 1022 } 1023 1024 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) 1025 { 1026 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); 1027 } 1028 1029 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) 1030 { 1031 return hba->caps & UFSHCD_CAP_WB_EN; 1032 } 1033 1034 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) 1035 { 1036 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; 1037 } 1038 1039 #define ufshcd_writel(hba, val, reg) \ 1040 writel((val), (hba)->mmio_base + (reg)) 1041 #define ufshcd_readl(hba, reg) \ 1042 readl((hba)->mmio_base + (reg)) 1043 1044 /** 1045 * ufshcd_rmwl - perform read/modify/write for a controller register 1046 * @hba: per adapter instance 1047 * @mask: mask to apply on read value 1048 * @val: actual value to write 1049 * @reg: register address 1050 */ 1051 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 1052 { 1053 u32 tmp; 1054 1055 tmp = ufshcd_readl(hba, reg); 1056 tmp &= ~mask; 1057 tmp |= (val & mask); 1058 ufshcd_writel(hba, tmp, reg); 1059 } 1060 1061 int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1062 void ufshcd_dealloc_host(struct ufs_hba *); 1063 int ufshcd_hba_enable(struct ufs_hba *hba); 1064 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); 1065 int ufshcd_link_recovery(struct ufs_hba *hba); 1066 int ufshcd_make_hba_operational(struct ufs_hba *hba); 1067 void ufshcd_remove(struct ufs_hba *); 1068 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); 1069 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); 1070 void ufshcd_delay_us(unsigned long us, unsigned long tolerance); 1071 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); 1072 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); 1073 void ufshcd_hba_stop(struct ufs_hba *hba); 1074 void ufshcd_schedule_eh_work(struct ufs_hba *hba); 1075 1076 /** 1077 * ufshcd_set_variant - set variant specific data to the hba 1078 * @hba: per adapter instance 1079 * @variant: pointer to variant specific data 1080 */ 1081 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) 1082 { 1083 BUG_ON(!hba); 1084 hba->priv = variant; 1085 } 1086 1087 /** 1088 * ufshcd_get_variant - get variant specific data from the hba 1089 * @hba: per adapter instance 1090 */ 1091 static inline void *ufshcd_get_variant(struct ufs_hba *hba) 1092 { 1093 BUG_ON(!hba); 1094 return hba->priv; 1095 } 1096 1097 #ifdef CONFIG_PM 1098 extern int ufshcd_runtime_suspend(struct device *dev); 1099 extern int ufshcd_runtime_resume(struct device *dev); 1100 #endif 1101 #ifdef CONFIG_PM_SLEEP 1102 extern int ufshcd_system_suspend(struct device *dev); 1103 extern int ufshcd_system_resume(struct device *dev); 1104 #endif 1105 extern int ufshcd_shutdown(struct ufs_hba *hba); 1106 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 1107 int agreed_gear, 1108 int adapt_val); 1109 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 1110 u8 attr_set, u32 mib_val, u8 peer); 1111 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 1112 u32 *mib_val, u8 peer); 1113 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, 1114 struct ufs_pa_layer_attr *desired_pwr_mode); 1115 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); 1116 1117 /* UIC command interfaces for DME primitives */ 1118 #define DME_LOCAL 0 1119 #define DME_PEER 1 1120 #define ATTR_SET_NOR 0 /* NORMAL */ 1121 #define ATTR_SET_ST 1 /* STATIC */ 1122 1123 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 1124 u32 mib_val) 1125 { 1126 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1127 mib_val, DME_LOCAL); 1128 } 1129 1130 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, 1131 u32 mib_val) 1132 { 1133 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1134 mib_val, DME_LOCAL); 1135 } 1136 1137 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 1138 u32 mib_val) 1139 { 1140 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1141 mib_val, DME_PEER); 1142 } 1143 1144 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, 1145 u32 mib_val) 1146 { 1147 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1148 mib_val, DME_PEER); 1149 } 1150 1151 static inline int ufshcd_dme_get(struct ufs_hba *hba, 1152 u32 attr_sel, u32 *mib_val) 1153 { 1154 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 1155 } 1156 1157 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 1158 u32 attr_sel, u32 *mib_val) 1159 { 1160 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 1161 } 1162 1163 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) 1164 { 1165 return (pwr_info->pwr_rx == FAST_MODE || 1166 pwr_info->pwr_rx == FASTAUTO_MODE) && 1167 (pwr_info->pwr_tx == FAST_MODE || 1168 pwr_info->pwr_tx == FASTAUTO_MODE); 1169 } 1170 1171 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) 1172 { 1173 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); 1174 } 1175 1176 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); 1177 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); 1178 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 1179 const struct ufs_dev_quirk *fixups); 1180 #define SD_ASCII_STD true 1181 #define SD_RAW false 1182 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 1183 u8 **buf, bool ascii); 1184 1185 int ufshcd_hold(struct ufs_hba *hba, bool async); 1186 void ufshcd_release(struct ufs_hba *hba); 1187 1188 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); 1189 1190 void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, 1191 int *desc_length); 1192 1193 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); 1194 1195 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); 1196 1197 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); 1198 1199 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 1200 struct utp_upiu_req *req_upiu, 1201 struct utp_upiu_req *rsp_upiu, 1202 int msgcode, 1203 u8 *desc_buff, int *buff_len, 1204 enum query_opcode desc_op); 1205 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 1206 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, 1207 struct ufs_ehs *ehs_rsp, int sg_cnt, 1208 struct scatterlist *sg_list, enum dma_data_direction dir); 1209 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); 1210 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); 1211 int ufshcd_suspend_prepare(struct device *dev); 1212 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); 1213 void ufshcd_resume_complete(struct device *dev); 1214 1215 /* Wrapper functions for safely calling variant operations */ 1216 static inline int ufshcd_vops_init(struct ufs_hba *hba) 1217 { 1218 if (hba->vops && hba->vops->init) 1219 return hba->vops->init(hba); 1220 1221 return 0; 1222 } 1223 1224 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) 1225 { 1226 if (hba->vops && hba->vops->phy_initialization) 1227 return hba->vops->phy_initialization(hba); 1228 1229 return 0; 1230 } 1231 1232 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; 1233 1234 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1235 const char *prefix); 1236 1237 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); 1238 int ufshcd_write_ee_control(struct ufs_hba *hba); 1239 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 1240 const u16 *other_mask, u16 set, u16 clr); 1241 1242 #endif /* End of Header */ 1243