1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * 6 * Authors: 7 * Santosh Yaraganavi <santosh.sy@samsung.com> 8 * Vinayak Holikatti <h.vinayak@samsung.com> 9 */ 10 11 #ifndef _UFS_H 12 #define _UFS_H 13 14 #include <linux/bitops.h> 15 #include <linux/types.h> 16 #include <uapi/scsi/scsi_bsg_ufs.h> 17 #include <linux/time64.h> 18 19 /* 20 * Using static_assert() is not allowed in UAPI header files. Hence the check 21 * in this header file of the size of struct utp_upiu_header. 22 */ 23 static_assert(sizeof(struct utp_upiu_header) == 12); 24 static_assert(sizeof(struct utp_upiu_query) == 20); 25 26 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req)) 27 #define QUERY_DESC_MAX_SIZE 255 28 #define QUERY_DESC_MIN_SIZE 2 29 #define QUERY_DESC_HDR_SIZE 2 30 #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \ 31 (sizeof(struct utp_upiu_header))) 32 #define UFS_SENSE_SIZE 18 33 34 /* 35 * UFS device may have standard LUs and LUN id could be from 0x00 to 36 * 0x7F. Standard LUs use "Peripheral Device Addressing Format". 37 * UFS device may also have the Well Known LUs (also referred as W-LU) 38 * which again could be from 0x00 to 0x7F. For W-LUs, device only use 39 * the "Extended Addressing Format" which means the W-LUNs would be 40 * from 0xc100 (SCSI_W_LUN_BASE) onwards. 41 * This means max. LUN number reported from UFS device could be 0xC17F. 42 */ 43 #define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F 44 #define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID) 45 #define UFS_UPIU_WLUN_ID (1 << 7) 46 47 /* WriteBooster buffer is available only for the logical unit from 0 to 7 */ 48 #define UFS_UPIU_MAX_WB_LUN_ID 8 49 50 /* 51 * WriteBooster buffer lifetime has a limit setted by vendor. 52 * If it is over the limit, WriteBooster feature will be disabled. 53 */ 54 #define UFS_WB_EXCEED_LIFETIME 0x0B 55 56 /* 57 * In UFS Spec, the Extra Header Segment (EHS) starts from byte 32 in UPIU request/response packet 58 */ 59 #define EHS_OFFSET_IN_RESPONSE 32 60 61 /* Well known logical unit id in LUN field of UPIU */ 62 enum { 63 UFS_UPIU_REPORT_LUNS_WLUN = 0x81, 64 UFS_UPIU_UFS_DEVICE_WLUN = 0xD0, 65 UFS_UPIU_BOOT_WLUN = 0xB0, 66 UFS_UPIU_RPMB_WLUN = 0xC4, 67 }; 68 69 /* 70 * UFS Protocol Information Unit related definitions 71 */ 72 73 /* Task management functions */ 74 enum { 75 UFS_ABORT_TASK = 0x01, 76 UFS_ABORT_TASK_SET = 0x02, 77 UFS_CLEAR_TASK_SET = 0x04, 78 UFS_LOGICAL_RESET = 0x08, 79 UFS_QUERY_TASK = 0x80, 80 UFS_QUERY_TASK_SET = 0x81, 81 }; 82 83 /* UTP UPIU Transaction Codes Initiator to Target */ 84 enum upiu_request_transaction { 85 UPIU_TRANSACTION_NOP_OUT = 0x00, 86 UPIU_TRANSACTION_COMMAND = 0x01, 87 UPIU_TRANSACTION_DATA_OUT = 0x02, 88 UPIU_TRANSACTION_TASK_REQ = 0x04, 89 UPIU_TRANSACTION_QUERY_REQ = 0x16, 90 }; 91 92 /* UTP UPIU Transaction Codes Target to Initiator */ 93 enum upiu_response_transaction { 94 UPIU_TRANSACTION_NOP_IN = 0x20, 95 UPIU_TRANSACTION_RESPONSE = 0x21, 96 UPIU_TRANSACTION_DATA_IN = 0x22, 97 UPIU_TRANSACTION_TASK_RSP = 0x24, 98 UPIU_TRANSACTION_READY_XFER = 0x31, 99 UPIU_TRANSACTION_QUERY_RSP = 0x36, 100 UPIU_TRANSACTION_REJECT_UPIU = 0x3F, 101 }; 102 103 /* UPIU Read/Write flags. See also table "UPIU Flags" in the UFS standard. */ 104 enum { 105 UPIU_CMD_FLAGS_NONE = 0x00, 106 UPIU_CMD_FLAGS_CP = 0x04, 107 UPIU_CMD_FLAGS_WRITE = 0x20, 108 UPIU_CMD_FLAGS_READ = 0x40, 109 }; 110 111 /* UPIU response flags */ 112 enum { 113 UPIU_RSP_FLAG_UNDERFLOW = 0x20, 114 UPIU_RSP_FLAG_OVERFLOW = 0x40, 115 }; 116 117 /* UPIU Task Attributes */ 118 enum { 119 UPIU_TASK_ATTR_SIMPLE = 0x00, 120 UPIU_TASK_ATTR_ORDERED = 0x01, 121 UPIU_TASK_ATTR_HEADQ = 0x02, 122 UPIU_TASK_ATTR_ACA = 0x03, 123 }; 124 125 /* UPIU Query request function */ 126 enum { 127 UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01, 128 UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81, 129 }; 130 131 /* Flag idn for Query Requests*/ 132 enum flag_idn { 133 QUERY_FLAG_IDN_FDEVICEINIT = 0x01, 134 QUERY_FLAG_IDN_PERMANENT_WPE = 0x02, 135 QUERY_FLAG_IDN_PWR_ON_WPE = 0x03, 136 QUERY_FLAG_IDN_BKOPS_EN = 0x04, 137 QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05, 138 QUERY_FLAG_IDN_PURGE_ENABLE = 0x06, 139 QUERY_FLAG_IDN_RESERVED2 = 0x07, 140 QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08, 141 QUERY_FLAG_IDN_BUSY_RTC = 0x09, 142 QUERY_FLAG_IDN_RESERVED3 = 0x0A, 143 QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B, 144 QUERY_FLAG_IDN_WB_EN = 0x0E, 145 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F, 146 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10, 147 QUERY_FLAG_IDN_HPB_RESET = 0x11, 148 QUERY_FLAG_IDN_HPB_EN = 0x12, 149 }; 150 151 /* Attribute idn for Query requests */ 152 enum attr_idn { 153 QUERY_ATTR_IDN_BOOT_LU_EN = 0x00, 154 QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01, 155 QUERY_ATTR_IDN_POWER_MODE = 0x02, 156 QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03, 157 QUERY_ATTR_IDN_OOO_DATA_EN = 0x04, 158 QUERY_ATTR_IDN_BKOPS_STATUS = 0x05, 159 QUERY_ATTR_IDN_PURGE_STATUS = 0x06, 160 QUERY_ATTR_IDN_MAX_DATA_IN = 0x07, 161 QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08, 162 QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09, 163 QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A, 164 QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B, 165 QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C, 166 QUERY_ATTR_IDN_EE_CONTROL = 0x0D, 167 QUERY_ATTR_IDN_EE_STATUS = 0x0E, 168 QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F, 169 QUERY_ATTR_IDN_CNTX_CONF = 0x10, 170 QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11, 171 QUERY_ATTR_IDN_RESERVED2 = 0x12, 172 QUERY_ATTR_IDN_RESERVED3 = 0x13, 173 QUERY_ATTR_IDN_FFU_STATUS = 0x14, 174 QUERY_ATTR_IDN_PSA_STATE = 0x15, 175 QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16, 176 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17, 177 QUERY_ATTR_IDN_CASE_ROUGH_TEMP = 0x18, 178 QUERY_ATTR_IDN_HIGH_TEMP_BOUND = 0x19, 179 QUERY_ATTR_IDN_LOW_TEMP_BOUND = 0x1A, 180 QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C, 181 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D, 182 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E, 183 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F, 184 QUERY_ATTR_IDN_TIMESTAMP = 0x30, 185 QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID = 0x34, 186 QUERY_ATTR_IDN_HID_DEFRAG_OPERATION = 0x35, 187 QUERY_ATTR_IDN_HID_AVAILABLE_SIZE = 0x36, 188 QUERY_ATTR_IDN_HID_SIZE = 0x37, 189 QUERY_ATTR_IDN_HID_PROGRESS_RATIO = 0x38, 190 QUERY_ATTR_IDN_HID_STATE = 0x39, 191 QUERY_ATTR_IDN_WB_BUF_RESIZE_HINT = 0x3C, 192 QUERY_ATTR_IDN_WB_BUF_RESIZE_EN = 0x3D, 193 QUERY_ATTR_IDN_WB_BUF_RESIZE_STATUS = 0x3E, 194 QUERY_ATTR_IDN_TX_EQ_GN_SETTINGS = 0x47, 195 QUERY_ATTR_IDN_TX_EQ_GN_SETTINGS_EXT = 0x48, 196 }; 197 198 /* Descriptor idn for Query requests */ 199 enum desc_idn { 200 QUERY_DESC_IDN_DEVICE = 0x0, 201 QUERY_DESC_IDN_CONFIGURATION = 0x1, 202 QUERY_DESC_IDN_UNIT = 0x2, 203 QUERY_DESC_IDN_RFU_0 = 0x3, 204 QUERY_DESC_IDN_INTERCONNECT = 0x4, 205 QUERY_DESC_IDN_STRING = 0x5, 206 QUERY_DESC_IDN_RFU_1 = 0x6, 207 QUERY_DESC_IDN_GEOMETRY = 0x7, 208 QUERY_DESC_IDN_POWER = 0x8, 209 QUERY_DESC_IDN_HEALTH = 0x9, 210 QUERY_DESC_IDN_MAX, 211 }; 212 213 enum desc_header_offset { 214 QUERY_DESC_LENGTH_OFFSET = 0x00, 215 QUERY_DESC_DESC_TYPE_OFFSET = 0x01, 216 }; 217 218 /* Unit descriptor parameters offsets in bytes*/ 219 enum unit_desc_param { 220 UNIT_DESC_PARAM_LEN = 0x0, 221 UNIT_DESC_PARAM_TYPE = 0x1, 222 UNIT_DESC_PARAM_UNIT_INDEX = 0x2, 223 UNIT_DESC_PARAM_LU_ENABLE = 0x3, 224 UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4, 225 UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5, 226 UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6, 227 UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7, 228 UNIT_DESC_PARAM_MEM_TYPE = 0x8, 229 UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9, 230 UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA, 231 UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB, 232 UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13, 233 UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17, 234 UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18, 235 UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20, 236 UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22, 237 UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23, 238 UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25, 239 UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27, 240 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29, 241 }; 242 243 /* RPMB Unit descriptor parameters offsets in bytes*/ 244 enum rpmb_unit_desc_param { 245 RPMB_UNIT_DESC_PARAM_LEN = 0x0, 246 RPMB_UNIT_DESC_PARAM_TYPE = 0x1, 247 RPMB_UNIT_DESC_PARAM_UNIT_INDEX = 0x2, 248 RPMB_UNIT_DESC_PARAM_LU_ENABLE = 0x3, 249 RPMB_UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4, 250 RPMB_UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5, 251 RPMB_UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6, 252 RPMB_UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7, 253 RPMB_UNIT_DESC_PARAM_MEM_TYPE = 0x8, 254 RPMB_UNIT_DESC_PARAM_REGION_EN = 0x9, 255 RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA, 256 RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB, 257 RPMB_UNIT_DESC_PARAM_REGION0_SIZE = 0x13, 258 RPMB_UNIT_DESC_PARAM_REGION1_SIZE = 0x14, 259 RPMB_UNIT_DESC_PARAM_REGION2_SIZE = 0x15, 260 RPMB_UNIT_DESC_PARAM_REGION3_SIZE = 0x16, 261 RPMB_UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17, 262 RPMB_UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18, 263 }; 264 265 /* Device descriptor parameters offsets in bytes*/ 266 enum device_desc_param { 267 DEVICE_DESC_PARAM_LEN = 0x0, 268 DEVICE_DESC_PARAM_TYPE = 0x1, 269 DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2, 270 DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3, 271 DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4, 272 DEVICE_DESC_PARAM_PRTCL = 0x5, 273 DEVICE_DESC_PARAM_NUM_LU = 0x6, 274 DEVICE_DESC_PARAM_NUM_WLU = 0x7, 275 DEVICE_DESC_PARAM_BOOT_ENBL = 0x8, 276 DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9, 277 DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA, 278 DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB, 279 DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC, 280 DEVICE_DESC_PARAM_SEC_LU = 0xD, 281 DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE, 282 DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF, 283 DEVICE_DESC_PARAM_SPEC_VER = 0x10, 284 DEVICE_DESC_PARAM_MANF_DATE = 0x12, 285 DEVICE_DESC_PARAM_MANF_NAME = 0x14, 286 DEVICE_DESC_PARAM_PRDCT_NAME = 0x15, 287 DEVICE_DESC_PARAM_SN = 0x16, 288 DEVICE_DESC_PARAM_OEM_ID = 0x17, 289 DEVICE_DESC_PARAM_MANF_ID = 0x18, 290 DEVICE_DESC_PARAM_UD_OFFSET = 0x1A, 291 DEVICE_DESC_PARAM_UD_LEN = 0x1B, 292 DEVICE_DESC_PARAM_RTT_CAP = 0x1C, 293 DEVICE_DESC_PARAM_FRQ_RTC = 0x1D, 294 DEVICE_DESC_PARAM_UFS_FEAT = 0x1F, 295 DEVICE_DESC_PARAM_FFU_TMT = 0x20, 296 DEVICE_DESC_PARAM_Q_DPTH = 0x21, 297 DEVICE_DESC_PARAM_DEV_VER = 0x22, 298 DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24, 299 DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25, 300 DEVICE_DESC_PARAM_PSA_TMT = 0x29, 301 DEVICE_DESC_PARAM_PRDCT_REV = 0x2A, 302 DEVICE_DESC_PARAM_HPB_VER = 0x40, 303 DEVICE_DESC_PARAM_HPB_CONTROL = 0x42, 304 DEVICE_DESC_PARAM_EXT_WB_SUP = 0x4D, 305 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F, 306 DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53, 307 DEVICE_DESC_PARAM_WB_TYPE = 0x54, 308 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55, 309 }; 310 311 /* Interconnect descriptor parameters offsets in bytes*/ 312 enum interconnect_desc_param { 313 INTERCONNECT_DESC_PARAM_LEN = 0x0, 314 INTERCONNECT_DESC_PARAM_TYPE = 0x1, 315 INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2, 316 INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4, 317 }; 318 319 /* Geometry descriptor parameters offsets in bytes*/ 320 enum geometry_desc_param { 321 GEOMETRY_DESC_PARAM_LEN = 0x0, 322 GEOMETRY_DESC_PARAM_TYPE = 0x1, 323 GEOMETRY_DESC_PARAM_DEV_CAP = 0x4, 324 GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC, 325 GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD, 326 GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11, 327 GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12, 328 GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13, 329 GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14, 330 GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15, 331 GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16, 332 GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17, 333 GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18, 334 GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19, 335 GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A, 336 GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B, 337 GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C, 338 GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D, 339 GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E, 340 GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20, 341 GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24, 342 GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26, 343 GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A, 344 GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C, 345 GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30, 346 GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32, 347 GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36, 348 GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38, 349 GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C, 350 GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E, 351 GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42, 352 GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44, 353 GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48, 354 GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49, 355 GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A, 356 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B, 357 GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F, 358 GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53, 359 GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54, 360 GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55, 361 GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56, 362 }; 363 364 /* Health descriptor parameters offsets in bytes*/ 365 enum health_desc_param { 366 HEALTH_DESC_PARAM_LEN = 0x0, 367 HEALTH_DESC_PARAM_TYPE = 0x1, 368 HEALTH_DESC_PARAM_EOL_INFO = 0x2, 369 HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3, 370 HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4, 371 }; 372 373 /* WriteBooster buffer mode */ 374 enum { 375 WB_BUF_MODE_LU_DEDICATED = 0x0, 376 WB_BUF_MODE_SHARED = 0x1, 377 }; 378 379 /* 380 * Logical Unit Write Protect 381 * 00h: LU not write protected 382 * 01h: LU write protected when fPowerOnWPEn =1 383 * 02h: LU permanently write protected when fPermanentWPEn =1 384 */ 385 enum ufs_lu_wp_type { 386 UFS_LU_NO_WP = 0x00, 387 UFS_LU_POWER_ON_WP = 0x01, 388 UFS_LU_PERM_WP = 0x02, 389 }; 390 391 /* bActiveICCLevel parameter current units */ 392 enum { 393 UFSHCD_NANO_AMP = 0, 394 UFSHCD_MICRO_AMP = 1, 395 UFSHCD_MILI_AMP = 2, 396 UFSHCD_AMP = 3, 397 }; 398 399 /* Possible values for wExtendedWriteBoosterSupport */ 400 enum { 401 UFS_DEV_WB_BUF_RESIZE = BIT(0), 402 }; 403 404 /* Possible values for dExtendedUFSFeaturesSupport */ 405 enum { 406 UFS_DEV_HIGH_TEMP_NOTIF = BIT(4), 407 UFS_DEV_LOW_TEMP_NOTIF = BIT(5), 408 UFS_DEV_EXT_TEMP_NOTIF = BIT(6), 409 UFS_DEV_HPB_SUPPORT = BIT(7), 410 UFS_DEV_WRITE_BOOSTER_SUP = BIT(8), 411 UFS_DEV_LVL_EXCEPTION_SUP = BIT(12), 412 UFS_DEV_HID_SUPPORT = BIT(13), 413 }; 414 #define UFS_DEV_HPB_SUPPORT_VERSION 0x310 415 416 #define POWER_DESC_MAX_ACTV_ICC_LVLS 16 417 418 /* Attribute bActiveICCLevel parameter bit masks definitions */ 419 #define ATTR_ICC_LVL_UNIT_OFFSET 14 420 #define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET) 421 #define ATTR_ICC_LVL_VALUE_MASK 0x3FF 422 423 /* Power descriptor parameters offsets in bytes */ 424 enum power_desc_param_offset { 425 PWR_DESC_LEN = 0x0, 426 PWR_DESC_TYPE = 0x1, 427 PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2, 428 PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22, 429 PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42, 430 }; 431 432 /* Exception event mask values */ 433 enum { 434 MASK_EE_STATUS = 0xFFFF, 435 MASK_EE_DYNCAP_EVENT = BIT(0), 436 MASK_EE_SYSPOOL_EVENT = BIT(1), 437 MASK_EE_URGENT_BKOPS = BIT(2), 438 MASK_EE_TOO_HIGH_TEMP = BIT(3), 439 MASK_EE_TOO_LOW_TEMP = BIT(4), 440 MASK_EE_WRITEBOOSTER_EVENT = BIT(5), 441 MASK_EE_PERFORMANCE_THROTTLING = BIT(6), 442 MASK_EE_DEV_LVL_EXCEPTION = BIT(7), 443 MASK_EE_HEALTH_CRITICAL = BIT(9), 444 }; 445 #define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_TEMP | MASK_EE_TOO_LOW_TEMP) 446 447 /* Background operation status */ 448 enum bkops_status { 449 BKOPS_STATUS_NO_OP = 0x0, 450 BKOPS_STATUS_NON_CRITICAL = 0x1, 451 BKOPS_STATUS_PERF_IMPACT = 0x2, 452 BKOPS_STATUS_CRITICAL = 0x3, 453 BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL, 454 }; 455 456 /* UTP QUERY Transaction Specific Fields OpCode */ 457 enum query_opcode { 458 UPIU_QUERY_OPCODE_NOP = 0x0, 459 UPIU_QUERY_OPCODE_READ_DESC = 0x1, 460 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, 461 UPIU_QUERY_OPCODE_READ_ATTR = 0x3, 462 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, 463 UPIU_QUERY_OPCODE_READ_FLAG = 0x5, 464 UPIU_QUERY_OPCODE_SET_FLAG = 0x6, 465 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, 466 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, 467 }; 468 469 /* bRefClkFreq attribute values */ 470 enum ufs_ref_clk_freq { 471 REF_CLK_FREQ_19_2_MHZ = 0, 472 REF_CLK_FREQ_26_MHZ = 1, 473 REF_CLK_FREQ_38_4_MHZ = 2, 474 REF_CLK_FREQ_52_MHZ = 3, 475 REF_CLK_FREQ_INVAL = -1, 476 }; 477 478 /* bDefragOperation attribute values */ 479 enum ufs_hid_defrag_operation { 480 HID_ANALYSIS_AND_DEFRAG_DISABLE = 0, 481 HID_ANALYSIS_ENABLE = 1, 482 HID_ANALYSIS_AND_DEFRAG_ENABLE = 2, 483 }; 484 485 /* bHIDState attribute values */ 486 enum ufs_hid_state { 487 HID_IDLE = 0, 488 ANALYSIS_IN_PROGRESS = 1, 489 DEFRAG_REQUIRED = 2, 490 DEFRAG_IN_PROGRESS = 3, 491 DEFRAG_COMPLETED = 4, 492 DEFRAG_NOT_REQUIRED = 5, 493 NUM_UFS_HID_STATES = 6, 494 }; 495 496 /* bWriteBoosterBufferResizeEn attribute */ 497 enum wb_resize_en { 498 WB_RESIZE_EN_IDLE = 0, 499 WB_RESIZE_EN_DECREASE = 1, 500 WB_RESIZE_EN_INCREASE = 2, 501 }; 502 503 /* bWriteBoosterBufferResizeHint attribute */ 504 enum wb_resize_hint { 505 WB_RESIZE_HINT_KEEP = 0, 506 WB_RESIZE_HINT_DECREASE = 1, 507 WB_RESIZE_HINT_INCREASE = 2, 508 }; 509 510 /* bWriteBoosterBufferResizeStatus attribute */ 511 enum wb_resize_status { 512 WB_RESIZE_STATUS_IDLE = 0, 513 WB_RESIZE_STATUS_IN_PROGRESS = 1, 514 WB_RESIZE_STATUS_COMPLETE_SUCCESS = 2, 515 WB_RESIZE_STATUS_GENERAL_FAILURE = 3, 516 }; 517 518 /* Query response result code */ 519 enum { 520 QUERY_RESULT_SUCCESS = 0x00, 521 QUERY_RESULT_NOT_READABLE = 0xF6, 522 QUERY_RESULT_NOT_WRITEABLE = 0xF7, 523 QUERY_RESULT_ALREADY_WRITTEN = 0xF8, 524 QUERY_RESULT_INVALID_LENGTH = 0xF9, 525 QUERY_RESULT_INVALID_VALUE = 0xFA, 526 QUERY_RESULT_INVALID_SELECTOR = 0xFB, 527 QUERY_RESULT_INVALID_INDEX = 0xFC, 528 QUERY_RESULT_INVALID_IDN = 0xFD, 529 QUERY_RESULT_INVALID_OPCODE = 0xFE, 530 QUERY_RESULT_GENERAL_FAILURE = 0xFF, 531 }; 532 533 /* UTP Transfer Request Command Type (CT) */ 534 enum { 535 UPIU_COMMAND_SET_TYPE_SCSI = 0x0, 536 UPIU_COMMAND_SET_TYPE_UFS = 0x1, 537 UPIU_COMMAND_SET_TYPE_QUERY = 0x2, 538 }; 539 540 /* Offset of the response code in the UPIU header */ 541 #define UPIU_RSP_CODE_OFFSET 8 542 543 enum { 544 MASK_TM_SERVICE_RESP = 0xFF, 545 }; 546 547 /* Task management service response */ 548 enum { 549 UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00, 550 UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04, 551 UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08, 552 UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05, 553 UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09, 554 }; 555 556 /* UFS device power modes */ 557 enum ufs_dev_pwr_mode { 558 UFS_ACTIVE_PWR_MODE = 1, 559 UFS_SLEEP_PWR_MODE = 2, 560 UFS_POWERDOWN_PWR_MODE = 3, 561 UFS_DEEPSLEEP_PWR_MODE = 4, 562 }; 563 564 #define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10) 565 566 /** 567 * struct utp_cmd_rsp - RESPONSE UPIU structure 568 * @residual_transfer_count: Residual transfer count DW-3 569 * @reserved: Reserved double words DW-4 to DW-7 570 * @sense_data_len: Sense data length DW-8 U16 571 * @sense_data: Sense data field DW-8 to DW-12 572 */ 573 struct utp_cmd_rsp { 574 __be32 residual_transfer_count; 575 __be32 reserved[4]; 576 __be16 sense_data_len; 577 u8 sense_data[UFS_SENSE_SIZE]; 578 }; 579 580 static_assert(sizeof(struct utp_cmd_rsp) == 40); 581 582 /** 583 * struct utp_upiu_rsp - general upiu response structure 584 * @header: UPIU header structure DW-0 to DW-2 585 * @sr: fields structure for scsi command DW-3 to DW-12 586 * @qr: fields structure for query request DW-3 to DW-7 587 */ 588 struct utp_upiu_rsp { 589 struct utp_upiu_header header; 590 union { 591 struct utp_cmd_rsp sr; 592 struct utp_upiu_query qr; 593 }; 594 }; 595 596 /* 597 * VCCQ & VCCQ2 current requirement when UFS device is in sleep state 598 * and link is in Hibern8 state. 599 */ 600 #define UFS_VREG_LPM_LOAD_UA 1000 /* uA */ 601 602 struct ufs_vreg { 603 struct regulator *reg; 604 const char *name; 605 bool always_on; 606 bool enabled; 607 int max_uA; 608 }; 609 610 struct ufs_vreg_info { 611 struct ufs_vreg *vcc; 612 struct ufs_vreg *vccq; 613 struct ufs_vreg *vccq2; 614 struct ufs_vreg *vdd_hba; 615 }; 616 617 /* UFS device descriptor wPeriodicRTCUpdate bit9 defines RTC time baseline */ 618 #define UFS_RTC_TIME_BASELINE BIT(9) 619 620 enum ufs_rtc_time { 621 UFS_RTC_RELATIVE, 622 UFS_RTC_ABSOLUTE 623 }; 624 625 struct ufs_dev_info { 626 bool f_power_on_wp_en; 627 /* Keeps information if any of the LU is power on write protected */ 628 bool is_lu_power_on_wp; 629 /* Maximum number of general LU supported by the UFS device */ 630 u8 max_lu_supported; 631 u16 wmanufacturerid; 632 /*UFS device Product Name */ 633 u8 *model; 634 u16 wspecversion; 635 u32 clk_gating_wait_us; 636 /* Stores the depth of queue in UFS device */ 637 u8 bqueuedepth; 638 639 /* UFS WB related flags */ 640 bool wb_enabled; 641 bool wb_buf_flush_enabled; 642 u8 wb_dedicated_lu; 643 u8 wb_buffer_type; 644 u16 ext_wb_sup; 645 646 bool b_rpm_dev_flush_capable; 647 u8 b_presrv_uspc_en; 648 649 bool b_advanced_rpmb_en; 650 651 /* UFS RTC */ 652 enum ufs_rtc_time rtc_type; 653 time64_t rtc_time_baseline; 654 u32 rtc_update_period; 655 656 u8 rtt_cap; /* bDeviceRTTCap */ 657 658 bool hid_sup; 659 660 /* Unique device ID string (manufacturer+model+serial+version+date) */ 661 char *device_id; 662 u8 rpmb_io_size; 663 u8 rpmb_region_size[4]; 664 }; 665 666 #endif /* End of Header */ 667