1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * 6 * Authors: 7 * Santosh Yaraganavi <santosh.sy@samsung.com> 8 * Vinayak Holikatti <h.vinayak@samsung.com> 9 */ 10 11 #ifndef _UFS_H 12 #define _UFS_H 13 14 #include <linux/bitops.h> 15 #include <linux/types.h> 16 #include <uapi/scsi/scsi_bsg_ufs.h> 17 #include <linux/time64.h> 18 19 /* 20 * Using static_assert() is not allowed in UAPI header files. Hence the check 21 * in this header file of the size of struct utp_upiu_header. 22 */ 23 static_assert(sizeof(struct utp_upiu_header) == 12); 24 static_assert(sizeof(struct utp_upiu_query) == 20); 25 26 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req)) 27 #define QUERY_DESC_MAX_SIZE 255 28 /* 29 * Max aggregated read data segment: the devman response area 30 * (ALIGNED_DEVMAN_RSP_SIZE) minus the fixed UPIU header it follows. 31 */ 32 #define QUERY_AGGREGATED_MAX_SIZE (4096 - GENERAL_UPIU_REQUEST_SIZE) 33 #define QUERY_DESC_MIN_SIZE 2 34 #define QUERY_DESC_HDR_SIZE 2 35 #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \ 36 (sizeof(struct utp_upiu_header))) 37 #define UFS_SENSE_SIZE 18 38 39 /* 40 * UFS device may have standard LUs and LUN id could be from 0x00 to 41 * 0x7F. Standard LUs use "Peripheral Device Addressing Format". 42 * UFS device may also have the Well Known LUs (also referred as W-LU) 43 * which again could be from 0x00 to 0x7F. For W-LUs, device only use 44 * the "Extended Addressing Format" which means the W-LUNs would be 45 * from 0xc100 (SCSI_W_LUN_BASE) onwards. 46 * This means max. LUN number reported from UFS device could be 0xC17F. 47 */ 48 #define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F 49 #define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID) 50 #define UFS_UPIU_WLUN_ID (1 << 7) 51 52 /* WriteBooster buffer is available only for the logical unit from 0 to 7 */ 53 #define UFS_UPIU_MAX_WB_LUN_ID 8 54 55 /* 56 * WriteBooster buffer lifetime has a limit setted by vendor. 57 * If it is over the limit, WriteBooster feature will be disabled. 58 */ 59 #define UFS_WB_EXCEED_LIFETIME 0x0B 60 61 /* 62 * In UFS Spec, the Extra Header Segment (EHS) starts from byte 32 in UPIU request/response packet 63 */ 64 #define EHS_OFFSET_IN_RESPONSE 32 65 66 /* Well known logical unit id in LUN field of UPIU */ 67 enum { 68 UFS_UPIU_REPORT_LUNS_WLUN = 0x81, 69 UFS_UPIU_UFS_DEVICE_WLUN = 0xD0, 70 UFS_UPIU_BOOT_WLUN = 0xB0, 71 UFS_UPIU_RPMB_WLUN = 0xC4, 72 }; 73 74 /* 75 * UFS Protocol Information Unit related definitions 76 */ 77 78 /* Task management functions */ 79 enum { 80 UFS_ABORT_TASK = 0x01, 81 UFS_ABORT_TASK_SET = 0x02, 82 UFS_CLEAR_TASK_SET = 0x04, 83 UFS_LOGICAL_RESET = 0x08, 84 UFS_QUERY_TASK = 0x80, 85 UFS_QUERY_TASK_SET = 0x81, 86 }; 87 88 /* UTP UPIU Transaction Codes Initiator to Target */ 89 enum upiu_request_transaction { 90 UPIU_TRANSACTION_NOP_OUT = 0x00, 91 UPIU_TRANSACTION_COMMAND = 0x01, 92 UPIU_TRANSACTION_DATA_OUT = 0x02, 93 UPIU_TRANSACTION_TASK_REQ = 0x04, 94 UPIU_TRANSACTION_QUERY_REQ = 0x16, 95 }; 96 97 /* UTP UPIU Transaction Codes Target to Initiator */ 98 enum upiu_response_transaction { 99 UPIU_TRANSACTION_NOP_IN = 0x20, 100 UPIU_TRANSACTION_RESPONSE = 0x21, 101 UPIU_TRANSACTION_DATA_IN = 0x22, 102 UPIU_TRANSACTION_TASK_RSP = 0x24, 103 UPIU_TRANSACTION_READY_XFER = 0x31, 104 UPIU_TRANSACTION_QUERY_RSP = 0x36, 105 UPIU_TRANSACTION_REJECT_UPIU = 0x3F, 106 }; 107 108 /* UPIU Read/Write flags. See also table "UPIU Flags" in the UFS standard. */ 109 enum { 110 UPIU_CMD_FLAGS_NONE = 0x00, 111 UPIU_CMD_FLAGS_CP = 0x04, 112 UPIU_CMD_FLAGS_WRITE = 0x20, 113 UPIU_CMD_FLAGS_READ = 0x40, 114 }; 115 116 /* UPIU response flags */ 117 enum { 118 UPIU_RSP_FLAG_UNDERFLOW = 0x20, 119 UPIU_RSP_FLAG_OVERFLOW = 0x40, 120 }; 121 122 /* UPIU Task Attributes */ 123 enum { 124 UPIU_TASK_ATTR_SIMPLE = 0x00, 125 UPIU_TASK_ATTR_ORDERED = 0x01, 126 UPIU_TASK_ATTR_HEADQ = 0x02, 127 UPIU_TASK_ATTR_ACA = 0x03, 128 }; 129 130 /* UPIU Query request function */ 131 enum { 132 UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01, 133 UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81, 134 }; 135 136 /* Flag idn for Query Requests*/ 137 enum flag_idn { 138 QUERY_FLAG_IDN_FDEVICEINIT = 0x01, 139 QUERY_FLAG_IDN_PERMANENT_WPE = 0x02, 140 QUERY_FLAG_IDN_PWR_ON_WPE = 0x03, 141 QUERY_FLAG_IDN_BKOPS_EN = 0x04, 142 QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05, 143 QUERY_FLAG_IDN_PURGE_ENABLE = 0x06, 144 QUERY_FLAG_IDN_RESERVED2 = 0x07, 145 QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08, 146 QUERY_FLAG_IDN_BUSY_RTC = 0x09, 147 QUERY_FLAG_IDN_RESERVED3 = 0x0A, 148 QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B, 149 QUERY_FLAG_IDN_WB_EN = 0x0E, 150 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F, 151 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10, 152 QUERY_FLAG_IDN_HPB_RESET = 0x11, 153 QUERY_FLAG_IDN_HPB_EN = 0x12, 154 }; 155 156 /* Attribute idn for Query requests */ 157 enum attr_idn { 158 QUERY_ATTR_IDN_BOOT_LU_EN = 0x00, 159 QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01, 160 QUERY_ATTR_IDN_POWER_MODE = 0x02, 161 QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03, 162 QUERY_ATTR_IDN_OOO_DATA_EN = 0x04, 163 QUERY_ATTR_IDN_BKOPS_STATUS = 0x05, 164 QUERY_ATTR_IDN_PURGE_STATUS = 0x06, 165 QUERY_ATTR_IDN_MAX_DATA_IN = 0x07, 166 QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08, 167 QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09, 168 QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A, 169 QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B, 170 QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C, 171 QUERY_ATTR_IDN_EE_CONTROL = 0x0D, 172 QUERY_ATTR_IDN_EE_STATUS = 0x0E, 173 QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F, 174 QUERY_ATTR_IDN_CNTX_CONF = 0x10, 175 QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11, 176 QUERY_ATTR_IDN_RESERVED2 = 0x12, 177 QUERY_ATTR_IDN_RESERVED3 = 0x13, 178 QUERY_ATTR_IDN_FFU_STATUS = 0x14, 179 QUERY_ATTR_IDN_PSA_STATE = 0x15, 180 QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16, 181 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17, 182 QUERY_ATTR_IDN_CASE_ROUGH_TEMP = 0x18, 183 QUERY_ATTR_IDN_HIGH_TEMP_BOUND = 0x19, 184 QUERY_ATTR_IDN_LOW_TEMP_BOUND = 0x1A, 185 QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C, 186 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D, 187 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E, 188 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F, 189 QUERY_ATTR_IDN_TIMESTAMP = 0x30, 190 QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID = 0x34, 191 QUERY_ATTR_IDN_HID_DEFRAG_OPERATION = 0x35, 192 QUERY_ATTR_IDN_HID_AVAILABLE_SIZE = 0x36, 193 QUERY_ATTR_IDN_HID_SIZE = 0x37, 194 QUERY_ATTR_IDN_HID_PROGRESS_RATIO = 0x38, 195 QUERY_ATTR_IDN_HID_STATE = 0x39, 196 QUERY_ATTR_IDN_WB_BUF_RESIZE_HINT = 0x3C, 197 QUERY_ATTR_IDN_WB_BUF_RESIZE_EN = 0x3D, 198 QUERY_ATTR_IDN_WB_BUF_RESIZE_STATUS = 0x3E, 199 QUERY_ATTR_IDN_TX_EQ_GN_SETTINGS = 0x47, 200 QUERY_ATTR_IDN_TX_EQ_GN_SETTINGS_EXT = 0x48, 201 }; 202 203 /* Descriptor idn for Query requests */ 204 enum desc_idn { 205 QUERY_DESC_IDN_DEVICE = 0x0, 206 QUERY_DESC_IDN_CONFIGURATION = 0x1, 207 QUERY_DESC_IDN_UNIT = 0x2, 208 QUERY_DESC_IDN_RFU_0 = 0x3, 209 QUERY_DESC_IDN_INTERCONNECT = 0x4, 210 QUERY_DESC_IDN_STRING = 0x5, 211 QUERY_DESC_IDN_RFU_1 = 0x6, 212 QUERY_DESC_IDN_GEOMETRY = 0x7, 213 QUERY_DESC_IDN_POWER = 0x8, 214 QUERY_DESC_IDN_HEALTH = 0x9, 215 QUERY_DESC_IDN_MAX, 216 }; 217 218 enum desc_header_offset { 219 QUERY_DESC_LENGTH_OFFSET = 0x00, 220 QUERY_DESC_DESC_TYPE_OFFSET = 0x01, 221 }; 222 223 /* Unit descriptor parameters offsets in bytes*/ 224 enum unit_desc_param { 225 UNIT_DESC_PARAM_LEN = 0x0, 226 UNIT_DESC_PARAM_TYPE = 0x1, 227 UNIT_DESC_PARAM_UNIT_INDEX = 0x2, 228 UNIT_DESC_PARAM_LU_ENABLE = 0x3, 229 UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4, 230 UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5, 231 UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6, 232 UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7, 233 UNIT_DESC_PARAM_MEM_TYPE = 0x8, 234 UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9, 235 UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA, 236 UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB, 237 UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13, 238 UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17, 239 UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18, 240 UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20, 241 UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22, 242 UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23, 243 UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25, 244 UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27, 245 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29, 246 }; 247 248 /* RPMB Unit descriptor parameters offsets in bytes*/ 249 enum rpmb_unit_desc_param { 250 RPMB_UNIT_DESC_PARAM_LEN = 0x0, 251 RPMB_UNIT_DESC_PARAM_TYPE = 0x1, 252 RPMB_UNIT_DESC_PARAM_UNIT_INDEX = 0x2, 253 RPMB_UNIT_DESC_PARAM_LU_ENABLE = 0x3, 254 RPMB_UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4, 255 RPMB_UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5, 256 RPMB_UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6, 257 RPMB_UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7, 258 RPMB_UNIT_DESC_PARAM_MEM_TYPE = 0x8, 259 RPMB_UNIT_DESC_PARAM_REGION_EN = 0x9, 260 RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA, 261 RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB, 262 RPMB_UNIT_DESC_PARAM_REGION0_SIZE = 0x13, 263 RPMB_UNIT_DESC_PARAM_REGION1_SIZE = 0x14, 264 RPMB_UNIT_DESC_PARAM_REGION2_SIZE = 0x15, 265 RPMB_UNIT_DESC_PARAM_REGION3_SIZE = 0x16, 266 RPMB_UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17, 267 RPMB_UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18, 268 }; 269 270 /* Device descriptor parameters offsets in bytes*/ 271 enum device_desc_param { 272 DEVICE_DESC_PARAM_LEN = 0x0, 273 DEVICE_DESC_PARAM_TYPE = 0x1, 274 DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2, 275 DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3, 276 DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4, 277 DEVICE_DESC_PARAM_PRTCL = 0x5, 278 DEVICE_DESC_PARAM_NUM_LU = 0x6, 279 DEVICE_DESC_PARAM_NUM_WLU = 0x7, 280 DEVICE_DESC_PARAM_BOOT_ENBL = 0x8, 281 DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9, 282 DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA, 283 DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB, 284 DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC, 285 DEVICE_DESC_PARAM_SEC_LU = 0xD, 286 DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE, 287 DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF, 288 DEVICE_DESC_PARAM_SPEC_VER = 0x10, 289 DEVICE_DESC_PARAM_MANF_DATE = 0x12, 290 DEVICE_DESC_PARAM_MANF_NAME = 0x14, 291 DEVICE_DESC_PARAM_PRDCT_NAME = 0x15, 292 DEVICE_DESC_PARAM_SN = 0x16, 293 DEVICE_DESC_PARAM_OEM_ID = 0x17, 294 DEVICE_DESC_PARAM_MANF_ID = 0x18, 295 DEVICE_DESC_PARAM_UD_OFFSET = 0x1A, 296 DEVICE_DESC_PARAM_UD_LEN = 0x1B, 297 DEVICE_DESC_PARAM_RTT_CAP = 0x1C, 298 DEVICE_DESC_PARAM_FRQ_RTC = 0x1D, 299 DEVICE_DESC_PARAM_UFS_FEAT = 0x1F, 300 DEVICE_DESC_PARAM_FFU_TMT = 0x20, 301 DEVICE_DESC_PARAM_Q_DPTH = 0x21, 302 DEVICE_DESC_PARAM_DEV_VER = 0x22, 303 DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24, 304 DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25, 305 DEVICE_DESC_PARAM_PSA_TMT = 0x29, 306 DEVICE_DESC_PARAM_PRDCT_REV = 0x2A, 307 DEVICE_DESC_PARAM_HPB_VER = 0x40, 308 DEVICE_DESC_PARAM_HPB_CONTROL = 0x42, 309 DEVICE_DESC_PARAM_EXT_WB_SUP = 0x4D, 310 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F, 311 DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53, 312 DEVICE_DESC_PARAM_WB_TYPE = 0x54, 313 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55, 314 }; 315 316 /* Interconnect descriptor parameters offsets in bytes*/ 317 enum interconnect_desc_param { 318 INTERCONNECT_DESC_PARAM_LEN = 0x0, 319 INTERCONNECT_DESC_PARAM_TYPE = 0x1, 320 INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2, 321 INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4, 322 }; 323 324 /* Geometry descriptor parameters offsets in bytes*/ 325 enum geometry_desc_param { 326 GEOMETRY_DESC_PARAM_LEN = 0x0, 327 GEOMETRY_DESC_PARAM_TYPE = 0x1, 328 GEOMETRY_DESC_PARAM_DEV_CAP = 0x4, 329 GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC, 330 GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD, 331 GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11, 332 GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12, 333 GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13, 334 GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14, 335 GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15, 336 GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16, 337 GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17, 338 GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18, 339 GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19, 340 GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A, 341 GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B, 342 GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C, 343 GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D, 344 GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E, 345 GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20, 346 GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24, 347 GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26, 348 GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A, 349 GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C, 350 GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30, 351 GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32, 352 GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36, 353 GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38, 354 GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C, 355 GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E, 356 GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42, 357 GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44, 358 GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48, 359 GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49, 360 GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A, 361 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B, 362 GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F, 363 GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53, 364 GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54, 365 GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55, 366 GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56, 367 }; 368 369 /* Health descriptor parameters offsets in bytes*/ 370 enum health_desc_param { 371 HEALTH_DESC_PARAM_LEN = 0x0, 372 HEALTH_DESC_PARAM_TYPE = 0x1, 373 HEALTH_DESC_PARAM_EOL_INFO = 0x2, 374 HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3, 375 HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4, 376 }; 377 378 /* WriteBooster buffer mode */ 379 enum { 380 WB_BUF_MODE_LU_DEDICATED = 0x0, 381 WB_BUF_MODE_SHARED = 0x1, 382 }; 383 384 /* 385 * Logical Unit Write Protect 386 * 00h: LU not write protected 387 * 01h: LU write protected when fPowerOnWPEn =1 388 * 02h: LU permanently write protected when fPermanentWPEn =1 389 */ 390 enum ufs_lu_wp_type { 391 UFS_LU_NO_WP = 0x00, 392 UFS_LU_POWER_ON_WP = 0x01, 393 UFS_LU_PERM_WP = 0x02, 394 }; 395 396 /* bActiveICCLevel parameter current units */ 397 enum { 398 UFSHCD_NANO_AMP = 0, 399 UFSHCD_MICRO_AMP = 1, 400 UFSHCD_MILI_AMP = 2, 401 UFSHCD_AMP = 3, 402 }; 403 404 /* Possible values for wExtendedWriteBoosterSupport */ 405 enum { 406 UFS_DEV_WB_BUF_RESIZE = BIT(0), 407 }; 408 409 /* Possible values for dExtendedUFSFeaturesSupport */ 410 enum { 411 UFS_DEV_HIGH_TEMP_NOTIF = BIT(4), 412 UFS_DEV_LOW_TEMP_NOTIF = BIT(5), 413 UFS_DEV_EXT_TEMP_NOTIF = BIT(6), 414 UFS_DEV_HPB_SUPPORT = BIT(7), 415 UFS_DEV_WRITE_BOOSTER_SUP = BIT(8), 416 UFS_DEV_LVL_EXCEPTION_SUP = BIT(12), 417 UFS_DEV_HID_SUPPORT = BIT(13), 418 }; 419 #define UFS_DEV_HPB_SUPPORT_VERSION 0x310 420 421 #define POWER_DESC_MAX_ACTV_ICC_LVLS 16 422 423 /* Attribute bActiveICCLevel parameter bit masks definitions */ 424 #define ATTR_ICC_LVL_UNIT_OFFSET 14 425 #define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET) 426 #define ATTR_ICC_LVL_VALUE_MASK 0x3FF 427 428 /* Power descriptor parameters offsets in bytes */ 429 enum power_desc_param_offset { 430 PWR_DESC_LEN = 0x0, 431 PWR_DESC_TYPE = 0x1, 432 PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2, 433 PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22, 434 PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42, 435 }; 436 437 /* Exception event mask values */ 438 enum { 439 MASK_EE_STATUS = 0xFFFF, 440 MASK_EE_DYNCAP_EVENT = BIT(0), 441 MASK_EE_SYSPOOL_EVENT = BIT(1), 442 MASK_EE_URGENT_BKOPS = BIT(2), 443 MASK_EE_TOO_HIGH_TEMP = BIT(3), 444 MASK_EE_TOO_LOW_TEMP = BIT(4), 445 MASK_EE_WRITEBOOSTER_EVENT = BIT(5), 446 MASK_EE_PERFORMANCE_THROTTLING = BIT(6), 447 MASK_EE_DEV_LVL_EXCEPTION = BIT(7), 448 MASK_EE_HEALTH_CRITICAL = BIT(9), 449 }; 450 #define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_TEMP | MASK_EE_TOO_LOW_TEMP) 451 452 /* Background operation status */ 453 enum bkops_status { 454 BKOPS_STATUS_NO_OP = 0x0, 455 BKOPS_STATUS_NON_CRITICAL = 0x1, 456 BKOPS_STATUS_PERF_IMPACT = 0x2, 457 BKOPS_STATUS_CRITICAL = 0x3, 458 BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL, 459 }; 460 461 /* UTP QUERY Transaction Specific Fields OpCode */ 462 enum query_opcode { 463 UPIU_QUERY_OPCODE_NOP = 0x0, 464 UPIU_QUERY_OPCODE_READ_DESC = 0x1, 465 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2, 466 UPIU_QUERY_OPCODE_READ_ATTR = 0x3, 467 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4, 468 UPIU_QUERY_OPCODE_READ_FLAG = 0x5, 469 UPIU_QUERY_OPCODE_SET_FLAG = 0x6, 470 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7, 471 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8, 472 UPIU_QUERY_OPCODE_AGGREGATED_READ = 0x9, 473 }; 474 475 /* bRefClkFreq attribute values */ 476 enum ufs_ref_clk_freq { 477 REF_CLK_FREQ_19_2_MHZ = 0, 478 REF_CLK_FREQ_26_MHZ = 1, 479 REF_CLK_FREQ_38_4_MHZ = 2, 480 REF_CLK_FREQ_52_MHZ = 3, 481 REF_CLK_FREQ_INVAL = -1, 482 }; 483 484 /* bDefragOperation attribute values */ 485 enum ufs_hid_defrag_operation { 486 HID_ANALYSIS_AND_DEFRAG_DISABLE = 0, 487 HID_ANALYSIS_ENABLE = 1, 488 HID_ANALYSIS_AND_DEFRAG_ENABLE = 2, 489 }; 490 491 /* bHIDState attribute values */ 492 enum ufs_hid_state { 493 HID_IDLE = 0, 494 ANALYSIS_IN_PROGRESS = 1, 495 DEFRAG_REQUIRED = 2, 496 DEFRAG_IN_PROGRESS = 3, 497 DEFRAG_COMPLETED = 4, 498 DEFRAG_NOT_REQUIRED = 5, 499 NUM_UFS_HID_STATES = 6, 500 }; 501 502 /* bWriteBoosterBufferResizeEn attribute */ 503 enum wb_resize_en { 504 WB_RESIZE_EN_IDLE = 0, 505 WB_RESIZE_EN_DECREASE = 1, 506 WB_RESIZE_EN_INCREASE = 2, 507 }; 508 509 /* bWriteBoosterBufferResizeHint attribute */ 510 enum wb_resize_hint { 511 WB_RESIZE_HINT_KEEP = 0, 512 WB_RESIZE_HINT_DECREASE = 1, 513 WB_RESIZE_HINT_INCREASE = 2, 514 }; 515 516 /* bWriteBoosterBufferResizeStatus attribute */ 517 enum wb_resize_status { 518 WB_RESIZE_STATUS_IDLE = 0, 519 WB_RESIZE_STATUS_IN_PROGRESS = 1, 520 WB_RESIZE_STATUS_COMPLETE_SUCCESS = 2, 521 WB_RESIZE_STATUS_GENERAL_FAILURE = 3, 522 }; 523 524 /* Query response result code */ 525 enum { 526 QUERY_RESULT_SUCCESS = 0x00, 527 QUERY_RESULT_NOT_READABLE = 0xF6, 528 QUERY_RESULT_NOT_WRITEABLE = 0xF7, 529 QUERY_RESULT_ALREADY_WRITTEN = 0xF8, 530 QUERY_RESULT_INVALID_LENGTH = 0xF9, 531 QUERY_RESULT_INVALID_VALUE = 0xFA, 532 QUERY_RESULT_INVALID_SELECTOR = 0xFB, 533 QUERY_RESULT_INVALID_INDEX = 0xFC, 534 QUERY_RESULT_INVALID_IDN = 0xFD, 535 QUERY_RESULT_INVALID_OPCODE = 0xFE, 536 QUERY_RESULT_GENERAL_FAILURE = 0xFF, 537 }; 538 539 /* UTP Transfer Request Command Type (CT) */ 540 enum { 541 UPIU_COMMAND_SET_TYPE_SCSI = 0x0, 542 UPIU_COMMAND_SET_TYPE_UFS = 0x1, 543 UPIU_COMMAND_SET_TYPE_QUERY = 0x2, 544 }; 545 546 /* Offset of the response code in the UPIU header */ 547 #define UPIU_RSP_CODE_OFFSET 8 548 549 enum { 550 MASK_TM_SERVICE_RESP = 0xFF, 551 }; 552 553 /* Task management service response */ 554 enum { 555 UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00, 556 UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04, 557 UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08, 558 UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05, 559 UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09, 560 }; 561 562 /* UFS device power modes */ 563 enum ufs_dev_pwr_mode { 564 UFS_ACTIVE_PWR_MODE = 1, 565 UFS_SLEEP_PWR_MODE = 2, 566 UFS_POWERDOWN_PWR_MODE = 3, 567 UFS_DEEPSLEEP_PWR_MODE = 4, 568 }; 569 570 #define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10) 571 572 /** 573 * struct utp_cmd_rsp - RESPONSE UPIU structure 574 * @residual_transfer_count: Residual transfer count DW-3 575 * @reserved: Reserved double words DW-4 to DW-7 576 * @sense_data_len: Sense data length DW-8 U16 577 * @sense_data: Sense data field DW-8 to DW-12 578 */ 579 struct utp_cmd_rsp { 580 __be32 residual_transfer_count; 581 __be32 reserved[4]; 582 __be16 sense_data_len; 583 u8 sense_data[UFS_SENSE_SIZE]; 584 }; 585 586 static_assert(sizeof(struct utp_cmd_rsp) == 40); 587 588 /** 589 * struct utp_upiu_rsp - general upiu response structure 590 * @header: UPIU header structure DW-0 to DW-2 591 * @sr: fields structure for scsi command DW-3 to DW-12 592 * @qr: fields structure for query request DW-3 to DW-7 593 */ 594 struct utp_upiu_rsp { 595 struct utp_upiu_header header; 596 union { 597 struct utp_cmd_rsp sr; 598 struct utp_upiu_query qr; 599 }; 600 }; 601 602 /* 603 * VCCQ & VCCQ2 current requirement when UFS device is in sleep state 604 * and link is in Hibern8 state. 605 */ 606 #define UFS_VREG_LPM_LOAD_UA 1000 /* uA */ 607 608 struct ufs_vreg { 609 struct regulator *reg; 610 const char *name; 611 bool always_on; 612 bool enabled; 613 int max_uA; 614 }; 615 616 struct ufs_vreg_info { 617 struct ufs_vreg *vcc; 618 struct ufs_vreg *vccq; 619 struct ufs_vreg *vccq2; 620 struct ufs_vreg *vdd_hba; 621 }; 622 623 /* UFS device descriptor wPeriodicRTCUpdate bit9 defines RTC time baseline */ 624 #define UFS_RTC_TIME_BASELINE BIT(9) 625 626 enum ufs_rtc_time { 627 UFS_RTC_RELATIVE, 628 UFS_RTC_ABSOLUTE 629 }; 630 631 struct ufs_dev_info { 632 bool f_power_on_wp_en; 633 /* Keeps information if any of the LU is power on write protected */ 634 bool is_lu_power_on_wp; 635 /* Maximum number of general LU supported by the UFS device */ 636 u8 max_lu_supported; 637 u16 wmanufacturerid; 638 /*UFS device Product Name */ 639 u8 *model; 640 u16 wspecversion; 641 u32 clk_gating_wait_us; 642 /* Stores the depth of queue in UFS device */ 643 u8 bqueuedepth; 644 645 /* UFS WB related flags */ 646 bool wb_enabled; 647 bool wb_buf_flush_enabled; 648 u8 wb_dedicated_lu; 649 u8 wb_buffer_type; 650 u16 ext_wb_sup; 651 652 bool b_rpm_dev_flush_capable; 653 u8 b_presrv_uspc_en; 654 655 bool b_advanced_rpmb_en; 656 657 /* UFS RTC */ 658 enum ufs_rtc_time rtc_type; 659 time64_t rtc_time_baseline; 660 u32 rtc_update_period; 661 662 u8 rtt_cap; /* bDeviceRTTCap */ 663 664 bool hid_sup; 665 666 /* Unique device ID string (manufacturer+model+serial+version+date) */ 667 char *device_id; 668 u8 rpmb_io_size; 669 u8 rpmb_region_size[4]; 670 }; 671 672 #endif /* End of Header */ 673