1*29c8d9ebSAdit Ranadive /* 2*29c8d9ebSAdit Ranadive * Copyright (c) 2012-2016 VMware, Inc. All rights reserved. 3*29c8d9ebSAdit Ranadive * 4*29c8d9ebSAdit Ranadive * This program is free software; you can redistribute it and/or 5*29c8d9ebSAdit Ranadive * modify it under the terms of EITHER the GNU General Public License 6*29c8d9ebSAdit Ranadive * version 2 as published by the Free Software Foundation or the BSD 7*29c8d9ebSAdit Ranadive * 2-Clause License. This program is distributed in the hope that it 8*29c8d9ebSAdit Ranadive * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED 9*29c8d9ebSAdit Ranadive * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. 10*29c8d9ebSAdit Ranadive * See the GNU General Public License version 2 for more details at 11*29c8d9ebSAdit Ranadive * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html. 12*29c8d9ebSAdit Ranadive * 13*29c8d9ebSAdit Ranadive * You should have received a copy of the GNU General Public License 14*29c8d9ebSAdit Ranadive * along with this program available in the file COPYING in the main 15*29c8d9ebSAdit Ranadive * directory of this source tree. 16*29c8d9ebSAdit Ranadive * 17*29c8d9ebSAdit Ranadive * The BSD 2-Clause License 18*29c8d9ebSAdit Ranadive * 19*29c8d9ebSAdit Ranadive * Redistribution and use in source and binary forms, with or 20*29c8d9ebSAdit Ranadive * without modification, are permitted provided that the following 21*29c8d9ebSAdit Ranadive * conditions are met: 22*29c8d9ebSAdit Ranadive * 23*29c8d9ebSAdit Ranadive * - Redistributions of source code must retain the above 24*29c8d9ebSAdit Ranadive * copyright notice, this list of conditions and the following 25*29c8d9ebSAdit Ranadive * disclaimer. 26*29c8d9ebSAdit Ranadive * 27*29c8d9ebSAdit Ranadive * - Redistributions in binary form must reproduce the above 28*29c8d9ebSAdit Ranadive * copyright notice, this list of conditions and the following 29*29c8d9ebSAdit Ranadive * disclaimer in the documentation and/or other materials 30*29c8d9ebSAdit Ranadive * provided with the distribution. 31*29c8d9ebSAdit Ranadive * 32*29c8d9ebSAdit Ranadive * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33*29c8d9ebSAdit Ranadive * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34*29c8d9ebSAdit Ranadive * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35*29c8d9ebSAdit Ranadive * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36*29c8d9ebSAdit Ranadive * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 37*29c8d9ebSAdit Ranadive * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 38*29c8d9ebSAdit Ranadive * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 39*29c8d9ebSAdit Ranadive * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40*29c8d9ebSAdit Ranadive * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41*29c8d9ebSAdit Ranadive * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42*29c8d9ebSAdit Ranadive * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43*29c8d9ebSAdit Ranadive * OF THE POSSIBILITY OF SUCH DAMAGE. 44*29c8d9ebSAdit Ranadive */ 45*29c8d9ebSAdit Ranadive 46*29c8d9ebSAdit Ranadive #ifndef __VMW_PVRDMA_ABI_H__ 47*29c8d9ebSAdit Ranadive #define __VMW_PVRDMA_ABI_H__ 48*29c8d9ebSAdit Ranadive 49*29c8d9ebSAdit Ranadive #include <linux/types.h> 50*29c8d9ebSAdit Ranadive 51*29c8d9ebSAdit Ranadive #define PVRDMA_UVERBS_ABI_VERSION 3 /* ABI Version. */ 52*29c8d9ebSAdit Ranadive #define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF /* Bottom 24 bits. */ 53*29c8d9ebSAdit Ranadive #define PVRDMA_UAR_QP_OFFSET 0 /* QP doorbell. */ 54*29c8d9ebSAdit Ranadive #define PVRDMA_UAR_QP_SEND BIT(30) /* Send bit. */ 55*29c8d9ebSAdit Ranadive #define PVRDMA_UAR_QP_RECV BIT(31) /* Recv bit. */ 56*29c8d9ebSAdit Ranadive #define PVRDMA_UAR_CQ_OFFSET 4 /* CQ doorbell. */ 57*29c8d9ebSAdit Ranadive #define PVRDMA_UAR_CQ_ARM_SOL BIT(29) /* Arm solicited bit. */ 58*29c8d9ebSAdit Ranadive #define PVRDMA_UAR_CQ_ARM BIT(30) /* Arm bit. */ 59*29c8d9ebSAdit Ranadive #define PVRDMA_UAR_CQ_POLL BIT(31) /* Poll bit. */ 60*29c8d9ebSAdit Ranadive 61*29c8d9ebSAdit Ranadive enum pvrdma_wr_opcode { 62*29c8d9ebSAdit Ranadive PVRDMA_WR_RDMA_WRITE, 63*29c8d9ebSAdit Ranadive PVRDMA_WR_RDMA_WRITE_WITH_IMM, 64*29c8d9ebSAdit Ranadive PVRDMA_WR_SEND, 65*29c8d9ebSAdit Ranadive PVRDMA_WR_SEND_WITH_IMM, 66*29c8d9ebSAdit Ranadive PVRDMA_WR_RDMA_READ, 67*29c8d9ebSAdit Ranadive PVRDMA_WR_ATOMIC_CMP_AND_SWP, 68*29c8d9ebSAdit Ranadive PVRDMA_WR_ATOMIC_FETCH_AND_ADD, 69*29c8d9ebSAdit Ranadive PVRDMA_WR_LSO, 70*29c8d9ebSAdit Ranadive PVRDMA_WR_SEND_WITH_INV, 71*29c8d9ebSAdit Ranadive PVRDMA_WR_RDMA_READ_WITH_INV, 72*29c8d9ebSAdit Ranadive PVRDMA_WR_LOCAL_INV, 73*29c8d9ebSAdit Ranadive PVRDMA_WR_FAST_REG_MR, 74*29c8d9ebSAdit Ranadive PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP, 75*29c8d9ebSAdit Ranadive PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD, 76*29c8d9ebSAdit Ranadive PVRDMA_WR_BIND_MW, 77*29c8d9ebSAdit Ranadive PVRDMA_WR_REG_SIG_MR, 78*29c8d9ebSAdit Ranadive }; 79*29c8d9ebSAdit Ranadive 80*29c8d9ebSAdit Ranadive enum pvrdma_wc_status { 81*29c8d9ebSAdit Ranadive PVRDMA_WC_SUCCESS, 82*29c8d9ebSAdit Ranadive PVRDMA_WC_LOC_LEN_ERR, 83*29c8d9ebSAdit Ranadive PVRDMA_WC_LOC_QP_OP_ERR, 84*29c8d9ebSAdit Ranadive PVRDMA_WC_LOC_EEC_OP_ERR, 85*29c8d9ebSAdit Ranadive PVRDMA_WC_LOC_PROT_ERR, 86*29c8d9ebSAdit Ranadive PVRDMA_WC_WR_FLUSH_ERR, 87*29c8d9ebSAdit Ranadive PVRDMA_WC_MW_BIND_ERR, 88*29c8d9ebSAdit Ranadive PVRDMA_WC_BAD_RESP_ERR, 89*29c8d9ebSAdit Ranadive PVRDMA_WC_LOC_ACCESS_ERR, 90*29c8d9ebSAdit Ranadive PVRDMA_WC_REM_INV_REQ_ERR, 91*29c8d9ebSAdit Ranadive PVRDMA_WC_REM_ACCESS_ERR, 92*29c8d9ebSAdit Ranadive PVRDMA_WC_REM_OP_ERR, 93*29c8d9ebSAdit Ranadive PVRDMA_WC_RETRY_EXC_ERR, 94*29c8d9ebSAdit Ranadive PVRDMA_WC_RNR_RETRY_EXC_ERR, 95*29c8d9ebSAdit Ranadive PVRDMA_WC_LOC_RDD_VIOL_ERR, 96*29c8d9ebSAdit Ranadive PVRDMA_WC_REM_INV_RD_REQ_ERR, 97*29c8d9ebSAdit Ranadive PVRDMA_WC_REM_ABORT_ERR, 98*29c8d9ebSAdit Ranadive PVRDMA_WC_INV_EECN_ERR, 99*29c8d9ebSAdit Ranadive PVRDMA_WC_INV_EEC_STATE_ERR, 100*29c8d9ebSAdit Ranadive PVRDMA_WC_FATAL_ERR, 101*29c8d9ebSAdit Ranadive PVRDMA_WC_RESP_TIMEOUT_ERR, 102*29c8d9ebSAdit Ranadive PVRDMA_WC_GENERAL_ERR, 103*29c8d9ebSAdit Ranadive }; 104*29c8d9ebSAdit Ranadive 105*29c8d9ebSAdit Ranadive enum pvrdma_wc_opcode { 106*29c8d9ebSAdit Ranadive PVRDMA_WC_SEND, 107*29c8d9ebSAdit Ranadive PVRDMA_WC_RDMA_WRITE, 108*29c8d9ebSAdit Ranadive PVRDMA_WC_RDMA_READ, 109*29c8d9ebSAdit Ranadive PVRDMA_WC_COMP_SWAP, 110*29c8d9ebSAdit Ranadive PVRDMA_WC_FETCH_ADD, 111*29c8d9ebSAdit Ranadive PVRDMA_WC_BIND_MW, 112*29c8d9ebSAdit Ranadive PVRDMA_WC_LSO, 113*29c8d9ebSAdit Ranadive PVRDMA_WC_LOCAL_INV, 114*29c8d9ebSAdit Ranadive PVRDMA_WC_FAST_REG_MR, 115*29c8d9ebSAdit Ranadive PVRDMA_WC_MASKED_COMP_SWAP, 116*29c8d9ebSAdit Ranadive PVRDMA_WC_MASKED_FETCH_ADD, 117*29c8d9ebSAdit Ranadive PVRDMA_WC_RECV = 1 << 7, 118*29c8d9ebSAdit Ranadive PVRDMA_WC_RECV_RDMA_WITH_IMM, 119*29c8d9ebSAdit Ranadive }; 120*29c8d9ebSAdit Ranadive 121*29c8d9ebSAdit Ranadive enum pvrdma_wc_flags { 122*29c8d9ebSAdit Ranadive PVRDMA_WC_GRH = 1 << 0, 123*29c8d9ebSAdit Ranadive PVRDMA_WC_WITH_IMM = 1 << 1, 124*29c8d9ebSAdit Ranadive PVRDMA_WC_WITH_INVALIDATE = 1 << 2, 125*29c8d9ebSAdit Ranadive PVRDMA_WC_IP_CSUM_OK = 1 << 3, 126*29c8d9ebSAdit Ranadive PVRDMA_WC_WITH_SMAC = 1 << 4, 127*29c8d9ebSAdit Ranadive PVRDMA_WC_WITH_VLAN = 1 << 5, 128*29c8d9ebSAdit Ranadive PVRDMA_WC_FLAGS_MAX = PVRDMA_WC_WITH_VLAN, 129*29c8d9ebSAdit Ranadive }; 130*29c8d9ebSAdit Ranadive 131*29c8d9ebSAdit Ranadive struct pvrdma_alloc_ucontext_resp { 132*29c8d9ebSAdit Ranadive __u32 qp_tab_size; 133*29c8d9ebSAdit Ranadive __u32 reserved; 134*29c8d9ebSAdit Ranadive }; 135*29c8d9ebSAdit Ranadive 136*29c8d9ebSAdit Ranadive struct pvrdma_alloc_pd_resp { 137*29c8d9ebSAdit Ranadive __u32 pdn; 138*29c8d9ebSAdit Ranadive __u32 reserved; 139*29c8d9ebSAdit Ranadive }; 140*29c8d9ebSAdit Ranadive 141*29c8d9ebSAdit Ranadive struct pvrdma_create_cq { 142*29c8d9ebSAdit Ranadive __u64 buf_addr; 143*29c8d9ebSAdit Ranadive __u32 buf_size; 144*29c8d9ebSAdit Ranadive __u32 reserved; 145*29c8d9ebSAdit Ranadive }; 146*29c8d9ebSAdit Ranadive 147*29c8d9ebSAdit Ranadive struct pvrdma_create_cq_resp { 148*29c8d9ebSAdit Ranadive __u32 cqn; 149*29c8d9ebSAdit Ranadive __u32 reserved; 150*29c8d9ebSAdit Ranadive }; 151*29c8d9ebSAdit Ranadive 152*29c8d9ebSAdit Ranadive struct pvrdma_resize_cq { 153*29c8d9ebSAdit Ranadive __u64 buf_addr; 154*29c8d9ebSAdit Ranadive __u32 buf_size; 155*29c8d9ebSAdit Ranadive __u32 reserved; 156*29c8d9ebSAdit Ranadive }; 157*29c8d9ebSAdit Ranadive 158*29c8d9ebSAdit Ranadive struct pvrdma_create_srq { 159*29c8d9ebSAdit Ranadive __u64 buf_addr; 160*29c8d9ebSAdit Ranadive }; 161*29c8d9ebSAdit Ranadive 162*29c8d9ebSAdit Ranadive struct pvrdma_create_srq_resp { 163*29c8d9ebSAdit Ranadive __u32 srqn; 164*29c8d9ebSAdit Ranadive __u32 reserved; 165*29c8d9ebSAdit Ranadive }; 166*29c8d9ebSAdit Ranadive 167*29c8d9ebSAdit Ranadive struct pvrdma_create_qp { 168*29c8d9ebSAdit Ranadive __u64 rbuf_addr; 169*29c8d9ebSAdit Ranadive __u64 sbuf_addr; 170*29c8d9ebSAdit Ranadive __u32 rbuf_size; 171*29c8d9ebSAdit Ranadive __u32 sbuf_size; 172*29c8d9ebSAdit Ranadive __u64 qp_addr; 173*29c8d9ebSAdit Ranadive }; 174*29c8d9ebSAdit Ranadive 175*29c8d9ebSAdit Ranadive /* PVRDMA masked atomic compare and swap */ 176*29c8d9ebSAdit Ranadive struct pvrdma_ex_cmp_swap { 177*29c8d9ebSAdit Ranadive __u64 swap_val; 178*29c8d9ebSAdit Ranadive __u64 compare_val; 179*29c8d9ebSAdit Ranadive __u64 swap_mask; 180*29c8d9ebSAdit Ranadive __u64 compare_mask; 181*29c8d9ebSAdit Ranadive }; 182*29c8d9ebSAdit Ranadive 183*29c8d9ebSAdit Ranadive /* PVRDMA masked atomic fetch and add */ 184*29c8d9ebSAdit Ranadive struct pvrdma_ex_fetch_add { 185*29c8d9ebSAdit Ranadive __u64 add_val; 186*29c8d9ebSAdit Ranadive __u64 field_boundary; 187*29c8d9ebSAdit Ranadive }; 188*29c8d9ebSAdit Ranadive 189*29c8d9ebSAdit Ranadive /* PVRDMA address vector. */ 190*29c8d9ebSAdit Ranadive struct pvrdma_av { 191*29c8d9ebSAdit Ranadive __u32 port_pd; 192*29c8d9ebSAdit Ranadive __u32 sl_tclass_flowlabel; 193*29c8d9ebSAdit Ranadive __u8 dgid[16]; 194*29c8d9ebSAdit Ranadive __u8 src_path_bits; 195*29c8d9ebSAdit Ranadive __u8 gid_index; 196*29c8d9ebSAdit Ranadive __u8 stat_rate; 197*29c8d9ebSAdit Ranadive __u8 hop_limit; 198*29c8d9ebSAdit Ranadive __u8 dmac[6]; 199*29c8d9ebSAdit Ranadive __u8 reserved[6]; 200*29c8d9ebSAdit Ranadive }; 201*29c8d9ebSAdit Ranadive 202*29c8d9ebSAdit Ranadive /* PVRDMA scatter/gather entry */ 203*29c8d9ebSAdit Ranadive struct pvrdma_sge { 204*29c8d9ebSAdit Ranadive __u64 addr; 205*29c8d9ebSAdit Ranadive __u32 length; 206*29c8d9ebSAdit Ranadive __u32 lkey; 207*29c8d9ebSAdit Ranadive }; 208*29c8d9ebSAdit Ranadive 209*29c8d9ebSAdit Ranadive /* PVRDMA receive queue work request */ 210*29c8d9ebSAdit Ranadive struct pvrdma_rq_wqe_hdr { 211*29c8d9ebSAdit Ranadive __u64 wr_id; /* wr id */ 212*29c8d9ebSAdit Ranadive __u32 num_sge; /* size of s/g array */ 213*29c8d9ebSAdit Ranadive __u32 total_len; /* reserved */ 214*29c8d9ebSAdit Ranadive }; 215*29c8d9ebSAdit Ranadive /* Use pvrdma_sge (ib_sge) for receive queue s/g array elements. */ 216*29c8d9ebSAdit Ranadive 217*29c8d9ebSAdit Ranadive /* PVRDMA send queue work request */ 218*29c8d9ebSAdit Ranadive struct pvrdma_sq_wqe_hdr { 219*29c8d9ebSAdit Ranadive __u64 wr_id; /* wr id */ 220*29c8d9ebSAdit Ranadive __u32 num_sge; /* size of s/g array */ 221*29c8d9ebSAdit Ranadive __u32 total_len; /* reserved */ 222*29c8d9ebSAdit Ranadive __u32 opcode; /* operation type */ 223*29c8d9ebSAdit Ranadive __u32 send_flags; /* wr flags */ 224*29c8d9ebSAdit Ranadive union { 225*29c8d9ebSAdit Ranadive __u32 imm_data; 226*29c8d9ebSAdit Ranadive __u32 invalidate_rkey; 227*29c8d9ebSAdit Ranadive } ex; 228*29c8d9ebSAdit Ranadive __u32 reserved; 229*29c8d9ebSAdit Ranadive union { 230*29c8d9ebSAdit Ranadive struct { 231*29c8d9ebSAdit Ranadive __u64 remote_addr; 232*29c8d9ebSAdit Ranadive __u32 rkey; 233*29c8d9ebSAdit Ranadive __u8 reserved[4]; 234*29c8d9ebSAdit Ranadive } rdma; 235*29c8d9ebSAdit Ranadive struct { 236*29c8d9ebSAdit Ranadive __u64 remote_addr; 237*29c8d9ebSAdit Ranadive __u64 compare_add; 238*29c8d9ebSAdit Ranadive __u64 swap; 239*29c8d9ebSAdit Ranadive __u32 rkey; 240*29c8d9ebSAdit Ranadive __u32 reserved; 241*29c8d9ebSAdit Ranadive } atomic; 242*29c8d9ebSAdit Ranadive struct { 243*29c8d9ebSAdit Ranadive __u64 remote_addr; 244*29c8d9ebSAdit Ranadive __u32 log_arg_sz; 245*29c8d9ebSAdit Ranadive __u32 rkey; 246*29c8d9ebSAdit Ranadive union { 247*29c8d9ebSAdit Ranadive struct pvrdma_ex_cmp_swap cmp_swap; 248*29c8d9ebSAdit Ranadive struct pvrdma_ex_fetch_add fetch_add; 249*29c8d9ebSAdit Ranadive } wr_data; 250*29c8d9ebSAdit Ranadive } masked_atomics; 251*29c8d9ebSAdit Ranadive struct { 252*29c8d9ebSAdit Ranadive __u64 iova_start; 253*29c8d9ebSAdit Ranadive __u64 pl_pdir_dma; 254*29c8d9ebSAdit Ranadive __u32 page_shift; 255*29c8d9ebSAdit Ranadive __u32 page_list_len; 256*29c8d9ebSAdit Ranadive __u32 length; 257*29c8d9ebSAdit Ranadive __u32 access_flags; 258*29c8d9ebSAdit Ranadive __u32 rkey; 259*29c8d9ebSAdit Ranadive } fast_reg; 260*29c8d9ebSAdit Ranadive struct { 261*29c8d9ebSAdit Ranadive __u32 remote_qpn; 262*29c8d9ebSAdit Ranadive __u32 remote_qkey; 263*29c8d9ebSAdit Ranadive struct pvrdma_av av; 264*29c8d9ebSAdit Ranadive } ud; 265*29c8d9ebSAdit Ranadive } wr; 266*29c8d9ebSAdit Ranadive }; 267*29c8d9ebSAdit Ranadive /* Use pvrdma_sge (ib_sge) for send queue s/g array elements. */ 268*29c8d9ebSAdit Ranadive 269*29c8d9ebSAdit Ranadive /* Completion queue element. */ 270*29c8d9ebSAdit Ranadive struct pvrdma_cqe { 271*29c8d9ebSAdit Ranadive __u64 wr_id; 272*29c8d9ebSAdit Ranadive __u64 qp; 273*29c8d9ebSAdit Ranadive __u32 opcode; 274*29c8d9ebSAdit Ranadive __u32 status; 275*29c8d9ebSAdit Ranadive __u32 byte_len; 276*29c8d9ebSAdit Ranadive __u32 imm_data; 277*29c8d9ebSAdit Ranadive __u32 src_qp; 278*29c8d9ebSAdit Ranadive __u32 wc_flags; 279*29c8d9ebSAdit Ranadive __u32 vendor_err; 280*29c8d9ebSAdit Ranadive __u16 pkey_index; 281*29c8d9ebSAdit Ranadive __u16 slid; 282*29c8d9ebSAdit Ranadive __u8 sl; 283*29c8d9ebSAdit Ranadive __u8 dlid_path_bits; 284*29c8d9ebSAdit Ranadive __u8 port_num; 285*29c8d9ebSAdit Ranadive __u8 smac[6]; 286*29c8d9ebSAdit Ranadive __u8 reserved2[7]; /* Pad to next power of 2 (64). */ 287*29c8d9ebSAdit Ranadive }; 288*29c8d9ebSAdit Ranadive 289*29c8d9ebSAdit Ranadive #endif /* __VMW_PVRDMA_ABI_H__ */ 290