1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_ABI_USER_H 34 #define MLX5_ABI_USER_H 35 36 #include <linux/types.h> 37 38 enum { 39 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 40 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 41 }; 42 43 enum { 44 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 45 }; 46 47 enum { 48 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 49 }; 50 51 /* Increment this value if any changes that break userspace ABI 52 * compatibility are made. 53 */ 54 #define MLX5_IB_UVERBS_ABI_VERSION 1 55 56 /* Make sure that all structs defined in this file remain laid out so 57 * that they pack the same way on 32-bit and 64-bit architectures (to 58 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 59 * In particular do not use pointer types -- pass pointers in __u64 60 * instead. 61 */ 62 63 struct mlx5_ib_alloc_ucontext_req { 64 __u32 total_num_uuars; 65 __u32 num_low_latency_uuars; 66 }; 67 68 struct mlx5_ib_alloc_ucontext_req_v2 { 69 __u32 total_num_uuars; 70 __u32 num_low_latency_uuars; 71 __u32 flags; 72 __u32 comp_mask; 73 __u8 max_cqe_version; 74 __u8 reserved0; 75 __u16 reserved1; 76 __u32 reserved2; 77 }; 78 79 enum mlx5_ib_alloc_ucontext_resp_mask { 80 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 81 }; 82 83 enum mlx5_user_cmds_supp_uhw { 84 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 85 }; 86 87 struct mlx5_ib_alloc_ucontext_resp { 88 __u32 qp_tab_size; 89 __u32 bf_reg_size; 90 __u32 tot_uuars; 91 __u32 cache_line_size; 92 __u16 max_sq_desc_sz; 93 __u16 max_rq_desc_sz; 94 __u32 max_send_wqebb; 95 __u32 max_recv_wr; 96 __u32 max_srq_recv_wr; 97 __u16 num_ports; 98 __u16 reserved1; 99 __u32 comp_mask; 100 __u32 response_length; 101 __u8 cqe_version; 102 __u8 cmds_supp_uhw; 103 __u16 reserved2; 104 __u64 hca_core_clock_offset; 105 }; 106 107 struct mlx5_ib_alloc_pd_resp { 108 __u32 pdn; 109 }; 110 111 struct mlx5_ib_tso_caps { 112 __u32 max_tso; /* Maximum tso payload size in bytes */ 113 114 /* Corresponding bit will be set if qp type from 115 * 'enum ib_qp_type' is supported, e.g. 116 * supported_qpts |= 1 << IB_QPT_UD 117 */ 118 __u32 supported_qpts; 119 }; 120 121 struct mlx5_ib_rss_caps { 122 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 123 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 124 __u8 reserved[7]; 125 }; 126 127 struct mlx5_ib_query_device_resp { 128 __u32 comp_mask; 129 __u32 response_length; 130 struct mlx5_ib_tso_caps tso_caps; 131 struct mlx5_ib_rss_caps rss_caps; 132 }; 133 134 struct mlx5_ib_create_cq { 135 __u64 buf_addr; 136 __u64 db_addr; 137 __u32 cqe_size; 138 __u32 reserved; /* explicit padding (optional on i386) */ 139 }; 140 141 struct mlx5_ib_create_cq_resp { 142 __u32 cqn; 143 __u32 reserved; 144 }; 145 146 struct mlx5_ib_resize_cq { 147 __u64 buf_addr; 148 __u16 cqe_size; 149 __u16 reserved0; 150 __u32 reserved1; 151 }; 152 153 struct mlx5_ib_create_srq { 154 __u64 buf_addr; 155 __u64 db_addr; 156 __u32 flags; 157 __u32 reserved0; /* explicit padding (optional on i386) */ 158 __u32 uidx; 159 __u32 reserved1; 160 }; 161 162 struct mlx5_ib_create_srq_resp { 163 __u32 srqn; 164 __u32 reserved; 165 }; 166 167 struct mlx5_ib_create_qp { 168 __u64 buf_addr; 169 __u64 db_addr; 170 __u32 sq_wqe_count; 171 __u32 rq_wqe_count; 172 __u32 rq_wqe_shift; 173 __u32 flags; 174 __u32 uidx; 175 __u32 reserved0; 176 __u64 sq_buf_addr; 177 }; 178 179 /* RX Hash function flags */ 180 enum mlx5_rx_hash_function_flags { 181 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 182 }; 183 184 /* 185 * RX Hash flags, these flags allows to set which incoming packet's field should 186 * participates in RX Hash. Each flag represent certain packet's field, 187 * when the flag is set the field that is represented by the flag will 188 * participate in RX Hash calculation. 189 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 190 * and *TCP and *UDP flags can't be enabled together on the same QP. 191 */ 192 enum mlx5_rx_hash_fields { 193 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 194 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 195 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 196 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 197 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 198 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 199 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 200 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7 201 }; 202 203 struct mlx5_ib_create_qp_rss { 204 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 205 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 206 __u8 rx_key_len; /* valid only for Toeplitz */ 207 __u8 reserved[6]; 208 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 209 __u32 comp_mask; 210 __u32 reserved1; 211 }; 212 213 struct mlx5_ib_create_qp_resp { 214 __u32 uuar_index; 215 }; 216 217 struct mlx5_ib_alloc_mw { 218 __u32 comp_mask; 219 __u8 num_klms; 220 __u8 reserved1; 221 __u16 reserved2; 222 }; 223 224 struct mlx5_ib_create_wq { 225 __u64 buf_addr; 226 __u64 db_addr; 227 __u32 rq_wqe_count; 228 __u32 rq_wqe_shift; 229 __u32 user_index; 230 __u32 flags; 231 __u32 comp_mask; 232 __u32 reserved; 233 }; 234 235 struct mlx5_ib_create_wq_resp { 236 __u32 response_length; 237 __u32 reserved; 238 }; 239 240 struct mlx5_ib_create_rwq_ind_tbl_resp { 241 __u32 response_length; 242 __u32 reserved; 243 }; 244 245 struct mlx5_ib_modify_wq { 246 __u32 comp_mask; 247 __u32 reserved; 248 }; 249 #endif /* MLX5_ABI_USER_H */ 250