1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H 36 37 #include <linux/types.h> 38 #include <linux/if_ether.h> /* For ETH_ALEN. */ 39 40 enum { 41 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 42 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 43 }; 44 45 enum { 46 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 47 }; 48 49 enum { 50 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 51 }; 52 53 /* Increment this value if any changes that break userspace ABI 54 * compatibility are made. 55 */ 56 #define MLX5_IB_UVERBS_ABI_VERSION 1 57 58 /* Make sure that all structs defined in this file remain laid out so 59 * that they pack the same way on 32-bit and 64-bit architectures (to 60 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 61 * In particular do not use pointer types -- pass pointers in __u64 62 * instead. 63 */ 64 65 struct mlx5_ib_alloc_ucontext_req { 66 __u32 total_num_bfregs; 67 __u32 num_low_latency_bfregs; 68 }; 69 70 enum mlx5_lib_caps { 71 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 72 }; 73 74 struct mlx5_ib_alloc_ucontext_req_v2 { 75 __u32 total_num_bfregs; 76 __u32 num_low_latency_bfregs; 77 __u32 flags; 78 __u32 comp_mask; 79 __u8 max_cqe_version; 80 __u8 reserved0; 81 __u16 reserved1; 82 __u32 reserved2; 83 __u64 lib_caps; 84 }; 85 86 enum mlx5_ib_alloc_ucontext_resp_mask { 87 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 88 }; 89 90 enum mlx5_user_cmds_supp_uhw { 91 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 92 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 93 }; 94 95 /* The eth_min_inline response value is set to off-by-one vs the FW 96 * returned value to allow user-space to deal with older kernels. 97 */ 98 enum mlx5_user_inline_mode { 99 MLX5_USER_INLINE_MODE_NA, 100 MLX5_USER_INLINE_MODE_NONE, 101 MLX5_USER_INLINE_MODE_L2, 102 MLX5_USER_INLINE_MODE_IP, 103 MLX5_USER_INLINE_MODE_TCP_UDP, 104 }; 105 106 struct mlx5_ib_alloc_ucontext_resp { 107 __u32 qp_tab_size; 108 __u32 bf_reg_size; 109 __u32 tot_bfregs; 110 __u32 cache_line_size; 111 __u16 max_sq_desc_sz; 112 __u16 max_rq_desc_sz; 113 __u32 max_send_wqebb; 114 __u32 max_recv_wr; 115 __u32 max_srq_recv_wr; 116 __u16 num_ports; 117 __u16 reserved1; 118 __u32 comp_mask; 119 __u32 response_length; 120 __u8 cqe_version; 121 __u8 cmds_supp_uhw; 122 __u8 eth_min_inline; 123 __u8 reserved2; 124 __u64 hca_core_clock_offset; 125 __u32 log_uar_size; 126 __u32 num_uars_per_page; 127 }; 128 129 struct mlx5_ib_alloc_pd_resp { 130 __u32 pdn; 131 }; 132 133 struct mlx5_ib_tso_caps { 134 __u32 max_tso; /* Maximum tso payload size in bytes */ 135 136 /* Corresponding bit will be set if qp type from 137 * 'enum ib_qp_type' is supported, e.g. 138 * supported_qpts |= 1 << IB_QPT_UD 139 */ 140 __u32 supported_qpts; 141 }; 142 143 struct mlx5_ib_rss_caps { 144 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 145 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 146 __u8 reserved[7]; 147 }; 148 149 enum mlx5_ib_cqe_comp_res_format { 150 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 151 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 152 MLX5_IB_CQE_RES_RESERVED = 1 << 2, 153 }; 154 155 struct mlx5_ib_cqe_comp_caps { 156 __u32 max_num; 157 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 158 }; 159 160 struct mlx5_packet_pacing_caps { 161 __u32 qp_rate_limit_min; 162 __u32 qp_rate_limit_max; /* In kpbs */ 163 164 /* Corresponding bit will be set if qp type from 165 * 'enum ib_qp_type' is supported, e.g. 166 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 167 */ 168 __u32 supported_qpts; 169 __u32 reserved; 170 }; 171 172 enum mlx5_ib_mpw_caps { 173 MPW_RESERVED = 1 << 0, 174 MLX5_IB_ALLOW_MPW = 1 << 1, 175 MLX5_IB_SUPPORT_EMPW = 1 << 2, 176 }; 177 178 enum mlx5_ib_sw_parsing_offloads { 179 MLX5_IB_SW_PARSING = 1 << 0, 180 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 181 MLX5_IB_SW_PARSING_LSO = 1 << 2, 182 }; 183 184 struct mlx5_ib_sw_parsing_caps { 185 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */ 186 187 /* Corresponding bit will be set if qp type from 188 * 'enum ib_qp_type' is supported, e.g. 189 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 190 */ 191 __u32 supported_qpts; 192 }; 193 194 struct mlx5_ib_query_device_resp { 195 __u32 comp_mask; 196 __u32 response_length; 197 struct mlx5_ib_tso_caps tso_caps; 198 struct mlx5_ib_rss_caps rss_caps; 199 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 200 struct mlx5_packet_pacing_caps packet_pacing_caps; 201 __u32 mlx5_ib_support_multi_pkt_send_wqes; 202 __u32 reserved; 203 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 204 }; 205 206 struct mlx5_ib_create_cq { 207 __u64 buf_addr; 208 __u64 db_addr; 209 __u32 cqe_size; 210 __u8 cqe_comp_en; 211 __u8 cqe_comp_res_format; 212 __u16 reserved; /* explicit padding (optional on i386) */ 213 }; 214 215 struct mlx5_ib_create_cq_resp { 216 __u32 cqn; 217 __u32 reserved; 218 }; 219 220 struct mlx5_ib_resize_cq { 221 __u64 buf_addr; 222 __u16 cqe_size; 223 __u16 reserved0; 224 __u32 reserved1; 225 }; 226 227 struct mlx5_ib_create_srq { 228 __u64 buf_addr; 229 __u64 db_addr; 230 __u32 flags; 231 __u32 reserved0; /* explicit padding (optional on i386) */ 232 __u32 uidx; 233 __u32 reserved1; 234 }; 235 236 struct mlx5_ib_create_srq_resp { 237 __u32 srqn; 238 __u32 reserved; 239 }; 240 241 struct mlx5_ib_create_qp { 242 __u64 buf_addr; 243 __u64 db_addr; 244 __u32 sq_wqe_count; 245 __u32 rq_wqe_count; 246 __u32 rq_wqe_shift; 247 __u32 flags; 248 __u32 uidx; 249 __u32 reserved0; 250 __u64 sq_buf_addr; 251 }; 252 253 /* RX Hash function flags */ 254 enum mlx5_rx_hash_function_flags { 255 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 256 }; 257 258 /* 259 * RX Hash flags, these flags allows to set which incoming packet's field should 260 * participates in RX Hash. Each flag represent certain packet's field, 261 * when the flag is set the field that is represented by the flag will 262 * participate in RX Hash calculation. 263 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 264 * and *TCP and *UDP flags can't be enabled together on the same QP. 265 */ 266 enum mlx5_rx_hash_fields { 267 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 268 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 269 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 270 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 271 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 272 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 273 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 274 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7 275 }; 276 277 struct mlx5_ib_create_qp_rss { 278 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 279 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 280 __u8 rx_key_len; /* valid only for Toeplitz */ 281 __u8 reserved[6]; 282 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 283 __u32 comp_mask; 284 __u32 reserved1; 285 }; 286 287 struct mlx5_ib_create_qp_resp { 288 __u32 bfreg_index; 289 }; 290 291 struct mlx5_ib_alloc_mw { 292 __u32 comp_mask; 293 __u8 num_klms; 294 __u8 reserved1; 295 __u16 reserved2; 296 }; 297 298 struct mlx5_ib_create_wq { 299 __u64 buf_addr; 300 __u64 db_addr; 301 __u32 rq_wqe_count; 302 __u32 rq_wqe_shift; 303 __u32 user_index; 304 __u32 flags; 305 __u32 comp_mask; 306 __u32 reserved; 307 }; 308 309 struct mlx5_ib_create_ah_resp { 310 __u32 response_length; 311 __u8 dmac[ETH_ALEN]; 312 __u8 reserved[6]; 313 }; 314 315 struct mlx5_ib_create_wq_resp { 316 __u32 response_length; 317 __u32 reserved; 318 }; 319 320 struct mlx5_ib_create_rwq_ind_tbl_resp { 321 __u32 response_length; 322 __u32 reserved; 323 }; 324 325 struct mlx5_ib_modify_wq { 326 __u32 comp_mask; 327 __u32 reserved; 328 }; 329 #endif /* MLX5_ABI_USER_H */ 330