1 /* 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2015 Intel Corporation. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * BSD LICENSE 20 * 21 * Copyright(c) 2015 Intel Corporation. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 27 * - Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * - Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in 31 * the documentation and/or other materials provided with the 32 * distribution. 33 * - Neither the name of Intel Corporation nor the names of its 34 * contributors may be used to endorse or promote products derived 35 * from this software without specific prior written permission. 36 * 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 * 49 */ 50 51 /* 52 * This file contains defines, structures, etc. that are used 53 * to communicate between kernel and user code. 54 */ 55 56 #ifndef _LINUX__HFI1_USER_H 57 #define _LINUX__HFI1_USER_H 58 59 #include <linux/types.h> 60 61 /* 62 * This version number is given to the driver by the user code during 63 * initialization in the spu_userversion field of hfi1_user_info, so 64 * the driver can check for compatibility with user code. 65 * 66 * The major version changes when data structures change in an incompatible 67 * way. The driver must be the same for initialization to succeed. 68 */ 69 #define HFI1_USER_SWMAJOR 5 70 71 /* 72 * Minor version differences are always compatible 73 * a within a major version, however if user software is larger 74 * than driver software, some new features and/or structure fields 75 * may not be implemented; the user code must deal with this if it 76 * cares, or it must abort after initialization reports the difference. 77 */ 78 #define HFI1_USER_SWMINOR 1 79 80 /* 81 * Set of HW and driver capability/feature bits. 82 * These bit values are used to configure enabled/disabled HW and 83 * driver features. The same set of bits are communicated to user 84 * space. 85 */ 86 #define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */ 87 #define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */ 88 #define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */ 89 #define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */ 90 #define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */ 91 /* 1UL << 5 unused */ 92 #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */ 93 #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/ 94 #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */ 95 #define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) /* Don't drop on EGR buffs full */ 96 #define HFI1_CAP_TID_UNMAP (1UL << 10) /* Disable Expected TID caching */ 97 #define HFI1_CAP_PRINT_UNIMPL (1UL << 11) /* Show for unimplemented feats */ 98 #define HFI1_CAP_ALLOW_PERM_JKEY (1UL << 12) /* Allow use of permissive JKEY */ 99 #define HFI1_CAP_NO_INTEGRITY (1UL << 13) /* Enable ctxt integrity checks */ 100 #define HFI1_CAP_PKEY_CHECK (1UL << 14) /* Enable ctxt PKey checking */ 101 #define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */ 102 /* 1UL << 16 unused */ 103 #define HFI1_CAP_SDMA_HEAD_CHECK (1UL << 17) /* SDMA head checking */ 104 #define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */ 105 106 #define HFI1_RCVHDR_ENTSIZE_2 (1UL << 0) 107 #define HFI1_RCVHDR_ENTSIZE_16 (1UL << 1) 108 #define HFI1_RCVDHR_ENTSIZE_32 (1UL << 2) 109 110 /* User commands. */ 111 #define HFI1_CMD_ASSIGN_CTXT 1 /* allocate HFI and context */ 112 #define HFI1_CMD_CTXT_INFO 2 /* find out what resources we got */ 113 #define HFI1_CMD_USER_INFO 3 /* set up userspace */ 114 #define HFI1_CMD_TID_UPDATE 4 /* update expected TID entries */ 115 #define HFI1_CMD_TID_FREE 5 /* free expected TID entries */ 116 #define HFI1_CMD_CREDIT_UPD 6 /* force an update of PIO credit */ 117 #define HFI1_CMD_SDMA_STATUS_UPD 7 /* force update of SDMA status ring */ 118 119 #define HFI1_CMD_RECV_CTRL 8 /* control receipt of packets */ 120 #define HFI1_CMD_POLL_TYPE 9 /* set the kind of polling we want */ 121 #define HFI1_CMD_ACK_EVENT 10 /* ack & clear user status bits */ 122 #define HFI1_CMD_SET_PKEY 11 /* set context's pkey */ 123 #define HFI1_CMD_CTXT_RESET 12 /* reset context's HW send context */ 124 #define HFI1_CMD_TID_INVAL_READ 13 /* read TID cache invalidations */ 125 126 #define _HFI1_EVENT_FROZEN_BIT 0 127 #define _HFI1_EVENT_LINKDOWN_BIT 1 128 #define _HFI1_EVENT_LID_CHANGE_BIT 2 129 #define _HFI1_EVENT_LMC_CHANGE_BIT 3 130 #define _HFI1_EVENT_SL2VL_CHANGE_BIT 4 131 #define _HFI1_EVENT_TID_MMU_NOTIFY_BIT 5 132 #define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_TID_MMU_NOTIFY_BIT 133 134 #define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT) 135 #define HFI1_EVENT_LINKDOWN (1UL << _HFI1_EVENT_LINKDOWN_BIT) 136 #define HFI1_EVENT_LID_CHANGE (1UL << _HFI1_EVENT_LID_CHANGE_BIT) 137 #define HFI1_EVENT_LMC_CHANGE (1UL << _HFI1_EVENT_LMC_CHANGE_BIT) 138 #define HFI1_EVENT_SL2VL_CHANGE (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT) 139 #define HFI1_EVENT_TID_MMU_NOTIFY (1UL << _HFI1_EVENT_TID_MMU_NOTIFY_BIT) 140 141 /* 142 * These are the status bits readable (in ASCII form, 64bit value) 143 * from the "status" sysfs file. For binary compatibility, values 144 * must remain as is; removed states can be reused for different 145 * purposes. 146 */ 147 #define HFI1_STATUS_INITTED 0x1 /* basic initialization done */ 148 /* Chip has been found and initialized */ 149 #define HFI1_STATUS_CHIP_PRESENT 0x20 150 /* IB link is at ACTIVE, usable for data traffic */ 151 #define HFI1_STATUS_IB_READY 0x40 152 /* link is configured, LID, MTU, etc. have been set */ 153 #define HFI1_STATUS_IB_CONF 0x80 154 /* A Fatal hardware error has occurred. */ 155 #define HFI1_STATUS_HWERROR 0x200 156 157 /* 158 * Number of supported shared contexts. 159 * This is the maximum number of software contexts that can share 160 * a hardware send/receive context. 161 */ 162 #define HFI1_MAX_SHARED_CTXTS 8 163 164 /* 165 * Poll types 166 */ 167 #define HFI1_POLL_TYPE_ANYRCV 0x0 168 #define HFI1_POLL_TYPE_URGENT 0x1 169 170 /* 171 * This structure is passed to the driver to tell it where 172 * user code buffers are, sizes, etc. The offsets and sizes of the 173 * fields must remain unchanged, for binary compatibility. It can 174 * be extended, if userversion is changed so user code can tell, if needed 175 */ 176 struct hfi1_user_info { 177 /* 178 * version of user software, to detect compatibility issues. 179 * Should be set to HFI1_USER_SWVERSION. 180 */ 181 __u32 userversion; 182 __u32 pad; 183 /* 184 * If two or more processes wish to share a context, each process 185 * must set the subcontext_cnt and subcontext_id to the same 186 * values. The only restriction on the subcontext_id is that 187 * it be unique for a given node. 188 */ 189 __u16 subctxt_cnt; 190 __u16 subctxt_id; 191 /* 128bit UUID passed in by PSM. */ 192 __u8 uuid[16]; 193 }; 194 195 struct hfi1_ctxt_info { 196 __u64 runtime_flags; /* chip/drv runtime flags (HFI1_CAP_*) */ 197 __u32 rcvegr_size; /* size of each eager buffer */ 198 __u16 num_active; /* number of active units */ 199 __u16 unit; /* unit (chip) assigned to caller */ 200 __u16 ctxt; /* ctxt on unit assigned to caller */ 201 __u16 subctxt; /* subctxt on unit assigned to caller */ 202 __u16 rcvtids; /* number of Rcv TIDs for this context */ 203 __u16 credits; /* number of PIO credits for this context */ 204 __u16 numa_node; /* NUMA node of the assigned device */ 205 __u16 rec_cpu; /* cpu # for affinity (0xffff if none) */ 206 __u16 send_ctxt; /* send context in use by this user context */ 207 __u16 egrtids; /* number of RcvArray entries for Eager Rcvs */ 208 __u16 rcvhdrq_cnt; /* number of RcvHdrQ entries */ 209 __u16 rcvhdrq_entsize; /* size (in bytes) for each RcvHdrQ entry */ 210 __u16 sdma_ring_size; /* number of entries in SDMA request ring */ 211 }; 212 213 struct hfi1_tid_info { 214 /* virtual address of first page in transfer */ 215 __u64 vaddr; 216 /* pointer to tid array. this array is big enough */ 217 __u64 tidlist; 218 /* number of tids programmed by this request */ 219 __u32 tidcnt; 220 /* length of transfer buffer programmed by this request */ 221 __u32 length; 222 }; 223 224 struct hfi1_cmd { 225 __u32 type; /* command type */ 226 __u32 len; /* length of struct pointed to by add */ 227 __u64 addr; /* pointer to user structure */ 228 }; 229 230 enum hfi1_sdma_comp_state { 231 FREE = 0, 232 QUEUED, 233 COMPLETE, 234 ERROR 235 }; 236 237 /* 238 * SDMA completion ring entry 239 */ 240 struct hfi1_sdma_comp_entry { 241 __u32 status; 242 __u32 errcode; 243 }; 244 245 /* 246 * Device status and notifications from driver to user-space. 247 */ 248 struct hfi1_status { 249 __u64 dev; /* device/hw status bits */ 250 __u64 port; /* port state and status bits */ 251 char freezemsg[0]; 252 }; 253 254 /* 255 * This structure is returned by the driver immediately after 256 * open to get implementation-specific info, and info specific to this 257 * instance. 258 * 259 * This struct must have explicit pad fields where type sizes 260 * may result in different alignments between 32 and 64 bit 261 * programs, since the 64 bit * bit kernel requires the user code 262 * to have matching offsets 263 */ 264 struct hfi1_base_info { 265 /* version of hardware, for feature checking. */ 266 __u32 hw_version; 267 /* version of software, for feature checking. */ 268 __u32 sw_version; 269 /* Job key */ 270 __u16 jkey; 271 __u16 padding1; 272 /* 273 * The special QP (queue pair) value that identifies PSM 274 * protocol packet from standard IB packets. 275 */ 276 __u32 bthqp; 277 /* PIO credit return address, */ 278 __u64 sc_credits_addr; 279 /* 280 * Base address of write-only pio buffers for this process. 281 * Each buffer has sendpio_credits*64 bytes. 282 */ 283 __u64 pio_bufbase_sop; 284 /* 285 * Base address of write-only pio buffers for this process. 286 * Each buffer has sendpio_credits*64 bytes. 287 */ 288 __u64 pio_bufbase; 289 /* address where receive buffer queue is mapped into */ 290 __u64 rcvhdr_bufbase; 291 /* base address of Eager receive buffers. */ 292 __u64 rcvegr_bufbase; 293 /* base address of SDMA completion ring */ 294 __u64 sdma_comp_bufbase; 295 /* 296 * User register base for init code, not to be used directly by 297 * protocol or applications. Always maps real chip register space. 298 * the register addresses are: 299 * ur_rcvhdrhead, ur_rcvhdrtail, ur_rcvegrhead, ur_rcvegrtail, 300 * ur_rcvtidflow 301 */ 302 __u64 user_regbase; 303 /* notification events */ 304 __u64 events_bufbase; 305 /* status page */ 306 __u64 status_bufbase; 307 /* rcvhdrtail update */ 308 __u64 rcvhdrtail_base; 309 /* 310 * shared memory pages for subctxts if ctxt is shared; these cover 311 * all the processes in the group sharing a single context. 312 * all have enough space for the num_subcontexts value on this job. 313 */ 314 __u64 subctxt_uregbase; 315 __u64 subctxt_rcvegrbuf; 316 __u64 subctxt_rcvhdrbuf; 317 }; 318 319 enum sdma_req_opcode { 320 EXPECTED = 0, 321 EAGER 322 }; 323 324 #define HFI1_SDMA_REQ_VERSION_MASK 0xF 325 #define HFI1_SDMA_REQ_VERSION_SHIFT 0x0 326 #define HFI1_SDMA_REQ_OPCODE_MASK 0xF 327 #define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4 328 #define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF 329 #define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8 330 331 struct sdma_req_info { 332 /* 333 * bits 0-3 - version (currently unused) 334 * bits 4-7 - opcode (enum sdma_req_opcode) 335 * bits 8-15 - io vector count 336 */ 337 __u16 ctrl; 338 /* 339 * Number of fragments contained in this request. 340 * User-space has already computed how many 341 * fragment-sized packet the user buffer will be 342 * split into. 343 */ 344 __u16 npkts; 345 /* 346 * Size of each fragment the user buffer will be 347 * split into. 348 */ 349 __u16 fragsize; 350 /* 351 * Index of the slot in the SDMA completion ring 352 * this request should be using. User-space is 353 * in charge of managing its own ring. 354 */ 355 __u16 comp_idx; 356 } __packed; 357 358 /* 359 * SW KDETH header. 360 * swdata is SW defined portion. 361 */ 362 struct hfi1_kdeth_header { 363 __le32 ver_tid_offset; 364 __le16 jkey; 365 __le16 hcrc; 366 __le32 swdata[7]; 367 } __packed; 368 369 /* 370 * Structure describing the headers that User space uses. The 371 * structure above is a subset of this one. 372 */ 373 struct hfi1_pkt_header { 374 __le16 pbc[4]; 375 __be16 lrh[4]; 376 __be32 bth[3]; 377 struct hfi1_kdeth_header kdeth; 378 } __packed; 379 380 381 /* 382 * The list of usermode accessible registers. 383 */ 384 enum hfi1_ureg { 385 /* (RO) DMA RcvHdr to be used next. */ 386 ur_rcvhdrtail = 0, 387 /* (RW) RcvHdr entry to be processed next by host. */ 388 ur_rcvhdrhead = 1, 389 /* (RO) Index of next Eager index to use. */ 390 ur_rcvegrindextail = 2, 391 /* (RW) Eager TID to be processed next */ 392 ur_rcvegrindexhead = 3, 393 /* (RO) Receive Eager Offset Tail */ 394 ur_rcvegroffsettail = 4, 395 /* For internal use only; max register number. */ 396 ur_maxreg, 397 /* (RW) Receive TID flow table */ 398 ur_rcvtidflowtable = 256 399 }; 400 401 #endif /* _LINIUX__HFI1_USER_H */ 402