1 /* 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2015 Intel Corporation. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * BSD LICENSE 20 * 21 * Copyright(c) 2015 Intel Corporation. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 27 * - Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * - Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in 31 * the documentation and/or other materials provided with the 32 * distribution. 33 * - Neither the name of Intel Corporation nor the names of its 34 * contributors may be used to endorse or promote products derived 35 * from this software without specific prior written permission. 36 * 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 * 49 */ 50 51 /* 52 * This file contains defines, structures, etc. that are used 53 * to communicate between kernel and user code. 54 */ 55 56 #ifndef _LINUX__HFI1_USER_H 57 #define _LINUX__HFI1_USER_H 58 59 #include <linux/types.h> 60 #include <rdma/rdma_user_ioctl.h> 61 #include <rdma/hfi/hfi1_ioctl.h> 62 63 /* 64 * This version number is given to the driver by the user code during 65 * initialization in the spu_userversion field of hfi1_user_info, so 66 * the driver can check for compatibility with user code. 67 * 68 * The major version changes when data structures change in an incompatible 69 * way. The driver must be the same for initialization to succeed. 70 */ 71 #define HFI1_USER_SWMAJOR 6 72 73 /* 74 * Minor version differences are always compatible 75 * a within a major version, however if user software is larger 76 * than driver software, some new features and/or structure fields 77 * may not be implemented; the user code must deal with this if it 78 * cares, or it must abort after initialization reports the difference. 79 */ 80 #define HFI1_USER_SWMINOR 3 81 82 /* 83 * We will encode the major/minor inside a single 32bit version number. 84 */ 85 #define HFI1_SWMAJOR_SHIFT 16 86 87 /* 88 * Set of HW and driver capability/feature bits. 89 * These bit values are used to configure enabled/disabled HW and 90 * driver features. The same set of bits are communicated to user 91 * space. 92 */ 93 #define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */ 94 #define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */ 95 #define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */ 96 #define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */ 97 #define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */ 98 /* 1UL << 5 unused */ 99 #define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */ 100 #define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/ 101 #define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */ 102 #define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) /* Don't drop on EGR buffs full */ 103 #define HFI1_CAP_TID_UNMAP (1UL << 10) /* Disable Expected TID caching */ 104 #define HFI1_CAP_PRINT_UNIMPL (1UL << 11) /* Show for unimplemented feats */ 105 #define HFI1_CAP_ALLOW_PERM_JKEY (1UL << 12) /* Allow use of permissive JKEY */ 106 #define HFI1_CAP_NO_INTEGRITY (1UL << 13) /* Enable ctxt integrity checks */ 107 #define HFI1_CAP_PKEY_CHECK (1UL << 14) /* Enable ctxt PKey checking */ 108 #define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */ 109 /* 1UL << 16 unused */ 110 #define HFI1_CAP_SDMA_HEAD_CHECK (1UL << 17) /* SDMA head checking */ 111 #define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */ 112 113 #define HFI1_RCVHDR_ENTSIZE_2 (1UL << 0) 114 #define HFI1_RCVHDR_ENTSIZE_16 (1UL << 1) 115 #define HFI1_RCVDHR_ENTSIZE_32 (1UL << 2) 116 117 /* User commands. */ 118 #define HFI1_CMD_ASSIGN_CTXT 1 /* allocate HFI and context */ 119 #define HFI1_CMD_CTXT_INFO 2 /* find out what resources we got */ 120 #define HFI1_CMD_USER_INFO 3 /* set up userspace */ 121 #define HFI1_CMD_TID_UPDATE 4 /* update expected TID entries */ 122 #define HFI1_CMD_TID_FREE 5 /* free expected TID entries */ 123 #define HFI1_CMD_CREDIT_UPD 6 /* force an update of PIO credit */ 124 125 #define HFI1_CMD_RECV_CTRL 8 /* control receipt of packets */ 126 #define HFI1_CMD_POLL_TYPE 9 /* set the kind of polling we want */ 127 #define HFI1_CMD_ACK_EVENT 10 /* ack & clear user status bits */ 128 #define HFI1_CMD_SET_PKEY 11 /* set context's pkey */ 129 #define HFI1_CMD_CTXT_RESET 12 /* reset context's HW send context */ 130 #define HFI1_CMD_TID_INVAL_READ 13 /* read TID cache invalidations */ 131 #define HFI1_CMD_GET_VERS 14 /* get the version of the user cdev */ 132 133 /* 134 * User IOCTLs can not go above 128 if they do then see common.h and change the 135 * base for the snoop ioctl 136 */ 137 138 /* 139 * Make the ioctls occupy the last 0xf0-0xff portion of the IB range 140 */ 141 #define __NUM(cmd) (HFI1_CMD_##cmd + 0xe0) 142 143 struct hfi1_cmd; 144 #define HFI1_IOCTL_ASSIGN_CTXT \ 145 _IOWR(IB_IOCTL_MAGIC, __NUM(ASSIGN_CTXT), struct hfi1_user_info) 146 #define HFI1_IOCTL_CTXT_INFO \ 147 _IOW(IB_IOCTL_MAGIC, __NUM(CTXT_INFO), struct hfi1_ctxt_info) 148 #define HFI1_IOCTL_USER_INFO \ 149 _IOW(IB_IOCTL_MAGIC, __NUM(USER_INFO), struct hfi1_base_info) 150 #define HFI1_IOCTL_TID_UPDATE \ 151 _IOWR(IB_IOCTL_MAGIC, __NUM(TID_UPDATE), struct hfi1_tid_info) 152 #define HFI1_IOCTL_TID_FREE \ 153 _IOWR(IB_IOCTL_MAGIC, __NUM(TID_FREE), struct hfi1_tid_info) 154 #define HFI1_IOCTL_CREDIT_UPD \ 155 _IO(IB_IOCTL_MAGIC, __NUM(CREDIT_UPD)) 156 #define HFI1_IOCTL_RECV_CTRL \ 157 _IOW(IB_IOCTL_MAGIC, __NUM(RECV_CTRL), int) 158 #define HFI1_IOCTL_POLL_TYPE \ 159 _IOW(IB_IOCTL_MAGIC, __NUM(POLL_TYPE), int) 160 #define HFI1_IOCTL_ACK_EVENT \ 161 _IOW(IB_IOCTL_MAGIC, __NUM(ACK_EVENT), unsigned long) 162 #define HFI1_IOCTL_SET_PKEY \ 163 _IOW(IB_IOCTL_MAGIC, __NUM(SET_PKEY), __u16) 164 #define HFI1_IOCTL_CTXT_RESET \ 165 _IO(IB_IOCTL_MAGIC, __NUM(CTXT_RESET)) 166 #define HFI1_IOCTL_TID_INVAL_READ \ 167 _IOWR(IB_IOCTL_MAGIC, __NUM(TID_INVAL_READ), struct hfi1_tid_info) 168 #define HFI1_IOCTL_GET_VERS \ 169 _IOR(IB_IOCTL_MAGIC, __NUM(GET_VERS), int) 170 171 #define _HFI1_EVENT_FROZEN_BIT 0 172 #define _HFI1_EVENT_LINKDOWN_BIT 1 173 #define _HFI1_EVENT_LID_CHANGE_BIT 2 174 #define _HFI1_EVENT_LMC_CHANGE_BIT 3 175 #define _HFI1_EVENT_SL2VL_CHANGE_BIT 4 176 #define _HFI1_EVENT_TID_MMU_NOTIFY_BIT 5 177 #define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_TID_MMU_NOTIFY_BIT 178 179 #define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT) 180 #define HFI1_EVENT_LINKDOWN (1UL << _HFI1_EVENT_LINKDOWN_BIT) 181 #define HFI1_EVENT_LID_CHANGE (1UL << _HFI1_EVENT_LID_CHANGE_BIT) 182 #define HFI1_EVENT_LMC_CHANGE (1UL << _HFI1_EVENT_LMC_CHANGE_BIT) 183 #define HFI1_EVENT_SL2VL_CHANGE (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT) 184 #define HFI1_EVENT_TID_MMU_NOTIFY (1UL << _HFI1_EVENT_TID_MMU_NOTIFY_BIT) 185 186 /* 187 * These are the status bits readable (in ASCII form, 64bit value) 188 * from the "status" sysfs file. For binary compatibility, values 189 * must remain as is; removed states can be reused for different 190 * purposes. 191 */ 192 #define HFI1_STATUS_INITTED 0x1 /* basic initialization done */ 193 /* Chip has been found and initialized */ 194 #define HFI1_STATUS_CHIP_PRESENT 0x20 195 /* IB link is at ACTIVE, usable for data traffic */ 196 #define HFI1_STATUS_IB_READY 0x40 197 /* link is configured, LID, MTU, etc. have been set */ 198 #define HFI1_STATUS_IB_CONF 0x80 199 /* A Fatal hardware error has occurred. */ 200 #define HFI1_STATUS_HWERROR 0x200 201 202 /* 203 * Number of supported shared contexts. 204 * This is the maximum number of software contexts that can share 205 * a hardware send/receive context. 206 */ 207 #define HFI1_MAX_SHARED_CTXTS 8 208 209 /* 210 * Poll types 211 */ 212 #define HFI1_POLL_TYPE_ANYRCV 0x0 213 #define HFI1_POLL_TYPE_URGENT 0x1 214 215 enum hfi1_sdma_comp_state { 216 FREE = 0, 217 QUEUED, 218 COMPLETE, 219 ERROR 220 }; 221 222 /* 223 * SDMA completion ring entry 224 */ 225 struct hfi1_sdma_comp_entry { 226 __u32 status; 227 __u32 errcode; 228 }; 229 230 /* 231 * Device status and notifications from driver to user-space. 232 */ 233 struct hfi1_status { 234 __u64 dev; /* device/hw status bits */ 235 __u64 port; /* port state and status bits */ 236 char freezemsg[0]; 237 }; 238 239 enum sdma_req_opcode { 240 EXPECTED = 0, 241 EAGER 242 }; 243 244 #define HFI1_SDMA_REQ_VERSION_MASK 0xF 245 #define HFI1_SDMA_REQ_VERSION_SHIFT 0x0 246 #define HFI1_SDMA_REQ_OPCODE_MASK 0xF 247 #define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4 248 #define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF 249 #define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8 250 251 struct sdma_req_info { 252 /* 253 * bits 0-3 - version (currently unused) 254 * bits 4-7 - opcode (enum sdma_req_opcode) 255 * bits 8-15 - io vector count 256 */ 257 __u16 ctrl; 258 /* 259 * Number of fragments contained in this request. 260 * User-space has already computed how many 261 * fragment-sized packet the user buffer will be 262 * split into. 263 */ 264 __u16 npkts; 265 /* 266 * Size of each fragment the user buffer will be 267 * split into. 268 */ 269 __u16 fragsize; 270 /* 271 * Index of the slot in the SDMA completion ring 272 * this request should be using. User-space is 273 * in charge of managing its own ring. 274 */ 275 __u16 comp_idx; 276 } __packed; 277 278 /* 279 * SW KDETH header. 280 * swdata is SW defined portion. 281 */ 282 struct hfi1_kdeth_header { 283 __le32 ver_tid_offset; 284 __le16 jkey; 285 __le16 hcrc; 286 __le32 swdata[7]; 287 } __packed; 288 289 /* 290 * Structure describing the headers that User space uses. The 291 * structure above is a subset of this one. 292 */ 293 struct hfi1_pkt_header { 294 __le16 pbc[4]; 295 __be16 lrh[4]; 296 __be32 bth[3]; 297 struct hfi1_kdeth_header kdeth; 298 } __packed; 299 300 301 /* 302 * The list of usermode accessible registers. 303 */ 304 enum hfi1_ureg { 305 /* (RO) DMA RcvHdr to be used next. */ 306 ur_rcvhdrtail = 0, 307 /* (RW) RcvHdr entry to be processed next by host. */ 308 ur_rcvhdrhead = 1, 309 /* (RO) Index of next Eager index to use. */ 310 ur_rcvegrindextail = 2, 311 /* (RW) Eager TID to be processed next */ 312 ur_rcvegrindexhead = 3, 313 /* (RO) Receive Eager Offset Tail */ 314 ur_rcvegroffsettail = 4, 315 /* For internal use only; max register number. */ 316 ur_maxreg, 317 /* (RW) Receive TID flow table */ 318 ur_rcvtidflowtable = 256 319 }; 320 321 #endif /* _LINIUX__HFI1_USER_H */ 322