1607ca46eSDavid Howells /* 2607ca46eSDavid Howells * Virtio PCI driver 3607ca46eSDavid Howells * 4607ca46eSDavid Howells * This module allows virtio devices to be used over a virtual PCI device. 5607ca46eSDavid Howells * This can be used with QEMU based VMMs like KVM or Xen. 6607ca46eSDavid Howells * 7607ca46eSDavid Howells * Copyright IBM Corp. 2007 8607ca46eSDavid Howells * 9607ca46eSDavid Howells * Authors: 10607ca46eSDavid Howells * Anthony Liguori <aliguori@us.ibm.com> 11607ca46eSDavid Howells * 12607ca46eSDavid Howells * This header is BSD licensed so anyone can use the definitions to implement 13607ca46eSDavid Howells * compatible drivers/servers. 14607ca46eSDavid Howells * 15607ca46eSDavid Howells * Redistribution and use in source and binary forms, with or without 16607ca46eSDavid Howells * modification, are permitted provided that the following conditions 17607ca46eSDavid Howells * are met: 18607ca46eSDavid Howells * 1. Redistributions of source code must retain the above copyright 19607ca46eSDavid Howells * notice, this list of conditions and the following disclaimer. 20607ca46eSDavid Howells * 2. Redistributions in binary form must reproduce the above copyright 21607ca46eSDavid Howells * notice, this list of conditions and the following disclaimer in the 22607ca46eSDavid Howells * documentation and/or other materials provided with the distribution. 23607ca46eSDavid Howells * 3. Neither the name of IBM nor the names of its contributors 24607ca46eSDavid Howells * may be used to endorse or promote products derived from this software 25607ca46eSDavid Howells * without specific prior written permission. 26607ca46eSDavid Howells * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND 27607ca46eSDavid Howells * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28607ca46eSDavid Howells * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29607ca46eSDavid Howells * ARE DISCLAIMED. IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE 30607ca46eSDavid Howells * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31607ca46eSDavid Howells * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32607ca46eSDavid Howells * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33607ca46eSDavid Howells * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34607ca46eSDavid Howells * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35607ca46eSDavid Howells * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36607ca46eSDavid Howells * SUCH DAMAGE. 37607ca46eSDavid Howells */ 38607ca46eSDavid Howells 39607ca46eSDavid Howells #ifndef _LINUX_VIRTIO_PCI_H 40607ca46eSDavid Howells #define _LINUX_VIRTIO_PCI_H 41607ca46eSDavid Howells 427f870c81SMichael S. Tsirkin #include <linux/types.h> 43607ca46eSDavid Howells 440dce3771SMichael S. Tsirkin #ifndef VIRTIO_PCI_NO_LEGACY 450dce3771SMichael S. Tsirkin 46607ca46eSDavid Howells /* A 32-bit r/o bitmask of the features supported by the host */ 47607ca46eSDavid Howells #define VIRTIO_PCI_HOST_FEATURES 0 48607ca46eSDavid Howells 49607ca46eSDavid Howells /* A 32-bit r/w bitmask of features activated by the guest */ 50607ca46eSDavid Howells #define VIRTIO_PCI_GUEST_FEATURES 4 51607ca46eSDavid Howells 52607ca46eSDavid Howells /* A 32-bit r/w PFN for the currently selected queue */ 53607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_PFN 8 54607ca46eSDavid Howells 55607ca46eSDavid Howells /* A 16-bit r/o queue size for the currently selected queue */ 56607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_NUM 12 57607ca46eSDavid Howells 58607ca46eSDavid Howells /* A 16-bit r/w queue selector */ 59607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_SEL 14 60607ca46eSDavid Howells 61607ca46eSDavid Howells /* A 16-bit r/w queue notifier */ 62607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_NOTIFY 16 63607ca46eSDavid Howells 64607ca46eSDavid Howells /* An 8-bit device status register. */ 65607ca46eSDavid Howells #define VIRTIO_PCI_STATUS 18 66607ca46eSDavid Howells 67607ca46eSDavid Howells /* An 8-bit r/o interrupt status register. Reading the value will return the 68607ca46eSDavid Howells * current contents of the ISR and will also clear it. This is effectively 69607ca46eSDavid Howells * a read-and-acknowledge. */ 70607ca46eSDavid Howells #define VIRTIO_PCI_ISR 19 71607ca46eSDavid Howells 72607ca46eSDavid Howells /* MSI-X registers: only enabled if MSI-X is enabled. */ 73607ca46eSDavid Howells /* A 16-bit vector for configuration changes. */ 74607ca46eSDavid Howells #define VIRTIO_MSI_CONFIG_VECTOR 20 75607ca46eSDavid Howells /* A 16-bit vector for selected queue notifications. */ 76607ca46eSDavid Howells #define VIRTIO_MSI_QUEUE_VECTOR 22 77607ca46eSDavid Howells 78607ca46eSDavid Howells /* The remaining space is defined by each driver as the per-driver 79607ca46eSDavid Howells * configuration space */ 808b21ab14SMichael S. Tsirkin #define VIRTIO_PCI_CONFIG_OFF(msix_enabled) ((msix_enabled) ? 24 : 20) 818b21ab14SMichael S. Tsirkin /* Deprecated: please use VIRTIO_PCI_CONFIG_OFF instead */ 828b21ab14SMichael S. Tsirkin #define VIRTIO_PCI_CONFIG(dev) VIRTIO_PCI_CONFIG_OFF((dev)->msix_enabled) 83607ca46eSDavid Howells 84607ca46eSDavid Howells /* Virtio ABI version, this must match exactly */ 85607ca46eSDavid Howells #define VIRTIO_PCI_ABI_VERSION 0 86607ca46eSDavid Howells 87607ca46eSDavid Howells /* How many bits to shift physical queue address written to QUEUE_PFN. 88607ca46eSDavid Howells * 12 is historical, and due to x86 page size. */ 89607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12 90607ca46eSDavid Howells 91607ca46eSDavid Howells /* The alignment to use between consumer and producer parts of vring. 92607ca46eSDavid Howells * x86 pagesize again. */ 93607ca46eSDavid Howells #define VIRTIO_PCI_VRING_ALIGN 4096 940dce3771SMichael S. Tsirkin 950dce3771SMichael S. Tsirkin #endif /* VIRTIO_PCI_NO_LEGACY */ 960dce3771SMichael S. Tsirkin 970dce3771SMichael S. Tsirkin /* The bit of the ISR which indicates a device configuration change. */ 980dce3771SMichael S. Tsirkin #define VIRTIO_PCI_ISR_CONFIG 0x2 990dce3771SMichael S. Tsirkin /* Vector value used to disable MSI for queue */ 1000dce3771SMichael S. Tsirkin #define VIRTIO_MSI_NO_VECTOR 0xffff 1010dce3771SMichael S. Tsirkin 10271d70c26SRusty Russell #ifndef VIRTIO_PCI_NO_MODERN 10371d70c26SRusty Russell 10471d70c26SRusty Russell /* IDs for different capabilities. Must all exist. */ 10571d70c26SRusty Russell 10671d70c26SRusty Russell /* Common configuration */ 10771d70c26SRusty Russell #define VIRTIO_PCI_CAP_COMMON_CFG 1 10871d70c26SRusty Russell /* Notifications */ 10971d70c26SRusty Russell #define VIRTIO_PCI_CAP_NOTIFY_CFG 2 11071d70c26SRusty Russell /* ISR access */ 11171d70c26SRusty Russell #define VIRTIO_PCI_CAP_ISR_CFG 3 112*e6a02746SRusty Russell /* Device specific configuration */ 11371d70c26SRusty Russell #define VIRTIO_PCI_CAP_DEVICE_CFG 4 114*e6a02746SRusty Russell /* PCI configuration access */ 115*e6a02746SRusty Russell #define VIRTIO_PCI_CAP_PCI_CFG 5 11671d70c26SRusty Russell 11771d70c26SRusty Russell /* This is the PCI capability header: */ 11871d70c26SRusty Russell struct virtio_pci_cap { 11971d70c26SRusty Russell __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ 12071d70c26SRusty Russell __u8 cap_next; /* Generic PCI field: next ptr. */ 12171d70c26SRusty Russell __u8 cap_len; /* Generic PCI field: capability length */ 1221fcf0512SMichael S. Tsirkin __u8 cfg_type; /* Identifies the structure. */ 1231fcf0512SMichael S. Tsirkin __u8 bar; /* Where to find it. */ 1241fcf0512SMichael S. Tsirkin __u8 padding[3]; /* Pad to full dword. */ 12571d70c26SRusty Russell __le32 offset; /* Offset within bar. */ 1261fcf0512SMichael S. Tsirkin __le32 length; /* Length of the structure, in bytes. */ 12771d70c26SRusty Russell }; 12871d70c26SRusty Russell 12971d70c26SRusty Russell struct virtio_pci_notify_cap { 13071d70c26SRusty Russell struct virtio_pci_cap cap; 13171d70c26SRusty Russell __le32 notify_off_multiplier; /* Multiplier for queue_notify_off. */ 13271d70c26SRusty Russell }; 13371d70c26SRusty Russell 13471d70c26SRusty Russell /* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */ 13571d70c26SRusty Russell struct virtio_pci_common_cfg { 13671d70c26SRusty Russell /* About the whole device. */ 13771d70c26SRusty Russell __le32 device_feature_select; /* read-write */ 13871d70c26SRusty Russell __le32 device_feature; /* read-only */ 13971d70c26SRusty Russell __le32 guest_feature_select; /* read-write */ 14071d70c26SRusty Russell __le32 guest_feature; /* read-write */ 14171d70c26SRusty Russell __le16 msix_config; /* read-write */ 14271d70c26SRusty Russell __le16 num_queues; /* read-only */ 14371d70c26SRusty Russell __u8 device_status; /* read-write */ 14471d70c26SRusty Russell __u8 config_generation; /* read-only */ 14571d70c26SRusty Russell 14671d70c26SRusty Russell /* About a specific virtqueue. */ 14771d70c26SRusty Russell __le16 queue_select; /* read-write */ 14871d70c26SRusty Russell __le16 queue_size; /* read-write, power of 2. */ 14971d70c26SRusty Russell __le16 queue_msix_vector; /* read-write */ 15071d70c26SRusty Russell __le16 queue_enable; /* read-write */ 15171d70c26SRusty Russell __le16 queue_notify_off; /* read-only */ 15271d70c26SRusty Russell __le32 queue_desc_lo; /* read-write */ 15371d70c26SRusty Russell __le32 queue_desc_hi; /* read-write */ 15471d70c26SRusty Russell __le32 queue_avail_lo; /* read-write */ 15571d70c26SRusty Russell __le32 queue_avail_hi; /* read-write */ 15671d70c26SRusty Russell __le32 queue_used_lo; /* read-write */ 15771d70c26SRusty Russell __le32 queue_used_hi; /* read-write */ 15871d70c26SRusty Russell }; 15971d70c26SRusty Russell 16089461c4aSRusty Russell /* Macro versions of offsets for the Old Timers! */ 16189461c4aSRusty Russell #define VIRTIO_PCI_CAP_VNDR 0 16289461c4aSRusty Russell #define VIRTIO_PCI_CAP_NEXT 1 16389461c4aSRusty Russell #define VIRTIO_PCI_CAP_LEN 2 16489461c4aSRusty Russell #define VIRTIO_PCI_CAP_CFG_TYPE 3 16589461c4aSRusty Russell #define VIRTIO_PCI_CAP_BAR 4 16689461c4aSRusty Russell #define VIRTIO_PCI_CAP_OFFSET 8 16789461c4aSRusty Russell #define VIRTIO_PCI_CAP_LENGTH 12 16889461c4aSRusty Russell 16989461c4aSRusty Russell #define VIRTIO_PCI_NOTIFY_CAP_MULT 16 17089461c4aSRusty Russell 17189461c4aSRusty Russell #define VIRTIO_PCI_COMMON_DFSELECT 0 17289461c4aSRusty Russell #define VIRTIO_PCI_COMMON_DF 4 17389461c4aSRusty Russell #define VIRTIO_PCI_COMMON_GFSELECT 8 17489461c4aSRusty Russell #define VIRTIO_PCI_COMMON_GF 12 17589461c4aSRusty Russell #define VIRTIO_PCI_COMMON_MSIX 16 17689461c4aSRusty Russell #define VIRTIO_PCI_COMMON_NUMQ 18 17789461c4aSRusty Russell #define VIRTIO_PCI_COMMON_STATUS 20 17889461c4aSRusty Russell #define VIRTIO_PCI_COMMON_CFGGENERATION 21 17989461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_SELECT 22 18089461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_SIZE 24 18189461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_MSIX 26 18289461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_ENABLE 28 18389461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_NOFF 30 18489461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_DESCLO 32 18589461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_DESCHI 36 18689461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_AVAILLO 40 18789461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_AVAILHI 44 18889461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_USEDLO 48 18989461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_USEDHI 52 19089461c4aSRusty Russell 19171d70c26SRusty Russell #endif /* VIRTIO_PCI_NO_MODERN */ 19271d70c26SRusty Russell 193607ca46eSDavid Howells #endif 194