1607ca46eSDavid Howells /* 2607ca46eSDavid Howells * Virtio PCI driver 3607ca46eSDavid Howells * 4607ca46eSDavid Howells * This module allows virtio devices to be used over a virtual PCI device. 5607ca46eSDavid Howells * This can be used with QEMU based VMMs like KVM or Xen. 6607ca46eSDavid Howells * 7607ca46eSDavid Howells * Copyright IBM Corp. 2007 8607ca46eSDavid Howells * 9607ca46eSDavid Howells * Authors: 10607ca46eSDavid Howells * Anthony Liguori <aliguori@us.ibm.com> 11607ca46eSDavid Howells * 12607ca46eSDavid Howells * This header is BSD licensed so anyone can use the definitions to implement 13607ca46eSDavid Howells * compatible drivers/servers. 14607ca46eSDavid Howells * 15607ca46eSDavid Howells * Redistribution and use in source and binary forms, with or without 16607ca46eSDavid Howells * modification, are permitted provided that the following conditions 17607ca46eSDavid Howells * are met: 18607ca46eSDavid Howells * 1. Redistributions of source code must retain the above copyright 19607ca46eSDavid Howells * notice, this list of conditions and the following disclaimer. 20607ca46eSDavid Howells * 2. Redistributions in binary form must reproduce the above copyright 21607ca46eSDavid Howells * notice, this list of conditions and the following disclaimer in the 22607ca46eSDavid Howells * documentation and/or other materials provided with the distribution. 23607ca46eSDavid Howells * 3. Neither the name of IBM nor the names of its contributors 24607ca46eSDavid Howells * may be used to endorse or promote products derived from this software 25607ca46eSDavid Howells * without specific prior written permission. 26607ca46eSDavid Howells * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND 27607ca46eSDavid Howells * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28607ca46eSDavid Howells * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29607ca46eSDavid Howells * ARE DISCLAIMED. IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE 30607ca46eSDavid Howells * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31607ca46eSDavid Howells * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32607ca46eSDavid Howells * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33607ca46eSDavid Howells * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34607ca46eSDavid Howells * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35607ca46eSDavid Howells * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36607ca46eSDavid Howells * SUCH DAMAGE. 37607ca46eSDavid Howells */ 38607ca46eSDavid Howells 39607ca46eSDavid Howells #ifndef _LINUX_VIRTIO_PCI_H 40607ca46eSDavid Howells #define _LINUX_VIRTIO_PCI_H 41607ca46eSDavid Howells 427f870c81SMichael S. Tsirkin #include <linux/types.h> 43607ca46eSDavid Howells 440dce3771SMichael S. Tsirkin #ifndef VIRTIO_PCI_NO_LEGACY 450dce3771SMichael S. Tsirkin 46607ca46eSDavid Howells /* A 32-bit r/o bitmask of the features supported by the host */ 47607ca46eSDavid Howells #define VIRTIO_PCI_HOST_FEATURES 0 48607ca46eSDavid Howells 49607ca46eSDavid Howells /* A 32-bit r/w bitmask of features activated by the guest */ 50607ca46eSDavid Howells #define VIRTIO_PCI_GUEST_FEATURES 4 51607ca46eSDavid Howells 52607ca46eSDavid Howells /* A 32-bit r/w PFN for the currently selected queue */ 53607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_PFN 8 54607ca46eSDavid Howells 55607ca46eSDavid Howells /* A 16-bit r/o queue size for the currently selected queue */ 56607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_NUM 12 57607ca46eSDavid Howells 58607ca46eSDavid Howells /* A 16-bit r/w queue selector */ 59607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_SEL 14 60607ca46eSDavid Howells 61607ca46eSDavid Howells /* A 16-bit r/w queue notifier */ 62607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_NOTIFY 16 63607ca46eSDavid Howells 64607ca46eSDavid Howells /* An 8-bit device status register. */ 65607ca46eSDavid Howells #define VIRTIO_PCI_STATUS 18 66607ca46eSDavid Howells 67607ca46eSDavid Howells /* An 8-bit r/o interrupt status register. Reading the value will return the 68607ca46eSDavid Howells * current contents of the ISR and will also clear it. This is effectively 69607ca46eSDavid Howells * a read-and-acknowledge. */ 70607ca46eSDavid Howells #define VIRTIO_PCI_ISR 19 71607ca46eSDavid Howells 72607ca46eSDavid Howells /* MSI-X registers: only enabled if MSI-X is enabled. */ 73607ca46eSDavid Howells /* A 16-bit vector for configuration changes. */ 74607ca46eSDavid Howells #define VIRTIO_MSI_CONFIG_VECTOR 20 75607ca46eSDavid Howells /* A 16-bit vector for selected queue notifications. */ 76607ca46eSDavid Howells #define VIRTIO_MSI_QUEUE_VECTOR 22 77607ca46eSDavid Howells 78607ca46eSDavid Howells /* The remaining space is defined by each driver as the per-driver 79607ca46eSDavid Howells * configuration space */ 808b21ab14SMichael S. Tsirkin #define VIRTIO_PCI_CONFIG_OFF(msix_enabled) ((msix_enabled) ? 24 : 20) 818b21ab14SMichael S. Tsirkin /* Deprecated: please use VIRTIO_PCI_CONFIG_OFF instead */ 822008c154SMichael S. Tsirkin #define VIRTIO_PCI_CONFIG(dev) VIRTIO_PCI_CONFIG_OFF((dev)->msix_enabled) 83607ca46eSDavid Howells 84607ca46eSDavid Howells /* Virtio ABI version, this must match exactly */ 85607ca46eSDavid Howells #define VIRTIO_PCI_ABI_VERSION 0 86607ca46eSDavid Howells 87607ca46eSDavid Howells /* How many bits to shift physical queue address written to QUEUE_PFN. 88607ca46eSDavid Howells * 12 is historical, and due to x86 page size. */ 89607ca46eSDavid Howells #define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12 90607ca46eSDavid Howells 91607ca46eSDavid Howells /* The alignment to use between consumer and producer parts of vring. 92607ca46eSDavid Howells * x86 pagesize again. */ 93607ca46eSDavid Howells #define VIRTIO_PCI_VRING_ALIGN 4096 940dce3771SMichael S. Tsirkin 950dce3771SMichael S. Tsirkin #endif /* VIRTIO_PCI_NO_LEGACY */ 960dce3771SMichael S. Tsirkin 970dce3771SMichael S. Tsirkin /* The bit of the ISR which indicates a device configuration change. */ 980dce3771SMichael S. Tsirkin #define VIRTIO_PCI_ISR_CONFIG 0x2 990dce3771SMichael S. Tsirkin /* Vector value used to disable MSI for queue */ 1000dce3771SMichael S. Tsirkin #define VIRTIO_MSI_NO_VECTOR 0xffff 1010dce3771SMichael S. Tsirkin 10271d70c26SRusty Russell #ifndef VIRTIO_PCI_NO_MODERN 10371d70c26SRusty Russell 10471d70c26SRusty Russell /* IDs for different capabilities. Must all exist. */ 10571d70c26SRusty Russell 10671d70c26SRusty Russell /* Common configuration */ 10771d70c26SRusty Russell #define VIRTIO_PCI_CAP_COMMON_CFG 1 10871d70c26SRusty Russell /* Notifications */ 10971d70c26SRusty Russell #define VIRTIO_PCI_CAP_NOTIFY_CFG 2 11071d70c26SRusty Russell /* ISR access */ 11171d70c26SRusty Russell #define VIRTIO_PCI_CAP_ISR_CFG 3 112e6a02746SRusty Russell /* Device specific configuration */ 11371d70c26SRusty Russell #define VIRTIO_PCI_CAP_DEVICE_CFG 4 114e6a02746SRusty Russell /* PCI configuration access */ 115e6a02746SRusty Russell #define VIRTIO_PCI_CAP_PCI_CFG 5 1160dd4ff93SSebastien Boeuf /* Additional shared memory capability */ 1170dd4ff93SSebastien Boeuf #define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8 11871d70c26SRusty Russell 11971d70c26SRusty Russell /* This is the PCI capability header: */ 12071d70c26SRusty Russell struct virtio_pci_cap { 12171d70c26SRusty Russell __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ 12271d70c26SRusty Russell __u8 cap_next; /* Generic PCI field: next ptr. */ 12371d70c26SRusty Russell __u8 cap_len; /* Generic PCI field: capability length */ 1241fcf0512SMichael S. Tsirkin __u8 cfg_type; /* Identifies the structure. */ 1251fcf0512SMichael S. Tsirkin __u8 bar; /* Where to find it. */ 1260dd4ff93SSebastien Boeuf __u8 id; /* Multiple capabilities of the same type */ 1270dd4ff93SSebastien Boeuf __u8 padding[2]; /* Pad to full dword. */ 12871d70c26SRusty Russell __le32 offset; /* Offset within bar. */ 1291fcf0512SMichael S. Tsirkin __le32 length; /* Length of the structure, in bytes. */ 13071d70c26SRusty Russell }; 13171d70c26SRusty Russell 1320dd4ff93SSebastien Boeuf struct virtio_pci_cap64 { 1330dd4ff93SSebastien Boeuf struct virtio_pci_cap cap; 1340dd4ff93SSebastien Boeuf __le32 offset_hi; /* Most sig 32 bits of offset */ 1350dd4ff93SSebastien Boeuf __le32 length_hi; /* Most sig 32 bits of length */ 1360dd4ff93SSebastien Boeuf }; 1370dd4ff93SSebastien Boeuf 13871d70c26SRusty Russell struct virtio_pci_notify_cap { 13971d70c26SRusty Russell struct virtio_pci_cap cap; 14071d70c26SRusty Russell __le32 notify_off_multiplier; /* Multiplier for queue_notify_off. */ 14171d70c26SRusty Russell }; 14271d70c26SRusty Russell 14371d70c26SRusty Russell /* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */ 14471d70c26SRusty Russell struct virtio_pci_common_cfg { 14571d70c26SRusty Russell /* About the whole device. */ 14671d70c26SRusty Russell __le32 device_feature_select; /* read-write */ 14771d70c26SRusty Russell __le32 device_feature; /* read-only */ 14871d70c26SRusty Russell __le32 guest_feature_select; /* read-write */ 14971d70c26SRusty Russell __le32 guest_feature; /* read-write */ 15071d70c26SRusty Russell __le16 msix_config; /* read-write */ 15171d70c26SRusty Russell __le16 num_queues; /* read-only */ 15271d70c26SRusty Russell __u8 device_status; /* read-write */ 15371d70c26SRusty Russell __u8 config_generation; /* read-only */ 15471d70c26SRusty Russell 15571d70c26SRusty Russell /* About a specific virtqueue. */ 15671d70c26SRusty Russell __le16 queue_select; /* read-write */ 15771d70c26SRusty Russell __le16 queue_size; /* read-write, power of 2. */ 15871d70c26SRusty Russell __le16 queue_msix_vector; /* read-write */ 15971d70c26SRusty Russell __le16 queue_enable; /* read-write */ 16071d70c26SRusty Russell __le16 queue_notify_off; /* read-only */ 16171d70c26SRusty Russell __le32 queue_desc_lo; /* read-write */ 16271d70c26SRusty Russell __le32 queue_desc_hi; /* read-write */ 16371d70c26SRusty Russell __le32 queue_avail_lo; /* read-write */ 16471d70c26SRusty Russell __le32 queue_avail_hi; /* read-write */ 16571d70c26SRusty Russell __le32 queue_used_lo; /* read-write */ 16671d70c26SRusty Russell __le32 queue_used_hi; /* read-write */ 16771d70c26SRusty Russell }; 16871d70c26SRusty Russell 16935038957SMichael S. Tsirkin /* 17035038957SMichael S. Tsirkin * Warning: do not use sizeof on this: use offsetofend for 17135038957SMichael S. Tsirkin * specific fields you need. 17235038957SMichael S. Tsirkin */ 17335038957SMichael S. Tsirkin struct virtio_pci_modern_common_cfg { 17435038957SMichael S. Tsirkin struct virtio_pci_common_cfg cfg; 17535038957SMichael S. Tsirkin 17635038957SMichael S. Tsirkin __le16 queue_notify_data; /* read-write */ 17735038957SMichael S. Tsirkin __le16 queue_reset; /* read-write */ 178fd27ef6bSFeng Liu 179fd27ef6bSFeng Liu __le16 admin_queue_index; /* read-only */ 180fd27ef6bSFeng Liu __le16 admin_queue_num; /* read-only */ 18135038957SMichael S. Tsirkin }; 18235038957SMichael S. Tsirkin 1833121bb02SMichael S. Tsirkin /* Fields in VIRTIO_PCI_CAP_PCI_CFG: */ 1843121bb02SMichael S. Tsirkin struct virtio_pci_cfg_cap { 1853121bb02SMichael S. Tsirkin struct virtio_pci_cap cap; 1863121bb02SMichael S. Tsirkin __u8 pci_cfg_data[4]; /* Data for BAR access. */ 1873121bb02SMichael S. Tsirkin }; 1883121bb02SMichael S. Tsirkin 18989461c4aSRusty Russell /* Macro versions of offsets for the Old Timers! */ 19089461c4aSRusty Russell #define VIRTIO_PCI_CAP_VNDR 0 19189461c4aSRusty Russell #define VIRTIO_PCI_CAP_NEXT 1 19289461c4aSRusty Russell #define VIRTIO_PCI_CAP_LEN 2 19389461c4aSRusty Russell #define VIRTIO_PCI_CAP_CFG_TYPE 3 19489461c4aSRusty Russell #define VIRTIO_PCI_CAP_BAR 4 19589461c4aSRusty Russell #define VIRTIO_PCI_CAP_OFFSET 8 19689461c4aSRusty Russell #define VIRTIO_PCI_CAP_LENGTH 12 19789461c4aSRusty Russell 19889461c4aSRusty Russell #define VIRTIO_PCI_NOTIFY_CAP_MULT 16 19989461c4aSRusty Russell 20089461c4aSRusty Russell #define VIRTIO_PCI_COMMON_DFSELECT 0 20189461c4aSRusty Russell #define VIRTIO_PCI_COMMON_DF 4 20289461c4aSRusty Russell #define VIRTIO_PCI_COMMON_GFSELECT 8 20389461c4aSRusty Russell #define VIRTIO_PCI_COMMON_GF 12 20489461c4aSRusty Russell #define VIRTIO_PCI_COMMON_MSIX 16 20589461c4aSRusty Russell #define VIRTIO_PCI_COMMON_NUMQ 18 20689461c4aSRusty Russell #define VIRTIO_PCI_COMMON_STATUS 20 20789461c4aSRusty Russell #define VIRTIO_PCI_COMMON_CFGGENERATION 21 20889461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_SELECT 22 20989461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_SIZE 24 21089461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_MSIX 26 21189461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_ENABLE 28 21289461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_NOFF 30 21389461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_DESCLO 32 21489461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_DESCHI 36 21589461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_AVAILLO 40 21689461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_AVAILHI 44 21789461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_USEDLO 48 21889461c4aSRusty Russell #define VIRTIO_PCI_COMMON_Q_USEDHI 52 219ea024594SXuan Zhuo #define VIRTIO_PCI_COMMON_Q_NDATA 56 2200cdd450eSXuan Zhuo #define VIRTIO_PCI_COMMON_Q_RESET 58 221fd27ef6bSFeng Liu #define VIRTIO_PCI_COMMON_ADM_Q_IDX 60 222fd27ef6bSFeng Liu #define VIRTIO_PCI_COMMON_ADM_Q_NUM 62 22389461c4aSRusty Russell 22471d70c26SRusty Russell #endif /* VIRTIO_PCI_NO_MODERN */ 22571d70c26SRusty Russell 22692792ac7SFeng Liu /* Admin command status. */ 22792792ac7SFeng Liu #define VIRTIO_ADMIN_STATUS_OK 0 22892792ac7SFeng Liu 229388431b9SFeng Liu /* Admin command opcode. */ 230388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LIST_QUERY 0x0 231388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LIST_USE 0x1 232388431b9SFeng Liu 233388431b9SFeng Liu /* Admin command group type. */ 234388431b9SFeng Liu #define VIRTIO_ADMIN_GROUP_TYPE_SRIOV 0x1 235388431b9SFeng Liu 236388431b9SFeng Liu /* Transitional device admin command. */ 237388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_WRITE 0x2 238388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_READ 0x3 239388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_WRITE 0x4 240388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ 0x5 241388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO 0x6 242388431b9SFeng Liu 243*ec6ecb84SSuzuki K Poulose struct virtio_admin_cmd_hdr { 24492792ac7SFeng Liu __le16 opcode; 24592792ac7SFeng Liu /* 24692792ac7SFeng Liu * 1 - SR-IOV 24792792ac7SFeng Liu * 2-65535 - reserved 24892792ac7SFeng Liu */ 24992792ac7SFeng Liu __le16 group_type; 25092792ac7SFeng Liu /* Unused, reserved for future extensions. */ 25192792ac7SFeng Liu __u8 reserved1[12]; 25292792ac7SFeng Liu __le64 group_member_id; 25392792ac7SFeng Liu }; 25492792ac7SFeng Liu 255*ec6ecb84SSuzuki K Poulose struct virtio_admin_cmd_status { 25692792ac7SFeng Liu __le16 status; 25792792ac7SFeng Liu __le16 status_qualifier; 25892792ac7SFeng Liu /* Unused, reserved for future extensions. */ 25992792ac7SFeng Liu __u8 reserved2[4]; 26092792ac7SFeng Liu }; 26192792ac7SFeng Liu 262*ec6ecb84SSuzuki K Poulose struct virtio_admin_cmd_legacy_wr_data { 263388431b9SFeng Liu __u8 offset; /* Starting offset of the register(s) to write. */ 264388431b9SFeng Liu __u8 reserved[7]; 265388431b9SFeng Liu __u8 registers[]; 266388431b9SFeng Liu }; 267388431b9SFeng Liu 268*ec6ecb84SSuzuki K Poulose struct virtio_admin_cmd_legacy_rd_data { 269388431b9SFeng Liu __u8 offset; /* Starting offset of the register(s) to read. */ 270388431b9SFeng Liu }; 271388431b9SFeng Liu 272388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_END 0 273388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_DEV 0x1 274388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_MEM 0x2 275388431b9SFeng Liu 276388431b9SFeng Liu #define VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO 4 277388431b9SFeng Liu 278*ec6ecb84SSuzuki K Poulose struct virtio_admin_cmd_notify_info_data { 279388431b9SFeng Liu __u8 flags; /* 0 = end of list, 1 = owner device, 2 = member device */ 280388431b9SFeng Liu __u8 bar; /* BAR of the member or the owner device */ 281388431b9SFeng Liu __u8 padding[6]; 282388431b9SFeng Liu __le64 offset; /* Offset within bar. */ 283388431b9SFeng Liu }; 284388431b9SFeng Liu 285388431b9SFeng Liu struct virtio_admin_cmd_notify_info_result { 286388431b9SFeng Liu struct virtio_admin_cmd_notify_info_data entries[VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO]; 287388431b9SFeng Liu }; 288388431b9SFeng Liu 289607ca46eSDavid Howells #endif 290