1*e2be04c7SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */ 2607ca46eSDavid Howells /* 3607ca46eSDavid Howells * SyncLink Multiprotocol Serial Adapter Driver 4607ca46eSDavid Howells * 5607ca46eSDavid Howells * $Id: synclink.h,v 3.14 2006/07/17 20:15:43 paulkf Exp $ 6607ca46eSDavid Howells * 7607ca46eSDavid Howells * Copyright (C) 1998-2000 by Microgate Corporation 8607ca46eSDavid Howells * 9607ca46eSDavid Howells * Redistribution of this file is permitted under 10607ca46eSDavid Howells * the terms of the GNU Public License (GPL) 11607ca46eSDavid Howells */ 12607ca46eSDavid Howells 13607ca46eSDavid Howells #ifndef _UAPI_SYNCLINK_H_ 14607ca46eSDavid Howells #define _UAPI_SYNCLINK_H_ 15607ca46eSDavid Howells #define SYNCLINK_H_VERSION 3.6 16607ca46eSDavid Howells 17607ca46eSDavid Howells #include <linux/types.h> 18607ca46eSDavid Howells 19607ca46eSDavid Howells #define BIT0 0x0001 20607ca46eSDavid Howells #define BIT1 0x0002 21607ca46eSDavid Howells #define BIT2 0x0004 22607ca46eSDavid Howells #define BIT3 0x0008 23607ca46eSDavid Howells #define BIT4 0x0010 24607ca46eSDavid Howells #define BIT5 0x0020 25607ca46eSDavid Howells #define BIT6 0x0040 26607ca46eSDavid Howells #define BIT7 0x0080 27607ca46eSDavid Howells #define BIT8 0x0100 28607ca46eSDavid Howells #define BIT9 0x0200 29607ca46eSDavid Howells #define BIT10 0x0400 30607ca46eSDavid Howells #define BIT11 0x0800 31607ca46eSDavid Howells #define BIT12 0x1000 32607ca46eSDavid Howells #define BIT13 0x2000 33607ca46eSDavid Howells #define BIT14 0x4000 34607ca46eSDavid Howells #define BIT15 0x8000 35607ca46eSDavid Howells #define BIT16 0x00010000 36607ca46eSDavid Howells #define BIT17 0x00020000 37607ca46eSDavid Howells #define BIT18 0x00040000 38607ca46eSDavid Howells #define BIT19 0x00080000 39607ca46eSDavid Howells #define BIT20 0x00100000 40607ca46eSDavid Howells #define BIT21 0x00200000 41607ca46eSDavid Howells #define BIT22 0x00400000 42607ca46eSDavid Howells #define BIT23 0x00800000 43607ca46eSDavid Howells #define BIT24 0x01000000 44607ca46eSDavid Howells #define BIT25 0x02000000 45607ca46eSDavid Howells #define BIT26 0x04000000 46607ca46eSDavid Howells #define BIT27 0x08000000 47607ca46eSDavid Howells #define BIT28 0x10000000 48607ca46eSDavid Howells #define BIT29 0x20000000 49607ca46eSDavid Howells #define BIT30 0x40000000 50607ca46eSDavid Howells #define BIT31 0x80000000 51607ca46eSDavid Howells 52607ca46eSDavid Howells 53607ca46eSDavid Howells #define HDLC_MAX_FRAME_SIZE 65535 54607ca46eSDavid Howells #define MAX_ASYNC_TRANSMIT 4096 55607ca46eSDavid Howells #define MAX_ASYNC_BUFFER_SIZE 4096 56607ca46eSDavid Howells 57607ca46eSDavid Howells #define ASYNC_PARITY_NONE 0 58607ca46eSDavid Howells #define ASYNC_PARITY_EVEN 1 59607ca46eSDavid Howells #define ASYNC_PARITY_ODD 2 60607ca46eSDavid Howells #define ASYNC_PARITY_SPACE 3 61607ca46eSDavid Howells 62607ca46eSDavid Howells #define HDLC_FLAG_UNDERRUN_ABORT7 0x0000 63607ca46eSDavid Howells #define HDLC_FLAG_UNDERRUN_ABORT15 0x0001 64607ca46eSDavid Howells #define HDLC_FLAG_UNDERRUN_FLAG 0x0002 65607ca46eSDavid Howells #define HDLC_FLAG_UNDERRUN_CRC 0x0004 66607ca46eSDavid Howells #define HDLC_FLAG_SHARE_ZERO 0x0010 67607ca46eSDavid Howells #define HDLC_FLAG_AUTO_CTS 0x0020 68607ca46eSDavid Howells #define HDLC_FLAG_AUTO_DCD 0x0040 69607ca46eSDavid Howells #define HDLC_FLAG_AUTO_RTS 0x0080 70607ca46eSDavid Howells #define HDLC_FLAG_RXC_DPLL 0x0100 71607ca46eSDavid Howells #define HDLC_FLAG_RXC_BRG 0x0200 72607ca46eSDavid Howells #define HDLC_FLAG_RXC_TXCPIN 0x8000 73607ca46eSDavid Howells #define HDLC_FLAG_RXC_RXCPIN 0x0000 74607ca46eSDavid Howells #define HDLC_FLAG_TXC_DPLL 0x0400 75607ca46eSDavid Howells #define HDLC_FLAG_TXC_BRG 0x0800 76607ca46eSDavid Howells #define HDLC_FLAG_TXC_TXCPIN 0x0000 77607ca46eSDavid Howells #define HDLC_FLAG_TXC_RXCPIN 0x0008 78607ca46eSDavid Howells #define HDLC_FLAG_DPLL_DIV8 0x1000 79607ca46eSDavid Howells #define HDLC_FLAG_DPLL_DIV16 0x2000 80607ca46eSDavid Howells #define HDLC_FLAG_DPLL_DIV32 0x0000 81607ca46eSDavid Howells #define HDLC_FLAG_HDLC_LOOPMODE 0x4000 82607ca46eSDavid Howells 83607ca46eSDavid Howells #define HDLC_CRC_NONE 0 84607ca46eSDavid Howells #define HDLC_CRC_16_CCITT 1 85607ca46eSDavid Howells #define HDLC_CRC_32_CCITT 2 86607ca46eSDavid Howells #define HDLC_CRC_MASK 0x00ff 87607ca46eSDavid Howells #define HDLC_CRC_RETURN_EX 0x8000 88607ca46eSDavid Howells 89607ca46eSDavid Howells #define RX_OK 0 90607ca46eSDavid Howells #define RX_CRC_ERROR 1 91607ca46eSDavid Howells 92607ca46eSDavid Howells #define HDLC_TXIDLE_FLAGS 0 93607ca46eSDavid Howells #define HDLC_TXIDLE_ALT_ZEROS_ONES 1 94607ca46eSDavid Howells #define HDLC_TXIDLE_ZEROS 2 95607ca46eSDavid Howells #define HDLC_TXIDLE_ONES 3 96607ca46eSDavid Howells #define HDLC_TXIDLE_ALT_MARK_SPACE 4 97607ca46eSDavid Howells #define HDLC_TXIDLE_SPACE 5 98607ca46eSDavid Howells #define HDLC_TXIDLE_MARK 6 99607ca46eSDavid Howells #define HDLC_TXIDLE_CUSTOM_8 0x10000000 100607ca46eSDavid Howells #define HDLC_TXIDLE_CUSTOM_16 0x20000000 101607ca46eSDavid Howells 102607ca46eSDavid Howells #define HDLC_ENCODING_NRZ 0 103607ca46eSDavid Howells #define HDLC_ENCODING_NRZB 1 104607ca46eSDavid Howells #define HDLC_ENCODING_NRZI_MARK 2 105607ca46eSDavid Howells #define HDLC_ENCODING_NRZI_SPACE 3 106607ca46eSDavid Howells #define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE 107607ca46eSDavid Howells #define HDLC_ENCODING_BIPHASE_MARK 4 108607ca46eSDavid Howells #define HDLC_ENCODING_BIPHASE_SPACE 5 109607ca46eSDavid Howells #define HDLC_ENCODING_BIPHASE_LEVEL 6 110607ca46eSDavid Howells #define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7 111607ca46eSDavid Howells 112607ca46eSDavid Howells #define HDLC_PREAMBLE_LENGTH_8BITS 0 113607ca46eSDavid Howells #define HDLC_PREAMBLE_LENGTH_16BITS 1 114607ca46eSDavid Howells #define HDLC_PREAMBLE_LENGTH_32BITS 2 115607ca46eSDavid Howells #define HDLC_PREAMBLE_LENGTH_64BITS 3 116607ca46eSDavid Howells 117607ca46eSDavid Howells #define HDLC_PREAMBLE_PATTERN_NONE 0 118607ca46eSDavid Howells #define HDLC_PREAMBLE_PATTERN_ZEROS 1 119607ca46eSDavid Howells #define HDLC_PREAMBLE_PATTERN_FLAGS 2 120607ca46eSDavid Howells #define HDLC_PREAMBLE_PATTERN_10 3 121607ca46eSDavid Howells #define HDLC_PREAMBLE_PATTERN_01 4 122607ca46eSDavid Howells #define HDLC_PREAMBLE_PATTERN_ONES 5 123607ca46eSDavid Howells 124607ca46eSDavid Howells #define MGSL_MODE_ASYNC 1 125607ca46eSDavid Howells #define MGSL_MODE_HDLC 2 126607ca46eSDavid Howells #define MGSL_MODE_MONOSYNC 3 127607ca46eSDavid Howells #define MGSL_MODE_BISYNC 4 128607ca46eSDavid Howells #define MGSL_MODE_RAW 6 129607ca46eSDavid Howells #define MGSL_MODE_BASE_CLOCK 7 130607ca46eSDavid Howells #define MGSL_MODE_XSYNC 8 131607ca46eSDavid Howells 132607ca46eSDavid Howells #define MGSL_BUS_TYPE_ISA 1 133607ca46eSDavid Howells #define MGSL_BUS_TYPE_EISA 2 134607ca46eSDavid Howells #define MGSL_BUS_TYPE_PCI 5 135607ca46eSDavid Howells 136607ca46eSDavid Howells #define MGSL_INTERFACE_MASK 0xf 137607ca46eSDavid Howells #define MGSL_INTERFACE_DISABLE 0 138607ca46eSDavid Howells #define MGSL_INTERFACE_RS232 1 139607ca46eSDavid Howells #define MGSL_INTERFACE_V35 2 140607ca46eSDavid Howells #define MGSL_INTERFACE_RS422 3 141607ca46eSDavid Howells #define MGSL_INTERFACE_RTS_EN 0x10 142607ca46eSDavid Howells #define MGSL_INTERFACE_LL 0x20 143607ca46eSDavid Howells #define MGSL_INTERFACE_RL 0x40 144607ca46eSDavid Howells #define MGSL_INTERFACE_MSB_FIRST 0x80 145607ca46eSDavid Howells 146607ca46eSDavid Howells typedef struct _MGSL_PARAMS 147607ca46eSDavid Howells { 148607ca46eSDavid Howells /* Common */ 149607ca46eSDavid Howells 150607ca46eSDavid Howells unsigned long mode; /* Asynchronous or HDLC */ 151607ca46eSDavid Howells unsigned char loopback; /* internal loopback mode */ 152607ca46eSDavid Howells 153607ca46eSDavid Howells /* HDLC Only */ 154607ca46eSDavid Howells 155607ca46eSDavid Howells unsigned short flags; 156607ca46eSDavid Howells unsigned char encoding; /* NRZ, NRZI, etc. */ 157607ca46eSDavid Howells unsigned long clock_speed; /* external clock speed in bits per second */ 158607ca46eSDavid Howells unsigned char addr_filter; /* receive HDLC address filter, 0xFF = disable */ 159607ca46eSDavid Howells unsigned short crc_type; /* None, CRC16-CCITT, or CRC32-CCITT */ 160607ca46eSDavid Howells unsigned char preamble_length; 161607ca46eSDavid Howells unsigned char preamble; 162607ca46eSDavid Howells 163607ca46eSDavid Howells /* Async Only */ 164607ca46eSDavid Howells 165607ca46eSDavid Howells unsigned long data_rate; /* bits per second */ 166607ca46eSDavid Howells unsigned char data_bits; /* 7 or 8 data bits */ 167607ca46eSDavid Howells unsigned char stop_bits; /* 1 or 2 stop bits */ 168607ca46eSDavid Howells unsigned char parity; /* none, even, or odd */ 169607ca46eSDavid Howells 170607ca46eSDavid Howells } MGSL_PARAMS, *PMGSL_PARAMS; 171607ca46eSDavid Howells 172607ca46eSDavid Howells #define MICROGATE_VENDOR_ID 0x13c0 173607ca46eSDavid Howells #define SYNCLINK_DEVICE_ID 0x0010 174607ca46eSDavid Howells #define MGSCC_DEVICE_ID 0x0020 175607ca46eSDavid Howells #define SYNCLINK_SCA_DEVICE_ID 0x0030 176607ca46eSDavid Howells #define SYNCLINK_GT_DEVICE_ID 0x0070 177607ca46eSDavid Howells #define SYNCLINK_GT4_DEVICE_ID 0x0080 178607ca46eSDavid Howells #define SYNCLINK_AC_DEVICE_ID 0x0090 179607ca46eSDavid Howells #define SYNCLINK_GT2_DEVICE_ID 0x00A0 180607ca46eSDavid Howells #define MGSL_MAX_SERIAL_NUMBER 30 181607ca46eSDavid Howells 182607ca46eSDavid Howells /* 183607ca46eSDavid Howells ** device diagnostics status 184607ca46eSDavid Howells */ 185607ca46eSDavid Howells 186607ca46eSDavid Howells #define DiagStatus_OK 0 187607ca46eSDavid Howells #define DiagStatus_AddressFailure 1 188607ca46eSDavid Howells #define DiagStatus_AddressConflict 2 189607ca46eSDavid Howells #define DiagStatus_IrqFailure 3 190607ca46eSDavid Howells #define DiagStatus_IrqConflict 4 191607ca46eSDavid Howells #define DiagStatus_DmaFailure 5 192607ca46eSDavid Howells #define DiagStatus_DmaConflict 6 193607ca46eSDavid Howells #define DiagStatus_PciAdapterNotFound 7 194607ca46eSDavid Howells #define DiagStatus_CantAssignPciResources 8 195607ca46eSDavid Howells #define DiagStatus_CantAssignPciMemAddr 9 196607ca46eSDavid Howells #define DiagStatus_CantAssignPciIoAddr 10 197607ca46eSDavid Howells #define DiagStatus_CantAssignPciIrq 11 198607ca46eSDavid Howells #define DiagStatus_MemoryError 12 199607ca46eSDavid Howells 200607ca46eSDavid Howells #define SerialSignal_DCD 0x01 /* Data Carrier Detect */ 201607ca46eSDavid Howells #define SerialSignal_TXD 0x02 /* Transmit Data */ 202607ca46eSDavid Howells #define SerialSignal_RI 0x04 /* Ring Indicator */ 203607ca46eSDavid Howells #define SerialSignal_RXD 0x08 /* Receive Data */ 204607ca46eSDavid Howells #define SerialSignal_CTS 0x10 /* Clear to Send */ 205607ca46eSDavid Howells #define SerialSignal_RTS 0x20 /* Request to Send */ 206607ca46eSDavid Howells #define SerialSignal_DSR 0x40 /* Data Set Ready */ 207607ca46eSDavid Howells #define SerialSignal_DTR 0x80 /* Data Terminal Ready */ 208607ca46eSDavid Howells 209607ca46eSDavid Howells 210607ca46eSDavid Howells /* 211607ca46eSDavid Howells * Counters of the input lines (CTS, DSR, RI, CD) interrupts 212607ca46eSDavid Howells */ 213607ca46eSDavid Howells struct mgsl_icount { 214607ca46eSDavid Howells __u32 cts, dsr, rng, dcd, tx, rx; 215607ca46eSDavid Howells __u32 frame, parity, overrun, brk; 216607ca46eSDavid Howells __u32 buf_overrun; 217607ca46eSDavid Howells __u32 txok; 218607ca46eSDavid Howells __u32 txunder; 219607ca46eSDavid Howells __u32 txabort; 220607ca46eSDavid Howells __u32 txtimeout; 221607ca46eSDavid Howells __u32 rxshort; 222607ca46eSDavid Howells __u32 rxlong; 223607ca46eSDavid Howells __u32 rxabort; 224607ca46eSDavid Howells __u32 rxover; 225607ca46eSDavid Howells __u32 rxcrc; 226607ca46eSDavid Howells __u32 rxok; 227607ca46eSDavid Howells __u32 exithunt; 228607ca46eSDavid Howells __u32 rxidle; 229607ca46eSDavid Howells }; 230607ca46eSDavid Howells 231607ca46eSDavid Howells struct gpio_desc { 232607ca46eSDavid Howells __u32 state; 233607ca46eSDavid Howells __u32 smask; 234607ca46eSDavid Howells __u32 dir; 235607ca46eSDavid Howells __u32 dmask; 236607ca46eSDavid Howells }; 237607ca46eSDavid Howells 238607ca46eSDavid Howells #define DEBUG_LEVEL_DATA 1 239607ca46eSDavid Howells #define DEBUG_LEVEL_ERROR 2 240607ca46eSDavid Howells #define DEBUG_LEVEL_INFO 3 241607ca46eSDavid Howells #define DEBUG_LEVEL_BH 4 242607ca46eSDavid Howells #define DEBUG_LEVEL_ISR 5 243607ca46eSDavid Howells 244607ca46eSDavid Howells /* 245607ca46eSDavid Howells ** Event bit flags for use with MgslWaitEvent 246607ca46eSDavid Howells */ 247607ca46eSDavid Howells 248607ca46eSDavid Howells #define MgslEvent_DsrActive 0x0001 249607ca46eSDavid Howells #define MgslEvent_DsrInactive 0x0002 250607ca46eSDavid Howells #define MgslEvent_Dsr 0x0003 251607ca46eSDavid Howells #define MgslEvent_CtsActive 0x0004 252607ca46eSDavid Howells #define MgslEvent_CtsInactive 0x0008 253607ca46eSDavid Howells #define MgslEvent_Cts 0x000c 254607ca46eSDavid Howells #define MgslEvent_DcdActive 0x0010 255607ca46eSDavid Howells #define MgslEvent_DcdInactive 0x0020 256607ca46eSDavid Howells #define MgslEvent_Dcd 0x0030 257607ca46eSDavid Howells #define MgslEvent_RiActive 0x0040 258607ca46eSDavid Howells #define MgslEvent_RiInactive 0x0080 259607ca46eSDavid Howells #define MgslEvent_Ri 0x00c0 260607ca46eSDavid Howells #define MgslEvent_ExitHuntMode 0x0100 261607ca46eSDavid Howells #define MgslEvent_IdleReceived 0x0200 262607ca46eSDavid Howells 263607ca46eSDavid Howells /* Private IOCTL codes: 264607ca46eSDavid Howells * 265607ca46eSDavid Howells * MGSL_IOCSPARAMS set MGSL_PARAMS structure values 266607ca46eSDavid Howells * MGSL_IOCGPARAMS get current MGSL_PARAMS structure values 267607ca46eSDavid Howells * MGSL_IOCSTXIDLE set current transmit idle mode 268607ca46eSDavid Howells * MGSL_IOCGTXIDLE get current transmit idle mode 269607ca46eSDavid Howells * MGSL_IOCTXENABLE enable or disable transmitter 270607ca46eSDavid Howells * MGSL_IOCRXENABLE enable or disable receiver 271607ca46eSDavid Howells * MGSL_IOCTXABORT abort transmitting frame (HDLC) 272607ca46eSDavid Howells * MGSL_IOCGSTATS return current statistics 273607ca46eSDavid Howells * MGSL_IOCWAITEVENT wait for specified event to occur 274607ca46eSDavid Howells * MGSL_LOOPTXDONE transmit in HDLC LoopMode done 275607ca46eSDavid Howells * MGSL_IOCSIF set the serial interface type 276607ca46eSDavid Howells * MGSL_IOCGIF get the serial interface type 277607ca46eSDavid Howells */ 278607ca46eSDavid Howells #define MGSL_MAGIC_IOC 'm' 279607ca46eSDavid Howells #define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS) 280607ca46eSDavid Howells #define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS) 281607ca46eSDavid Howells #define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC,2) 282607ca46eSDavid Howells #define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC,3) 283607ca46eSDavid Howells #define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC,4) 284607ca46eSDavid Howells #define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC,5) 285607ca46eSDavid Howells #define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC,6) 286607ca46eSDavid Howells #define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC,7) 287607ca46eSDavid Howells #define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC,8,int) 288607ca46eSDavid Howells #define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC,15) 289607ca46eSDavid Howells #define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC,9) 290607ca46eSDavid Howells #define MGSL_IOCSIF _IO(MGSL_MAGIC_IOC,10) 291607ca46eSDavid Howells #define MGSL_IOCGIF _IO(MGSL_MAGIC_IOC,11) 292607ca46eSDavid Howells #define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC,16,struct gpio_desc) 293607ca46eSDavid Howells #define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC,17,struct gpio_desc) 294607ca46eSDavid Howells #define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc) 295607ca46eSDavid Howells #define MGSL_IOCSXSYNC _IO(MGSL_MAGIC_IOC, 19) 296607ca46eSDavid Howells #define MGSL_IOCGXSYNC _IO(MGSL_MAGIC_IOC, 20) 297607ca46eSDavid Howells #define MGSL_IOCSXCTRL _IO(MGSL_MAGIC_IOC, 21) 298607ca46eSDavid Howells #define MGSL_IOCGXCTRL _IO(MGSL_MAGIC_IOC, 22) 299607ca46eSDavid Howells 300607ca46eSDavid Howells 301607ca46eSDavid Howells #endif /* _UAPI_SYNCLINK_H_ */ 302