1e2be04c7SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2607ca46eSDavid Howells /* 3607ca46eSDavid Howells * Performance events: 4607ca46eSDavid Howells * 5607ca46eSDavid Howells * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> 6607ca46eSDavid Howells * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7607ca46eSDavid Howells * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8607ca46eSDavid Howells * 9607ca46eSDavid Howells * Data type definitions, declarations, prototypes. 10607ca46eSDavid Howells * 11607ca46eSDavid Howells * Started by: Thomas Gleixner and Ingo Molnar 12607ca46eSDavid Howells * 13607ca46eSDavid Howells * For licencing details see kernel-base/COPYING 14607ca46eSDavid Howells */ 15607ca46eSDavid Howells #ifndef _UAPI_LINUX_PERF_EVENT_H 16607ca46eSDavid Howells #define _UAPI_LINUX_PERF_EVENT_H 17607ca46eSDavid Howells 18607ca46eSDavid Howells #include <linux/types.h> 19607ca46eSDavid Howells #include <linux/ioctl.h> 20607ca46eSDavid Howells #include <asm/byteorder.h> 21607ca46eSDavid Howells 22607ca46eSDavid Howells /* 23607ca46eSDavid Howells * User-space ABI bits: 24607ca46eSDavid Howells */ 25607ca46eSDavid Howells 26607ca46eSDavid Howells /* 27607ca46eSDavid Howells * attr.type 28607ca46eSDavid Howells */ 29607ca46eSDavid Howells enum perf_type_id { 30607ca46eSDavid Howells PERF_TYPE_HARDWARE = 0, 31607ca46eSDavid Howells PERF_TYPE_SOFTWARE = 1, 32607ca46eSDavid Howells PERF_TYPE_TRACEPOINT = 2, 33607ca46eSDavid Howells PERF_TYPE_HW_CACHE = 3, 34607ca46eSDavid Howells PERF_TYPE_RAW = 4, 35607ca46eSDavid Howells PERF_TYPE_BREAKPOINT = 5, 36607ca46eSDavid Howells 37607ca46eSDavid Howells PERF_TYPE_MAX, /* non-ABI */ 38607ca46eSDavid Howells }; 39607ca46eSDavid Howells 40607ca46eSDavid Howells /* 4155bcf6efSKan Liang * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE 4255bcf6efSKan Liang * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA 4355bcf6efSKan Liang * AA: hardware event ID 4455bcf6efSKan Liang * EEEEEEEE: PMU type ID 4555bcf6efSKan Liang * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB 4655bcf6efSKan Liang * BB: hardware cache ID 4755bcf6efSKan Liang * CC: hardware cache op ID 4855bcf6efSKan Liang * DD: hardware cache op result ID 4955bcf6efSKan Liang * EEEEEEEE: PMU type ID 5055bcf6efSKan Liang * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied. 5155bcf6efSKan Liang */ 5255bcf6efSKan Liang #define PERF_PMU_TYPE_SHIFT 32 5355bcf6efSKan Liang #define PERF_HW_EVENT_MASK 0xffffffff 5455bcf6efSKan Liang 5555bcf6efSKan Liang /* 56607ca46eSDavid Howells * Generalized performance event event_id types, used by the 57607ca46eSDavid Howells * attr.event_id parameter of the sys_perf_event_open() 58607ca46eSDavid Howells * syscall: 59607ca46eSDavid Howells */ 60607ca46eSDavid Howells enum perf_hw_id { 61607ca46eSDavid Howells /* 62607ca46eSDavid Howells * Common hardware events, generalized by the kernel: 63607ca46eSDavid Howells */ 64607ca46eSDavid Howells PERF_COUNT_HW_CPU_CYCLES = 0, 65607ca46eSDavid Howells PERF_COUNT_HW_INSTRUCTIONS = 1, 66607ca46eSDavid Howells PERF_COUNT_HW_CACHE_REFERENCES = 2, 67607ca46eSDavid Howells PERF_COUNT_HW_CACHE_MISSES = 3, 68607ca46eSDavid Howells PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 69607ca46eSDavid Howells PERF_COUNT_HW_BRANCH_MISSES = 5, 70607ca46eSDavid Howells PERF_COUNT_HW_BUS_CYCLES = 6, 71607ca46eSDavid Howells PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 72607ca46eSDavid Howells PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 73607ca46eSDavid Howells PERF_COUNT_HW_REF_CPU_CYCLES = 9, 74607ca46eSDavid Howells 75607ca46eSDavid Howells PERF_COUNT_HW_MAX, /* non-ABI */ 76607ca46eSDavid Howells }; 77607ca46eSDavid Howells 78607ca46eSDavid Howells /* 79607ca46eSDavid Howells * Generalized hardware cache events: 80607ca46eSDavid Howells * 81607ca46eSDavid Howells * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 82607ca46eSDavid Howells * { read, write, prefetch } x 83607ca46eSDavid Howells * { accesses, misses } 84607ca46eSDavid Howells */ 85607ca46eSDavid Howells enum perf_hw_cache_id { 86607ca46eSDavid Howells PERF_COUNT_HW_CACHE_L1D = 0, 87607ca46eSDavid Howells PERF_COUNT_HW_CACHE_L1I = 1, 88607ca46eSDavid Howells PERF_COUNT_HW_CACHE_LL = 2, 89607ca46eSDavid Howells PERF_COUNT_HW_CACHE_DTLB = 3, 90607ca46eSDavid Howells PERF_COUNT_HW_CACHE_ITLB = 4, 91607ca46eSDavid Howells PERF_COUNT_HW_CACHE_BPU = 5, 92607ca46eSDavid Howells PERF_COUNT_HW_CACHE_NODE = 6, 93607ca46eSDavid Howells 94607ca46eSDavid Howells PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 95607ca46eSDavid Howells }; 96607ca46eSDavid Howells 97607ca46eSDavid Howells enum perf_hw_cache_op_id { 98607ca46eSDavid Howells PERF_COUNT_HW_CACHE_OP_READ = 0, 99607ca46eSDavid Howells PERF_COUNT_HW_CACHE_OP_WRITE = 1, 100607ca46eSDavid Howells PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 101607ca46eSDavid Howells 102607ca46eSDavid Howells PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 103607ca46eSDavid Howells }; 104607ca46eSDavid Howells 105607ca46eSDavid Howells enum perf_hw_cache_op_result_id { 106607ca46eSDavid Howells PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 107607ca46eSDavid Howells PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 108607ca46eSDavid Howells 109607ca46eSDavid Howells PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 110607ca46eSDavid Howells }; 111607ca46eSDavid Howells 112607ca46eSDavid Howells /* 113607ca46eSDavid Howells * Special "software" events provided by the kernel, even if the hardware 114607ca46eSDavid Howells * does not support performance events. These events measure various 115607ca46eSDavid Howells * physical and sw events of the kernel (and allow the profiling of them as 116607ca46eSDavid Howells * well): 117607ca46eSDavid Howells */ 118607ca46eSDavid Howells enum perf_sw_ids { 119607ca46eSDavid Howells PERF_COUNT_SW_CPU_CLOCK = 0, 120607ca46eSDavid Howells PERF_COUNT_SW_TASK_CLOCK = 1, 121607ca46eSDavid Howells PERF_COUNT_SW_PAGE_FAULTS = 2, 122607ca46eSDavid Howells PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 123607ca46eSDavid Howells PERF_COUNT_SW_CPU_MIGRATIONS = 4, 124607ca46eSDavid Howells PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 125607ca46eSDavid Howells PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 126607ca46eSDavid Howells PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 127607ca46eSDavid Howells PERF_COUNT_SW_EMULATION_FAULTS = 8, 128fa0097eeSAdrian Hunter PERF_COUNT_SW_DUMMY = 9, 129a43eec30SAlexei Starovoitov PERF_COUNT_SW_BPF_OUTPUT = 10, 130d0d1dd62SNamhyung Kim PERF_COUNT_SW_CGROUP_SWITCHES = 11, 131607ca46eSDavid Howells 132607ca46eSDavid Howells PERF_COUNT_SW_MAX, /* non-ABI */ 133607ca46eSDavid Howells }; 134607ca46eSDavid Howells 135607ca46eSDavid Howells /* 136607ca46eSDavid Howells * Bits that can be set in attr.sample_type to request information 137607ca46eSDavid Howells * in the overflow packets. 138607ca46eSDavid Howells */ 139607ca46eSDavid Howells enum perf_event_sample_format { 140607ca46eSDavid Howells PERF_SAMPLE_IP = 1U << 0, 141607ca46eSDavid Howells PERF_SAMPLE_TID = 1U << 1, 142607ca46eSDavid Howells PERF_SAMPLE_TIME = 1U << 2, 143607ca46eSDavid Howells PERF_SAMPLE_ADDR = 1U << 3, 144607ca46eSDavid Howells PERF_SAMPLE_READ = 1U << 4, 145607ca46eSDavid Howells PERF_SAMPLE_CALLCHAIN = 1U << 5, 146607ca46eSDavid Howells PERF_SAMPLE_ID = 1U << 6, 147607ca46eSDavid Howells PERF_SAMPLE_CPU = 1U << 7, 148607ca46eSDavid Howells PERF_SAMPLE_PERIOD = 1U << 8, 149607ca46eSDavid Howells PERF_SAMPLE_STREAM_ID = 1U << 9, 150607ca46eSDavid Howells PERF_SAMPLE_RAW = 1U << 10, 151607ca46eSDavid Howells PERF_SAMPLE_BRANCH_STACK = 1U << 11, 152607ca46eSDavid Howells PERF_SAMPLE_REGS_USER = 1U << 12, 153607ca46eSDavid Howells PERF_SAMPLE_STACK_USER = 1U << 13, 154c3feedf2SAndi Kleen PERF_SAMPLE_WEIGHT = 1U << 14, 155d6be9ad6SStephane Eranian PERF_SAMPLE_DATA_SRC = 1U << 15, 156ff3d527cSAdrian Hunter PERF_SAMPLE_IDENTIFIER = 1U << 16, 157fdfbbd07SAndi Kleen PERF_SAMPLE_TRANSACTION = 1U << 17, 15860e2364eSStephane Eranian PERF_SAMPLE_REGS_INTR = 1U << 18, 159fc7ce9c7SKan Liang PERF_SAMPLE_PHYS_ADDR = 1U << 19, 160a4faf00dSAlexander Shishkin PERF_SAMPLE_AUX = 1U << 20, 1616546b19fSNamhyung Kim PERF_SAMPLE_CGROUP = 1U << 21, 1628d97e718SKan Liang PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, 163995f088eSStephane Eranian PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, 1642a6c6b7dSKan Liang PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, 165607ca46eSDavid Howells 1662a6c6b7dSKan Liang PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */ 167607ca46eSDavid Howells }; 168607ca46eSDavid Howells 1692a6c6b7dSKan Liang #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) 170607ca46eSDavid Howells /* 171607ca46eSDavid Howells * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 172607ca46eSDavid Howells * 173607ca46eSDavid Howells * If the user does not pass priv level information via branch_sample_type, 174607ca46eSDavid Howells * the kernel uses the event's priv level. Branch and event priv levels do 175607ca46eSDavid Howells * not have to match. Branch priv level is checked for permissions. 176607ca46eSDavid Howells * 177607ca46eSDavid Howells * The branch types can be combined, however BRANCH_ANY covers all types 178607ca46eSDavid Howells * of branches and therefore it supersedes all the other types. 179607ca46eSDavid Howells */ 18027ac905bSYan, Zheng enum perf_branch_sample_type_shift { 18127ac905bSYan, Zheng PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 18227ac905bSYan, Zheng PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 18327ac905bSYan, Zheng PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 18427ac905bSYan, Zheng 18527ac905bSYan, Zheng PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 18627ac905bSYan, Zheng PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 18727ac905bSYan, Zheng PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 18827ac905bSYan, Zheng PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 18927ac905bSYan, Zheng PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 19027ac905bSYan, Zheng PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 19127ac905bSYan, Zheng PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 19227ac905bSYan, Zheng PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 19327ac905bSYan, Zheng 1942c44b193SPeter Zijlstra PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 195c9fdfa14SStephane Eranian PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 196c229bf9dSStephane Eranian PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 1972c44b193SPeter Zijlstra 198b16a5b52SAndi Kleen PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 199b16a5b52SAndi Kleen PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 200b16a5b52SAndi Kleen 201eb0baf8aSJin Yao PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 202eb0baf8aSJin Yao 203bbfd5e4fSKan Liang PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 204bbfd5e4fSKan Liang 2055402d25aSAnshuman Khandual PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18, /* save privilege mode */ 2065402d25aSAnshuman Khandual 207571d91dcSKan Liang PERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19, /* save occurrences of events on a branch */ 208571d91dcSKan Liang 20927ac905bSYan, Zheng PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 21027ac905bSYan, Zheng }; 21127ac905bSYan, Zheng 212607ca46eSDavid Howells enum perf_branch_sample_type { 21327ac905bSYan, Zheng PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 21427ac905bSYan, Zheng PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 21527ac905bSYan, Zheng PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 216607ca46eSDavid Howells 21727ac905bSYan, Zheng PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 2182c44b193SPeter Zijlstra PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 2192c44b193SPeter Zijlstra PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 2202c44b193SPeter Zijlstra PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 2212c44b193SPeter Zijlstra PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 22227ac905bSYan, Zheng PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 22327ac905bSYan, Zheng PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 22427ac905bSYan, Zheng PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 225607ca46eSDavid Howells 2262c44b193SPeter Zijlstra PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 227c9fdfa14SStephane Eranian PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 228c229bf9dSStephane Eranian PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 2292c44b193SPeter Zijlstra 230b16a5b52SAndi Kleen PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 231b16a5b52SAndi Kleen PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 232b16a5b52SAndi Kleen 233eb0baf8aSJin Yao PERF_SAMPLE_BRANCH_TYPE_SAVE = 234eb0baf8aSJin Yao 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 235eb0baf8aSJin Yao 236bbfd5e4fSKan Liang PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 237bbfd5e4fSKan Liang 2385402d25aSAnshuman Khandual PERF_SAMPLE_BRANCH_PRIV_SAVE = 1U << PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT, 2395402d25aSAnshuman Khandual 240571d91dcSKan Liang PERF_SAMPLE_BRANCH_COUNTERS = 1U << PERF_SAMPLE_BRANCH_COUNTERS_SHIFT, 241571d91dcSKan Liang 24227ac905bSYan, Zheng PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 243607ca46eSDavid Howells }; 244607ca46eSDavid Howells 245eb0baf8aSJin Yao /* 246eb0baf8aSJin Yao * Common flow change classification 247eb0baf8aSJin Yao */ 248eb0baf8aSJin Yao enum { 249eb0baf8aSJin Yao PERF_BR_UNKNOWN = 0, /* unknown */ 250eb0baf8aSJin Yao PERF_BR_COND = 1, /* conditional */ 251eb0baf8aSJin Yao PERF_BR_UNCOND = 2, /* unconditional */ 252eb0baf8aSJin Yao PERF_BR_IND = 3, /* indirect */ 253eb0baf8aSJin Yao PERF_BR_CALL = 4, /* function call */ 254eb0baf8aSJin Yao PERF_BR_IND_CALL = 5, /* indirect function call */ 255eb0baf8aSJin Yao PERF_BR_RET = 6, /* function return */ 256eb0baf8aSJin Yao PERF_BR_SYSCALL = 7, /* syscall */ 257eb0baf8aSJin Yao PERF_BR_SYSRET = 8, /* syscall return */ 258eb0baf8aSJin Yao PERF_BR_COND_CALL = 9, /* conditional function call */ 259eb0baf8aSJin Yao PERF_BR_COND_RET = 10, /* conditional function return */ 260cedd3614SAnshuman Khandual PERF_BR_ERET = 11, /* exception return */ 261cedd3614SAnshuman Khandual PERF_BR_IRQ = 12, /* irq */ 262a724ec82SAnshuman Khandual PERF_BR_SERROR = 13, /* system error */ 263a724ec82SAnshuman Khandual PERF_BR_NO_TX = 14, /* not in transaction */ 264b190bc4aSAnshuman Khandual PERF_BR_EXTEND_ABI = 15, /* extend ABI */ 265eb0baf8aSJin Yao PERF_BR_MAX, 266eb0baf8aSJin Yao }; 267eb0baf8aSJin Yao 26893315e46SSandipan Das /* 26993315e46SSandipan Das * Common branch speculation outcome classification 27093315e46SSandipan Das */ 27193315e46SSandipan Das enum { 27293315e46SSandipan Das PERF_BR_SPEC_NA = 0, /* Not available */ 27393315e46SSandipan Das PERF_BR_SPEC_WRONG_PATH = 1, /* Speculative but on wrong path */ 27493315e46SSandipan Das PERF_BR_NON_SPEC_CORRECT_PATH = 2, /* Non-speculative but on correct path */ 27593315e46SSandipan Das PERF_BR_SPEC_CORRECT_PATH = 3, /* Speculative and on correct path */ 27693315e46SSandipan Das PERF_BR_SPEC_MAX, 27793315e46SSandipan Das }; 27893315e46SSandipan Das 279b190bc4aSAnshuman Khandual enum { 280b190bc4aSAnshuman Khandual PERF_BR_NEW_FAULT_ALGN = 0, /* Alignment fault */ 281b190bc4aSAnshuman Khandual PERF_BR_NEW_FAULT_DATA = 1, /* Data fault */ 282b190bc4aSAnshuman Khandual PERF_BR_NEW_FAULT_INST = 2, /* Inst fault */ 283b190bc4aSAnshuman Khandual PERF_BR_NEW_ARCH_1 = 3, /* Architecture specific */ 284b190bc4aSAnshuman Khandual PERF_BR_NEW_ARCH_2 = 4, /* Architecture specific */ 285b190bc4aSAnshuman Khandual PERF_BR_NEW_ARCH_3 = 5, /* Architecture specific */ 286b190bc4aSAnshuman Khandual PERF_BR_NEW_ARCH_4 = 6, /* Architecture specific */ 287b190bc4aSAnshuman Khandual PERF_BR_NEW_ARCH_5 = 7, /* Architecture specific */ 288b190bc4aSAnshuman Khandual PERF_BR_NEW_MAX, 289b190bc4aSAnshuman Khandual }; 290b190bc4aSAnshuman Khandual 2915402d25aSAnshuman Khandual enum { 2925402d25aSAnshuman Khandual PERF_BR_PRIV_UNKNOWN = 0, 2935402d25aSAnshuman Khandual PERF_BR_PRIV_USER = 1, 2945402d25aSAnshuman Khandual PERF_BR_PRIV_KERNEL = 2, 2955402d25aSAnshuman Khandual PERF_BR_PRIV_HV = 3, 2965402d25aSAnshuman Khandual }; 2975402d25aSAnshuman Khandual 298f4054e52SAnshuman Khandual #define PERF_BR_ARM64_FIQ PERF_BR_NEW_ARCH_1 299f4054e52SAnshuman Khandual #define PERF_BR_ARM64_DEBUG_HALT PERF_BR_NEW_ARCH_2 300f4054e52SAnshuman Khandual #define PERF_BR_ARM64_DEBUG_EXIT PERF_BR_NEW_ARCH_3 301f4054e52SAnshuman Khandual #define PERF_BR_ARM64_DEBUG_INST PERF_BR_NEW_ARCH_4 302f4054e52SAnshuman Khandual #define PERF_BR_ARM64_DEBUG_DATA PERF_BR_NEW_ARCH_5 303f4054e52SAnshuman Khandual 304607ca46eSDavid Howells #define PERF_SAMPLE_BRANCH_PLM_ALL \ 305607ca46eSDavid Howells (PERF_SAMPLE_BRANCH_USER|\ 306607ca46eSDavid Howells PERF_SAMPLE_BRANCH_KERNEL|\ 307607ca46eSDavid Howells PERF_SAMPLE_BRANCH_HV) 308607ca46eSDavid Howells 309607ca46eSDavid Howells /* 310607ca46eSDavid Howells * Values to determine ABI of the registers dump. 311607ca46eSDavid Howells */ 312607ca46eSDavid Howells enum perf_sample_regs_abi { 313607ca46eSDavid Howells PERF_SAMPLE_REGS_ABI_NONE = 0, 314607ca46eSDavid Howells PERF_SAMPLE_REGS_ABI_32 = 1, 315607ca46eSDavid Howells PERF_SAMPLE_REGS_ABI_64 = 2, 316607ca46eSDavid Howells }; 317607ca46eSDavid Howells 318607ca46eSDavid Howells /* 319fdfbbd07SAndi Kleen * Values for the memory transaction event qualifier, mostly for 320fdfbbd07SAndi Kleen * abort events. Multiple bits can be set. 321fdfbbd07SAndi Kleen */ 322fdfbbd07SAndi Kleen enum { 323fdfbbd07SAndi Kleen PERF_TXN_ELISION = (1 << 0), /* From elision */ 324fdfbbd07SAndi Kleen PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 325fdfbbd07SAndi Kleen PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 326fdfbbd07SAndi Kleen PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 327fdfbbd07SAndi Kleen PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 328fdfbbd07SAndi Kleen PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 329fdfbbd07SAndi Kleen PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 330fdfbbd07SAndi Kleen PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 331fdfbbd07SAndi Kleen 332fdfbbd07SAndi Kleen PERF_TXN_MAX = (1 << 8), /* non-ABI */ 333fdfbbd07SAndi Kleen 334fdfbbd07SAndi Kleen /* bits 32..63 are reserved for the abort code */ 335fdfbbd07SAndi Kleen 336fdfbbd07SAndi Kleen PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 337fdfbbd07SAndi Kleen PERF_TXN_ABORT_SHIFT = 32, 338fdfbbd07SAndi Kleen }; 339fdfbbd07SAndi Kleen 340fdfbbd07SAndi Kleen /* 341607ca46eSDavid Howells * The format of the data returned by read() on a perf event fd, 342607ca46eSDavid Howells * as specified by attr.read_format: 343607ca46eSDavid Howells * 344607ca46eSDavid Howells * struct read_format { 345607ca46eSDavid Howells * { u64 value; 346607ca46eSDavid Howells * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 347607ca46eSDavid Howells * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 348607ca46eSDavid Howells * { u64 id; } && PERF_FORMAT_ID 349119a784cSNamhyung Kim * { u64 lost; } && PERF_FORMAT_LOST 350607ca46eSDavid Howells * } && !PERF_FORMAT_GROUP 351607ca46eSDavid Howells * 352607ca46eSDavid Howells * { u64 nr; 353607ca46eSDavid Howells * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 354607ca46eSDavid Howells * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 355607ca46eSDavid Howells * { u64 value; 356607ca46eSDavid Howells * { u64 id; } && PERF_FORMAT_ID 357119a784cSNamhyung Kim * { u64 lost; } && PERF_FORMAT_LOST 358607ca46eSDavid Howells * } cntr[nr]; 359607ca46eSDavid Howells * } && PERF_FORMAT_GROUP 360607ca46eSDavid Howells * }; 361607ca46eSDavid Howells */ 362607ca46eSDavid Howells enum perf_event_read_format { 363607ca46eSDavid Howells PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 364607ca46eSDavid Howells PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 365607ca46eSDavid Howells PERF_FORMAT_ID = 1U << 2, 366607ca46eSDavid Howells PERF_FORMAT_GROUP = 1U << 3, 367119a784cSNamhyung Kim PERF_FORMAT_LOST = 1U << 4, 368607ca46eSDavid Howells 369119a784cSNamhyung Kim PERF_FORMAT_MAX = 1U << 5, /* non-ABI */ 370607ca46eSDavid Howells }; 371607ca46eSDavid Howells 372607ca46eSDavid Howells #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 373607ca46eSDavid Howells #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 374607ca46eSDavid Howells #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 375607ca46eSDavid Howells #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 376607ca46eSDavid Howells /* add: sample_stack_user */ 37760e2364eSStephane Eranian #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 3781a594131SAlexander Shishkin #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 379a4faf00dSAlexander Shishkin #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 38097ba62b2SMarco Elver #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ 38109519ec3SRob Herring #define PERF_ATTR_SIZE_VER8 136 /* add: config3 */ 382607ca46eSDavid Howells 383607ca46eSDavid Howells /* 384607ca46eSDavid Howells * Hardware event_id to monitor via a performance monitoring event: 38597c79a38SArnaldo Carvalho de Melo * 38697c79a38SArnaldo Carvalho de Melo * @sample_max_stack: Max number of frame pointers in a callchain, 38797c79a38SArnaldo Carvalho de Melo * should be < /proc/sys/kernel/perf_event_max_stack 388607ca46eSDavid Howells */ 389607ca46eSDavid Howells struct perf_event_attr { 390607ca46eSDavid Howells 391607ca46eSDavid Howells /* 392607ca46eSDavid Howells * Major type: hardware/software/tracepoint/etc. 393607ca46eSDavid Howells */ 394607ca46eSDavid Howells __u32 type; 395607ca46eSDavid Howells 396607ca46eSDavid Howells /* 397607ca46eSDavid Howells * Size of the attr structure, for fwd/bwd compat. 398607ca46eSDavid Howells */ 399607ca46eSDavid Howells __u32 size; 400607ca46eSDavid Howells 401607ca46eSDavid Howells /* 402607ca46eSDavid Howells * Type specific configuration information. 403607ca46eSDavid Howells */ 404607ca46eSDavid Howells __u64 config; 405607ca46eSDavid Howells 406607ca46eSDavid Howells union { 407607ca46eSDavid Howells __u64 sample_period; 408607ca46eSDavid Howells __u64 sample_freq; 409607ca46eSDavid Howells }; 410607ca46eSDavid Howells 411607ca46eSDavid Howells __u64 sample_type; 412607ca46eSDavid Howells __u64 read_format; 413607ca46eSDavid Howells 414607ca46eSDavid Howells __u64 disabled : 1, /* off by default */ 415607ca46eSDavid Howells inherit : 1, /* children inherit it */ 416607ca46eSDavid Howells pinned : 1, /* must always be on PMU */ 417607ca46eSDavid Howells exclusive : 1, /* only group on PMU */ 418607ca46eSDavid Howells exclude_user : 1, /* don't count user */ 419607ca46eSDavid Howells exclude_kernel : 1, /* ditto kernel */ 420607ca46eSDavid Howells exclude_hv : 1, /* ditto hypervisor */ 421607ca46eSDavid Howells exclude_idle : 1, /* don't count when idle */ 422607ca46eSDavid Howells mmap : 1, /* include mmap data */ 423607ca46eSDavid Howells comm : 1, /* include comm data */ 424607ca46eSDavid Howells freq : 1, /* use freq, not period */ 425607ca46eSDavid Howells inherit_stat : 1, /* per task counts */ 426607ca46eSDavid Howells enable_on_exec : 1, /* next exec enables */ 427607ca46eSDavid Howells task : 1, /* trace fork/exit */ 428607ca46eSDavid Howells watermark : 1, /* wakeup_watermark */ 429607ca46eSDavid Howells /* 430607ca46eSDavid Howells * precise_ip: 431607ca46eSDavid Howells * 432607ca46eSDavid Howells * 0 - SAMPLE_IP can have arbitrary skid 433607ca46eSDavid Howells * 1 - SAMPLE_IP must have constant skid 434607ca46eSDavid Howells * 2 - SAMPLE_IP requested to have 0 skid 435607ca46eSDavid Howells * 3 - SAMPLE_IP must have 0 skid 436607ca46eSDavid Howells * 437607ca46eSDavid Howells * See also PERF_RECORD_MISC_EXACT_IP 438607ca46eSDavid Howells */ 439607ca46eSDavid Howells precise_ip : 2, /* skid constraint */ 440607ca46eSDavid Howells mmap_data : 1, /* non-exec mmap data */ 441607ca46eSDavid Howells sample_id_all : 1, /* sample_type all events */ 442607ca46eSDavid Howells 443607ca46eSDavid Howells exclude_host : 1, /* don't count in host */ 444607ca46eSDavid Howells exclude_guest : 1, /* don't count in guest */ 445607ca46eSDavid Howells 446607ca46eSDavid Howells exclude_callchain_kernel : 1, /* exclude kernel callchains */ 447607ca46eSDavid Howells exclude_callchain_user : 1, /* exclude user callchains */ 44813d7a241SStephane Eranian mmap2 : 1, /* include mmap with inode data */ 44982b89778SAdrian Hunter comm_exec : 1, /* flag comm events that are due to an exec */ 45034f43927SPeter Zijlstra use_clockid : 1, /* use @clockid for time fields */ 45145ac1403SAdrian Hunter context_switch : 1, /* context switch data */ 4529ecda41aSWang Nan write_backward : 1, /* Write ring buffer from end to beginning */ 453e4222673SHari Bathini namespaces : 1, /* include namespaces data */ 45476193a94SSong Liu ksymbol : 1, /* include ksymbol events */ 4556ee52e2aSSong Liu bpf_event : 1, /* include bpf events */ 456ab43762eSAlexander Shishkin aux_output : 1, /* generate AUX records instead of events */ 45796aaab68SNamhyung Kim cgroup : 1, /* include cgroup events */ 458e17d43b9SAdrian Hunter text_poke : 1, /* include text poke events */ 45988a16a13SJiri Olsa build_id : 1, /* use build id in mmap2 events */ 4602b26f0aaSMarco Elver inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */ 4612e498d0aSMarco Elver remove_on_exec : 1, /* event is removed from task on exec */ 46297ba62b2SMarco Elver sigtrap : 1, /* send synchronous SIGTRAP on event */ 46397ba62b2SMarco Elver __reserved_1 : 26; 464607ca46eSDavid Howells 465607ca46eSDavid Howells union { 466607ca46eSDavid Howells __u32 wakeup_events; /* wakeup every n events */ 467607ca46eSDavid Howells __u32 wakeup_watermark; /* bytes before wakeup */ 468607ca46eSDavid Howells }; 469607ca46eSDavid Howells 470607ca46eSDavid Howells __u32 bp_type; 471607ca46eSDavid Howells union { 472607ca46eSDavid Howells __u64 bp_addr; 47365074d43SSong Liu __u64 kprobe_func; /* for perf_kprobe */ 47465074d43SSong Liu __u64 uprobe_path; /* for perf_uprobe */ 475607ca46eSDavid Howells __u64 config1; /* extension of config */ 476607ca46eSDavid Howells }; 477607ca46eSDavid Howells union { 478607ca46eSDavid Howells __u64 bp_len; 47965074d43SSong Liu __u64 kprobe_addr; /* when kprobe_func == NULL */ 48065074d43SSong Liu __u64 probe_offset; /* for perf_[k,u]probe */ 481607ca46eSDavid Howells __u64 config2; /* extension of config1 */ 482607ca46eSDavid Howells }; 483607ca46eSDavid Howells __u64 branch_sample_type; /* enum perf_branch_sample_type */ 484607ca46eSDavid Howells 485607ca46eSDavid Howells /* 486607ca46eSDavid Howells * Defines set of user regs to dump on samples. 487607ca46eSDavid Howells * See asm/perf_regs.h for details. 488607ca46eSDavid Howells */ 489607ca46eSDavid Howells __u64 sample_regs_user; 490607ca46eSDavid Howells 491607ca46eSDavid Howells /* 492607ca46eSDavid Howells * Defines size of the user stack to dump on samples. 493607ca46eSDavid Howells */ 494607ca46eSDavid Howells __u32 sample_stack_user; 495607ca46eSDavid Howells 49634f43927SPeter Zijlstra __s32 clockid; 49760e2364eSStephane Eranian /* 49860e2364eSStephane Eranian * Defines set of regs to dump for each sample 49960e2364eSStephane Eranian * state captured on: 50060e2364eSStephane Eranian * - precise = 0: PMU interrupt 50160e2364eSStephane Eranian * - precise > 0: sampled instruction 50260e2364eSStephane Eranian * 50360e2364eSStephane Eranian * See asm/perf_regs.h for details. 50460e2364eSStephane Eranian */ 50560e2364eSStephane Eranian __u64 sample_regs_intr; 5061a594131SAlexander Shishkin 5071a594131SAlexander Shishkin /* 5081a594131SAlexander Shishkin * Wakeup watermark for AUX area 5091a594131SAlexander Shishkin */ 5101a594131SAlexander Shishkin __u32 aux_watermark; 51197c79a38SArnaldo Carvalho de Melo __u16 sample_max_stack; 512a4faf00dSAlexander Shishkin __u16 __reserved_2; 513a4faf00dSAlexander Shishkin __u32 aux_sample_size; 514a4faf00dSAlexander Shishkin __u32 __reserved_3; 51597ba62b2SMarco Elver 51697ba62b2SMarco Elver /* 51797ba62b2SMarco Elver * User provided data if sigtrap=1, passed back to user via 5180683b531SEric W. Biederman * siginfo_t::si_perf_data, e.g. to permit user to identify the event. 519ddecd228SMarco Elver * Note, siginfo_t::si_perf_data is long-sized, and sig_data will be 520ddecd228SMarco Elver * truncated accordingly on 32 bit architectures. 52197ba62b2SMarco Elver */ 52297ba62b2SMarco Elver __u64 sig_data; 52309519ec3SRob Herring 52409519ec3SRob Herring __u64 config3; /* extension of config2 */ 525607ca46eSDavid Howells }; 526607ca46eSDavid Howells 527f371b304SYonghong Song /* 528f371b304SYonghong Song * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 529f371b304SYonghong Song * to query bpf programs attached to the same perf tracepoint 530f371b304SYonghong Song * as the given perf event. 531f371b304SYonghong Song */ 532f371b304SYonghong Song struct perf_event_query_bpf { 533f371b304SYonghong Song /* 534f371b304SYonghong Song * The below ids array length 535f371b304SYonghong Song */ 536f371b304SYonghong Song __u32 ids_len; 537f371b304SYonghong Song /* 538f371b304SYonghong Song * Set by the kernel to indicate the number of 539f371b304SYonghong Song * available programs 540f371b304SYonghong Song */ 541f371b304SYonghong Song __u32 prog_cnt; 542f371b304SYonghong Song /* 543f371b304SYonghong Song * User provided buffer to store program ids 544f371b304SYonghong Song */ 54594dfc73eSGustavo A. R. Silva __u32 ids[]; 546f371b304SYonghong Song }; 547f371b304SYonghong Song 548607ca46eSDavid Howells /* 549607ca46eSDavid Howells * Ioctls that can be done on a perf event fd: 550607ca46eSDavid Howells */ 551607ca46eSDavid Howells #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 552607ca46eSDavid Howells #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 553607ca46eSDavid Howells #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 554607ca46eSDavid Howells #define PERF_EVENT_IOC_RESET _IO ('$', 3) 555607ca46eSDavid Howells #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 556607ca46eSDavid Howells #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 557607ca46eSDavid Howells #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 558a8e0108cSVince Weaver #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 5592541517cSAlexei Starovoitov #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 56086e7972fSWang Nan #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 561f371b304SYonghong Song #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 56232ff77e8SMilind Chabbi #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 563607ca46eSDavid Howells 564607ca46eSDavid Howells enum perf_event_ioc_flags { 565607ca46eSDavid Howells PERF_IOC_FLAG_GROUP = 1U << 0, 566607ca46eSDavid Howells }; 567607ca46eSDavid Howells 568607ca46eSDavid Howells /* 569607ca46eSDavid Howells * Structure of the page that can be mapped via mmap 570607ca46eSDavid Howells */ 571607ca46eSDavid Howells struct perf_event_mmap_page { 572607ca46eSDavid Howells __u32 version; /* version number of this structure */ 573607ca46eSDavid Howells __u32 compat_version; /* lowest version this is compat with */ 574607ca46eSDavid Howells 575607ca46eSDavid Howells /* 576607ca46eSDavid Howells * Bits needed to read the hw events in user-space. 577607ca46eSDavid Howells * 578b438b1abSAndy Lutomirski * u32 seq, time_mult, time_shift, index, width; 579607ca46eSDavid Howells * u64 count, enabled, running; 580607ca46eSDavid Howells * u64 cyc, time_offset; 581607ca46eSDavid Howells * s64 pmc = 0; 582607ca46eSDavid Howells * 583607ca46eSDavid Howells * do { 584607ca46eSDavid Howells * seq = pc->lock; 585607ca46eSDavid Howells * barrier() 586607ca46eSDavid Howells * 587607ca46eSDavid Howells * enabled = pc->time_enabled; 588607ca46eSDavid Howells * running = pc->time_running; 589607ca46eSDavid Howells * 590607ca46eSDavid Howells * if (pc->cap_usr_time && enabled != running) { 591607ca46eSDavid Howells * cyc = rdtsc(); 592607ca46eSDavid Howells * time_offset = pc->time_offset; 593607ca46eSDavid Howells * time_mult = pc->time_mult; 594607ca46eSDavid Howells * time_shift = pc->time_shift; 595607ca46eSDavid Howells * } 596607ca46eSDavid Howells * 597b438b1abSAndy Lutomirski * index = pc->index; 598607ca46eSDavid Howells * count = pc->offset; 599b438b1abSAndy Lutomirski * if (pc->cap_user_rdpmc && index) { 600607ca46eSDavid Howells * width = pc->pmc_width; 601b438b1abSAndy Lutomirski * pmc = rdpmc(index - 1); 602607ca46eSDavid Howells * } 603607ca46eSDavid Howells * 604607ca46eSDavid Howells * barrier(); 605607ca46eSDavid Howells * } while (pc->lock != seq); 606607ca46eSDavid Howells * 607607ca46eSDavid Howells * NOTE: for obvious reason this only works on self-monitoring 608607ca46eSDavid Howells * processes. 609607ca46eSDavid Howells */ 610607ca46eSDavid Howells __u32 lock; /* seqlock for synchronization */ 611607ca46eSDavid Howells __u32 index; /* hardware event identifier */ 612607ca46eSDavid Howells __s64 offset; /* add to hardware event value */ 613607ca46eSDavid Howells __u64 time_enabled; /* time event active */ 614607ca46eSDavid Howells __u64 time_running; /* time event on cpu */ 615607ca46eSDavid Howells union { 616607ca46eSDavid Howells __u64 capabilities; 617860f085bSAdrian Hunter struct { 618fa731587SPeter Zijlstra __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 619fa731587SPeter Zijlstra cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 620fa731587SPeter Zijlstra 621fa731587SPeter Zijlstra cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 6226c0246a4SPeter Zijlstra cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */ 623fa731587SPeter Zijlstra cap_user_time_zero : 1, /* The time_zero field is used */ 6246c0246a4SPeter Zijlstra cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */ 6256c0246a4SPeter Zijlstra cap_____res : 58; 626607ca46eSDavid Howells }; 627860f085bSAdrian Hunter }; 628607ca46eSDavid Howells 629607ca46eSDavid Howells /* 630b438b1abSAndy Lutomirski * If cap_user_rdpmc this field provides the bit-width of the value 631607ca46eSDavid Howells * read using the rdpmc() or equivalent instruction. This can be used 632607ca46eSDavid Howells * to sign extend the result like: 633607ca46eSDavid Howells * 634607ca46eSDavid Howells * pmc <<= 64 - width; 635607ca46eSDavid Howells * pmc >>= 64 - width; // signed shift right 636607ca46eSDavid Howells * count += pmc; 637607ca46eSDavid Howells */ 638607ca46eSDavid Howells __u16 pmc_width; 639607ca46eSDavid Howells 640607ca46eSDavid Howells /* 641607ca46eSDavid Howells * If cap_usr_time the below fields can be used to compute the time 642607ca46eSDavid Howells * delta since time_enabled (in ns) using rdtsc or similar. 643607ca46eSDavid Howells * 644607ca46eSDavid Howells * u64 quot, rem; 645607ca46eSDavid Howells * u64 delta; 646607ca46eSDavid Howells * 647607ca46eSDavid Howells * quot = (cyc >> time_shift); 648b9511cd7SAdrian Hunter * rem = cyc & (((u64)1 << time_shift) - 1); 649607ca46eSDavid Howells * delta = time_offset + quot * time_mult + 650607ca46eSDavid Howells * ((rem * time_mult) >> time_shift); 651607ca46eSDavid Howells * 652607ca46eSDavid Howells * Where time_offset,time_mult,time_shift and cyc are read in the 653607ca46eSDavid Howells * seqcount loop described above. This delta can then be added to 654b438b1abSAndy Lutomirski * enabled and possible running (if index), improving the scaling: 655607ca46eSDavid Howells * 656607ca46eSDavid Howells * enabled += delta; 657b438b1abSAndy Lutomirski * if (index) 658607ca46eSDavid Howells * running += delta; 659607ca46eSDavid Howells * 660607ca46eSDavid Howells * quot = count / running; 661607ca46eSDavid Howells * rem = count % running; 662607ca46eSDavid Howells * count = quot * enabled + (rem * enabled) / running; 663607ca46eSDavid Howells */ 664607ca46eSDavid Howells __u16 time_shift; 665607ca46eSDavid Howells __u32 time_mult; 666607ca46eSDavid Howells __u64 time_offset; 667c73deb6aSAdrian Hunter /* 668c73deb6aSAdrian Hunter * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 669c73deb6aSAdrian Hunter * from sample timestamps. 670c73deb6aSAdrian Hunter * 671c73deb6aSAdrian Hunter * time = timestamp - time_zero; 672c73deb6aSAdrian Hunter * quot = time / time_mult; 673c73deb6aSAdrian Hunter * rem = time % time_mult; 674c73deb6aSAdrian Hunter * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 675c73deb6aSAdrian Hunter * 676c73deb6aSAdrian Hunter * And vice versa: 677c73deb6aSAdrian Hunter * 678c73deb6aSAdrian Hunter * quot = cyc >> time_shift; 679b9511cd7SAdrian Hunter * rem = cyc & (((u64)1 << time_shift) - 1); 680c73deb6aSAdrian Hunter * timestamp = time_zero + quot * time_mult + 681c73deb6aSAdrian Hunter * ((rem * time_mult) >> time_shift); 682c73deb6aSAdrian Hunter */ 683c73deb6aSAdrian Hunter __u64 time_zero; 6846c0246a4SPeter Zijlstra 685fa731587SPeter Zijlstra __u32 size; /* Header size up to __reserved[] fields. */ 6866c0246a4SPeter Zijlstra __u32 __reserved_1; 6876c0246a4SPeter Zijlstra 6886c0246a4SPeter Zijlstra /* 6896c0246a4SPeter Zijlstra * If cap_usr_time_short, the hardware clock is less than 64bit wide 6906c0246a4SPeter Zijlstra * and we must compute the 'cyc' value, as used by cap_usr_time, as: 6916c0246a4SPeter Zijlstra * 6926c0246a4SPeter Zijlstra * cyc = time_cycles + ((cyc - time_cycles) & time_mask) 6936c0246a4SPeter Zijlstra * 6946c0246a4SPeter Zijlstra * NOTE: this form is explicitly chosen such that cap_usr_time_short 6956c0246a4SPeter Zijlstra * is a correction on top of cap_usr_time, and code that doesn't 6966c0246a4SPeter Zijlstra * know about cap_usr_time_short still works under the assumption 6976c0246a4SPeter Zijlstra * the counter doesn't wrap. 6986c0246a4SPeter Zijlstra */ 6996c0246a4SPeter Zijlstra __u64 time_cycles; 7006c0246a4SPeter Zijlstra __u64 time_mask; 701607ca46eSDavid Howells 702607ca46eSDavid Howells /* 703607ca46eSDavid Howells * Hole for extension of the self monitor capabilities 704607ca46eSDavid Howells */ 705607ca46eSDavid Howells 7066c0246a4SPeter Zijlstra __u8 __reserved[116*8]; /* align to 1k. */ 707607ca46eSDavid Howells 708607ca46eSDavid Howells /* 709607ca46eSDavid Howells * Control data for the mmap() data buffer. 710607ca46eSDavid Howells * 711bf378d34SPeter Zijlstra * User-space reading the @data_head value should issue an smp_rmb(), 712bf378d34SPeter Zijlstra * after reading this value. 713607ca46eSDavid Howells * 714607ca46eSDavid Howells * When the mapping is PROT_WRITE the @data_tail value should be 715bf378d34SPeter Zijlstra * written by userspace to reflect the last read data, after issueing 716bf378d34SPeter Zijlstra * an smp_mb() to separate the data read from the ->data_tail store. 717bf378d34SPeter Zijlstra * In this case the kernel will not over-write unread data. 718bf378d34SPeter Zijlstra * 719bf378d34SPeter Zijlstra * See perf_output_put_handle() for the data ordering. 720e8c6deacSAlexander Shishkin * 721e8c6deacSAlexander Shishkin * data_{offset,size} indicate the location and size of the perf record 722e8c6deacSAlexander Shishkin * buffer within the mmapped area. 723607ca46eSDavid Howells */ 724607ca46eSDavid Howells __u64 data_head; /* head in the data section */ 725607ca46eSDavid Howells __u64 data_tail; /* user-space written tail */ 726e8c6deacSAlexander Shishkin __u64 data_offset; /* where the buffer starts */ 727e8c6deacSAlexander Shishkin __u64 data_size; /* data buffer size */ 72845bfb2e5SPeter Zijlstra 72945bfb2e5SPeter Zijlstra /* 73045bfb2e5SPeter Zijlstra * AUX area is defined by aux_{offset,size} fields that should be set 73145bfb2e5SPeter Zijlstra * by the userspace, so that 73245bfb2e5SPeter Zijlstra * 73345bfb2e5SPeter Zijlstra * aux_offset >= data_offset + data_size 73445bfb2e5SPeter Zijlstra * 73545bfb2e5SPeter Zijlstra * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 73645bfb2e5SPeter Zijlstra * 73745bfb2e5SPeter Zijlstra * Ring buffer pointers aux_{head,tail} have the same semantics as 73845bfb2e5SPeter Zijlstra * data_{head,tail} and same ordering rules apply. 73945bfb2e5SPeter Zijlstra */ 74045bfb2e5SPeter Zijlstra __u64 aux_head; 74145bfb2e5SPeter Zijlstra __u64 aux_tail; 74245bfb2e5SPeter Zijlstra __u64 aux_offset; 74345bfb2e5SPeter Zijlstra __u64 aux_size; 744607ca46eSDavid Howells }; 745607ca46eSDavid Howells 74688a16a13SJiri Olsa /* 74788a16a13SJiri Olsa * The current state of perf_event_header::misc bits usage: 74888a16a13SJiri Olsa * ('|' used bit, '-' unused bit) 74988a16a13SJiri Olsa * 75088a16a13SJiri Olsa * 012 CDEF 75188a16a13SJiri Olsa * |||---------|||| 75288a16a13SJiri Olsa * 75388a16a13SJiri Olsa * Where: 75488a16a13SJiri Olsa * 0-2 CPUMODE_MASK 75588a16a13SJiri Olsa * 75688a16a13SJiri Olsa * C PROC_MAP_PARSE_TIMEOUT 75788a16a13SJiri Olsa * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT 75888a16a13SJiri Olsa * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT 75988a16a13SJiri Olsa * F (reserved) 76088a16a13SJiri Olsa */ 76188a16a13SJiri Olsa 762607ca46eSDavid Howells #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 763607ca46eSDavid Howells #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 764607ca46eSDavid Howells #define PERF_RECORD_MISC_KERNEL (1 << 0) 765607ca46eSDavid Howells #define PERF_RECORD_MISC_USER (2 << 0) 766607ca46eSDavid Howells #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 767607ca46eSDavid Howells #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 768607ca46eSDavid Howells #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 769607ca46eSDavid Howells 77082b89778SAdrian Hunter /* 771930e6fcdSKan Liang * Indicates that /proc/PID/maps parsing are truncated by time out. 772930e6fcdSKan Liang */ 773930e6fcdSKan Liang #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 774930e6fcdSKan Liang /* 775972c1488SJiri Olsa * Following PERF_RECORD_MISC_* are used on different 776972c1488SJiri Olsa * events, so can reuse the same bit position: 777972c1488SJiri Olsa * 778972c1488SJiri Olsa * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 779972c1488SJiri Olsa * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 7804f8f382eSDavid Miller * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 781972c1488SJiri Olsa * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 78282b89778SAdrian Hunter */ 7832fe85427SStephane Eranian #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 78482b89778SAdrian Hunter #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 7854f8f382eSDavid Miller #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 78645ac1403SAdrian Hunter #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 787607ca46eSDavid Howells /* 788101592b4SAlexey Budankov * These PERF_RECORD_MISC_* flags below are safely reused 789101592b4SAlexey Budankov * for the following events: 790101592b4SAlexey Budankov * 791101592b4SAlexey Budankov * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 792101592b4SAlexey Budankov * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 79388a16a13SJiri Olsa * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event 794101592b4SAlexey Budankov * 795101592b4SAlexey Budankov * 796101592b4SAlexey Budankov * PERF_RECORD_MISC_EXACT_IP: 797607ca46eSDavid Howells * Indicates that the content of PERF_SAMPLE_IP points to 798607ca46eSDavid Howells * the actual instruction that triggered the event. See also 799607ca46eSDavid Howells * perf_event_attr::precise_ip. 800101592b4SAlexey Budankov * 801101592b4SAlexey Budankov * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 802101592b4SAlexey Budankov * Indicates that thread was preempted in TASK_RUNNING state. 80388a16a13SJiri Olsa * 80488a16a13SJiri Olsa * PERF_RECORD_MISC_MMAP_BUILD_ID: 80588a16a13SJiri Olsa * Indicates that mmap2 event carries build id data. 806607ca46eSDavid Howells */ 807607ca46eSDavid Howells #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 808101592b4SAlexey Budankov #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 80988a16a13SJiri Olsa #define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) 810607ca46eSDavid Howells /* 811607ca46eSDavid Howells * Reserve the last bit to indicate some extended misc field 812607ca46eSDavid Howells */ 813607ca46eSDavid Howells #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 814607ca46eSDavid Howells 815607ca46eSDavid Howells struct perf_event_header { 816607ca46eSDavid Howells __u32 type; 817607ca46eSDavid Howells __u16 misc; 818607ca46eSDavid Howells __u16 size; 819607ca46eSDavid Howells }; 820607ca46eSDavid Howells 821e4222673SHari Bathini struct perf_ns_link_info { 822e4222673SHari Bathini __u64 dev; 823e4222673SHari Bathini __u64 ino; 824e4222673SHari Bathini }; 825e4222673SHari Bathini 826e4222673SHari Bathini enum { 827e4222673SHari Bathini NET_NS_INDEX = 0, 828e4222673SHari Bathini UTS_NS_INDEX = 1, 829e4222673SHari Bathini IPC_NS_INDEX = 2, 830e4222673SHari Bathini PID_NS_INDEX = 3, 831e4222673SHari Bathini USER_NS_INDEX = 4, 832e4222673SHari Bathini MNT_NS_INDEX = 5, 833e4222673SHari Bathini CGROUP_NS_INDEX = 6, 834e4222673SHari Bathini 835e4222673SHari Bathini NR_NAMESPACES, /* number of available namespaces */ 836e4222673SHari Bathini }; 837e4222673SHari Bathini 838607ca46eSDavid Howells enum perf_event_type { 839607ca46eSDavid Howells 840607ca46eSDavid Howells /* 841607ca46eSDavid Howells * If perf_event_attr.sample_id_all is set then all event types will 842607ca46eSDavid Howells * have the sample_type selected fields related to where/when 843ff3d527cSAdrian Hunter * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 844ff3d527cSAdrian Hunter * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 845ff3d527cSAdrian Hunter * just after the perf_event_header and the fields already present for 846ff3d527cSAdrian Hunter * the existing fields, i.e. at the end of the payload. That way a newer 847ff3d527cSAdrian Hunter * perf.data file will be supported by older perf tools, with these new 848ff3d527cSAdrian Hunter * optional fields being ignored. 849607ca46eSDavid Howells * 850a5cdd40cSPeter Zijlstra * struct sample_id { 851a5cdd40cSPeter Zijlstra * { u32 pid, tid; } && PERF_SAMPLE_TID 852a5cdd40cSPeter Zijlstra * { u64 time; } && PERF_SAMPLE_TIME 853a5cdd40cSPeter Zijlstra * { u64 id; } && PERF_SAMPLE_ID 854a5cdd40cSPeter Zijlstra * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 855a5cdd40cSPeter Zijlstra * { u32 cpu, res; } && PERF_SAMPLE_CPU 856ff3d527cSAdrian Hunter * { u64 id; } && PERF_SAMPLE_IDENTIFIER 857a5cdd40cSPeter Zijlstra * } && perf_event_attr::sample_id_all 858ff3d527cSAdrian Hunter * 859ff3d527cSAdrian Hunter * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 860ff3d527cSAdrian Hunter * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 861ff3d527cSAdrian Hunter * relative to header.size. 862a5cdd40cSPeter Zijlstra */ 863a5cdd40cSPeter Zijlstra 864a5cdd40cSPeter Zijlstra /* 865607ca46eSDavid Howells * The MMAP events record the PROT_EXEC mappings so that we can 866607ca46eSDavid Howells * correlate userspace IPs to code. They have the following structure: 867607ca46eSDavid Howells * 868607ca46eSDavid Howells * struct { 869607ca46eSDavid Howells * struct perf_event_header header; 870607ca46eSDavid Howells * 871607ca46eSDavid Howells * u32 pid, tid; 872607ca46eSDavid Howells * u64 addr; 873607ca46eSDavid Howells * u64 len; 874607ca46eSDavid Howells * u64 pgoff; 875607ca46eSDavid Howells * char filename[]; 876c5ecceefSPeter Zijlstra * struct sample_id sample_id; 877607ca46eSDavid Howells * }; 878607ca46eSDavid Howells */ 879607ca46eSDavid Howells PERF_RECORD_MMAP = 1, 880607ca46eSDavid Howells 881607ca46eSDavid Howells /* 882607ca46eSDavid Howells * struct { 883607ca46eSDavid Howells * struct perf_event_header header; 884607ca46eSDavid Howells * u64 id; 885607ca46eSDavid Howells * u64 lost; 886a5cdd40cSPeter Zijlstra * struct sample_id sample_id; 887607ca46eSDavid Howells * }; 888607ca46eSDavid Howells */ 889607ca46eSDavid Howells PERF_RECORD_LOST = 2, 890607ca46eSDavid Howells 891607ca46eSDavid Howells /* 892607ca46eSDavid Howells * struct { 893607ca46eSDavid Howells * struct perf_event_header header; 894607ca46eSDavid Howells * 895607ca46eSDavid Howells * u32 pid, tid; 896607ca46eSDavid Howells * char comm[]; 897a5cdd40cSPeter Zijlstra * struct sample_id sample_id; 898607ca46eSDavid Howells * }; 899607ca46eSDavid Howells */ 900607ca46eSDavid Howells PERF_RECORD_COMM = 3, 901607ca46eSDavid Howells 902607ca46eSDavid Howells /* 903607ca46eSDavid Howells * struct { 904607ca46eSDavid Howells * struct perf_event_header header; 905607ca46eSDavid Howells * u32 pid, ppid; 906607ca46eSDavid Howells * u32 tid, ptid; 907607ca46eSDavid Howells * u64 time; 908a5cdd40cSPeter Zijlstra * struct sample_id sample_id; 909607ca46eSDavid Howells * }; 910607ca46eSDavid Howells */ 911607ca46eSDavid Howells PERF_RECORD_EXIT = 4, 912607ca46eSDavid Howells 913607ca46eSDavid Howells /* 914607ca46eSDavid Howells * struct { 915607ca46eSDavid Howells * struct perf_event_header header; 916607ca46eSDavid Howells * u64 time; 917607ca46eSDavid Howells * u64 id; 918607ca46eSDavid Howells * u64 stream_id; 919a5cdd40cSPeter Zijlstra * struct sample_id sample_id; 920607ca46eSDavid Howells * }; 921607ca46eSDavid Howells */ 922607ca46eSDavid Howells PERF_RECORD_THROTTLE = 5, 923607ca46eSDavid Howells PERF_RECORD_UNTHROTTLE = 6, 924607ca46eSDavid Howells 925607ca46eSDavid Howells /* 926607ca46eSDavid Howells * struct { 927607ca46eSDavid Howells * struct perf_event_header header; 928607ca46eSDavid Howells * u32 pid, ppid; 929607ca46eSDavid Howells * u32 tid, ptid; 930607ca46eSDavid Howells * u64 time; 931a5cdd40cSPeter Zijlstra * struct sample_id sample_id; 932607ca46eSDavid Howells * }; 933607ca46eSDavid Howells */ 934607ca46eSDavid Howells PERF_RECORD_FORK = 7, 935607ca46eSDavid Howells 936607ca46eSDavid Howells /* 937607ca46eSDavid Howells * struct { 938607ca46eSDavid Howells * struct perf_event_header header; 939607ca46eSDavid Howells * u32 pid, tid; 940607ca46eSDavid Howells * 941607ca46eSDavid Howells * struct read_format values; 942a5cdd40cSPeter Zijlstra * struct sample_id sample_id; 943607ca46eSDavid Howells * }; 944607ca46eSDavid Howells */ 945607ca46eSDavid Howells PERF_RECORD_READ = 8, 946607ca46eSDavid Howells 947607ca46eSDavid Howells /* 948607ca46eSDavid Howells * struct { 949607ca46eSDavid Howells * struct perf_event_header header; 950607ca46eSDavid Howells * 951ff3d527cSAdrian Hunter * # 952ff3d527cSAdrian Hunter * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 953ff3d527cSAdrian Hunter * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 954ff3d527cSAdrian Hunter * # is fixed relative to header. 955ff3d527cSAdrian Hunter * # 956ff3d527cSAdrian Hunter * 957ff3d527cSAdrian Hunter * { u64 id; } && PERF_SAMPLE_IDENTIFIER 958607ca46eSDavid Howells * { u64 ip; } && PERF_SAMPLE_IP 959607ca46eSDavid Howells * { u32 pid, tid; } && PERF_SAMPLE_TID 960607ca46eSDavid Howells * { u64 time; } && PERF_SAMPLE_TIME 961607ca46eSDavid Howells * { u64 addr; } && PERF_SAMPLE_ADDR 962607ca46eSDavid Howells * { u64 id; } && PERF_SAMPLE_ID 963607ca46eSDavid Howells * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 964607ca46eSDavid Howells * { u32 cpu, res; } && PERF_SAMPLE_CPU 965607ca46eSDavid Howells * { u64 period; } && PERF_SAMPLE_PERIOD 966607ca46eSDavid Howells * 967607ca46eSDavid Howells * { struct read_format values; } && PERF_SAMPLE_READ 968607ca46eSDavid Howells * 969607ca46eSDavid Howells * { u64 nr, 970607ca46eSDavid Howells * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 971607ca46eSDavid Howells * 972607ca46eSDavid Howells * # 973607ca46eSDavid Howells * # The RAW record below is opaque data wrt the ABI 974607ca46eSDavid Howells * # 975607ca46eSDavid Howells * # That is, the ABI doesn't make any promises wrt to 976607ca46eSDavid Howells * # the stability of its content, it may vary depending 977607ca46eSDavid Howells * # on event, hardware, kernel version and phase of 978607ca46eSDavid Howells * # the moon. 979607ca46eSDavid Howells * # 980607ca46eSDavid Howells * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 981607ca46eSDavid Howells * # 982607ca46eSDavid Howells * 983607ca46eSDavid Howells * { u32 size; 984607ca46eSDavid Howells * char data[size];}&& PERF_SAMPLE_RAW 985607ca46eSDavid Howells * 986b878e7fbSVince Weaver * { u64 nr; 987bbfd5e4fSKan Liang * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 988bbfd5e4fSKan Liang * { u64 from, to, flags } lbr[nr]; 989571d91dcSKan Liang * # 990571d91dcSKan Liang * # The format of the counters is decided by the 991571d91dcSKan Liang * # "branch_counter_nr" and "branch_counter_width", 992571d91dcSKan Liang * # which are defined in the ABI. 993571d91dcSKan Liang * # 994571d91dcSKan Liang * { u64 counters; } cntr[nr] && PERF_SAMPLE_BRANCH_COUNTERS 995bbfd5e4fSKan Liang * } && PERF_SAMPLE_BRANCH_STACK 996607ca46eSDavid Howells * 997607ca46eSDavid Howells * { u64 abi; # enum perf_sample_regs_abi 998607ca46eSDavid Howells * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 999607ca46eSDavid Howells * 1000607ca46eSDavid Howells * { u64 size; 1001607ca46eSDavid Howells * char data[size]; 1002607ca46eSDavid Howells * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 1003c3feedf2SAndi Kleen * 10042a6c6b7dSKan Liang * { union perf_sample_weight 10052a6c6b7dSKan Liang * { 10062a6c6b7dSKan Liang * u64 full; && PERF_SAMPLE_WEIGHT 10072a6c6b7dSKan Liang * #if defined(__LITTLE_ENDIAN_BITFIELD) 10082a6c6b7dSKan Liang * struct { 10092a6c6b7dSKan Liang * u32 var1_dw; 10102a6c6b7dSKan Liang * u16 var2_w; 10112a6c6b7dSKan Liang * u16 var3_w; 10122a6c6b7dSKan Liang * } && PERF_SAMPLE_WEIGHT_STRUCT 10132a6c6b7dSKan Liang * #elif defined(__BIG_ENDIAN_BITFIELD) 10142a6c6b7dSKan Liang * struct { 10152a6c6b7dSKan Liang * u16 var3_w; 10162a6c6b7dSKan Liang * u16 var2_w; 10172a6c6b7dSKan Liang * u32 var1_dw; 10182a6c6b7dSKan Liang * } && PERF_SAMPLE_WEIGHT_STRUCT 10192a6c6b7dSKan Liang * #endif 10202a6c6b7dSKan Liang * } 10212a6c6b7dSKan Liang * } 1022d6be9ad6SStephane Eranian * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 1023189b84fbSVince Weaver * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 102460e2364eSStephane Eranian * { u64 abi; # enum perf_sample_regs_abi 102560e2364eSStephane Eranian * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 1026fc7ce9c7SKan Liang * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 1027a4faf00dSAlexander Shishkin * { u64 size; 1028a4faf00dSAlexander Shishkin * char data[size]; } && PERF_SAMPLE_AUX 10298d97e718SKan Liang * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE 1030995f088eSStephane Eranian * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE 1031607ca46eSDavid Howells * }; 1032607ca46eSDavid Howells */ 1033607ca46eSDavid Howells PERF_RECORD_SAMPLE = 9, 1034607ca46eSDavid Howells 103513d7a241SStephane Eranian /* 103613d7a241SStephane Eranian * The MMAP2 records are an augmented version of MMAP, they add 103713d7a241SStephane Eranian * maj, min, ino numbers to be used to uniquely identify each mapping 103813d7a241SStephane Eranian * 103913d7a241SStephane Eranian * struct { 104013d7a241SStephane Eranian * struct perf_event_header header; 104113d7a241SStephane Eranian * 104213d7a241SStephane Eranian * u32 pid, tid; 104313d7a241SStephane Eranian * u64 addr; 104413d7a241SStephane Eranian * u64 len; 104513d7a241SStephane Eranian * u64 pgoff; 104688a16a13SJiri Olsa * union { 104788a16a13SJiri Olsa * struct { 104813d7a241SStephane Eranian * u32 maj; 104913d7a241SStephane Eranian * u32 min; 105013d7a241SStephane Eranian * u64 ino; 105113d7a241SStephane Eranian * u64 ino_generation; 105288a16a13SJiri Olsa * }; 105388a16a13SJiri Olsa * struct { 105488a16a13SJiri Olsa * u8 build_id_size; 105588a16a13SJiri Olsa * u8 __reserved_1; 105688a16a13SJiri Olsa * u16 __reserved_2; 105788a16a13SJiri Olsa * u8 build_id[20]; 105888a16a13SJiri Olsa * }; 105988a16a13SJiri Olsa * }; 1060f972eb63SPeter Zijlstra * u32 prot, flags; 106113d7a241SStephane Eranian * char filename[]; 106213d7a241SStephane Eranian * struct sample_id sample_id; 106313d7a241SStephane Eranian * }; 106413d7a241SStephane Eranian */ 106513d7a241SStephane Eranian PERF_RECORD_MMAP2 = 10, 106613d7a241SStephane Eranian 106768db7e98SAlexander Shishkin /* 106868db7e98SAlexander Shishkin * Records that new data landed in the AUX buffer part. 106968db7e98SAlexander Shishkin * 107068db7e98SAlexander Shishkin * struct { 107168db7e98SAlexander Shishkin * struct perf_event_header header; 107268db7e98SAlexander Shishkin * 107368db7e98SAlexander Shishkin * u64 aux_offset; 107468db7e98SAlexander Shishkin * u64 aux_size; 107568db7e98SAlexander Shishkin * u64 flags; 107668db7e98SAlexander Shishkin * struct sample_id sample_id; 107768db7e98SAlexander Shishkin * }; 107868db7e98SAlexander Shishkin */ 107968db7e98SAlexander Shishkin PERF_RECORD_AUX = 11, 108068db7e98SAlexander Shishkin 1081ec0d7729SAlexander Shishkin /* 1082ec0d7729SAlexander Shishkin * Indicates that instruction trace has started 1083ec0d7729SAlexander Shishkin * 1084ec0d7729SAlexander Shishkin * struct { 1085ec0d7729SAlexander Shishkin * struct perf_event_header header; 1086ec0d7729SAlexander Shishkin * u32 pid; 1087ec0d7729SAlexander Shishkin * u32 tid; 108881df978cSJiri Olsa * struct sample_id sample_id; 1089ec0d7729SAlexander Shishkin * }; 1090ec0d7729SAlexander Shishkin */ 1091ec0d7729SAlexander Shishkin PERF_RECORD_ITRACE_START = 12, 1092ec0d7729SAlexander Shishkin 1093f38b0dbbSKan Liang /* 1094f38b0dbbSKan Liang * Records the dropped/lost sample number. 1095f38b0dbbSKan Liang * 1096f38b0dbbSKan Liang * struct { 1097f38b0dbbSKan Liang * struct perf_event_header header; 1098f38b0dbbSKan Liang * 1099f38b0dbbSKan Liang * u64 lost; 1100f38b0dbbSKan Liang * struct sample_id sample_id; 1101f38b0dbbSKan Liang * }; 1102f38b0dbbSKan Liang */ 1103f38b0dbbSKan Liang PERF_RECORD_LOST_SAMPLES = 13, 1104f38b0dbbSKan Liang 110545ac1403SAdrian Hunter /* 110645ac1403SAdrian Hunter * Records a context switch in or out (flagged by 110745ac1403SAdrian Hunter * PERF_RECORD_MISC_SWITCH_OUT). See also 110845ac1403SAdrian Hunter * PERF_RECORD_SWITCH_CPU_WIDE. 110945ac1403SAdrian Hunter * 111045ac1403SAdrian Hunter * struct { 111145ac1403SAdrian Hunter * struct perf_event_header header; 111245ac1403SAdrian Hunter * struct sample_id sample_id; 111345ac1403SAdrian Hunter * }; 111445ac1403SAdrian Hunter */ 111545ac1403SAdrian Hunter PERF_RECORD_SWITCH = 14, 111645ac1403SAdrian Hunter 111745ac1403SAdrian Hunter /* 111845ac1403SAdrian Hunter * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 111945ac1403SAdrian Hunter * next_prev_tid that are the next (switching out) or previous 112045ac1403SAdrian Hunter * (switching in) pid/tid. 112145ac1403SAdrian Hunter * 112245ac1403SAdrian Hunter * struct { 112345ac1403SAdrian Hunter * struct perf_event_header header; 112445ac1403SAdrian Hunter * u32 next_prev_pid; 112545ac1403SAdrian Hunter * u32 next_prev_tid; 112645ac1403SAdrian Hunter * struct sample_id sample_id; 112745ac1403SAdrian Hunter * }; 112845ac1403SAdrian Hunter */ 112945ac1403SAdrian Hunter PERF_RECORD_SWITCH_CPU_WIDE = 15, 113045ac1403SAdrian Hunter 1131e4222673SHari Bathini /* 1132e4222673SHari Bathini * struct { 1133e4222673SHari Bathini * struct perf_event_header header; 1134e4222673SHari Bathini * u32 pid; 1135e4222673SHari Bathini * u32 tid; 1136e4222673SHari Bathini * u64 nr_namespaces; 1137e4222673SHari Bathini * { u64 dev, inode; } [nr_namespaces]; 1138e4222673SHari Bathini * struct sample_id sample_id; 1139e4222673SHari Bathini * }; 1140e4222673SHari Bathini */ 1141e4222673SHari Bathini PERF_RECORD_NAMESPACES = 16, 1142e4222673SHari Bathini 114376193a94SSong Liu /* 114476193a94SSong Liu * Record ksymbol register/unregister events: 114576193a94SSong Liu * 114676193a94SSong Liu * struct { 114776193a94SSong Liu * struct perf_event_header header; 114876193a94SSong Liu * u64 addr; 114976193a94SSong Liu * u32 len; 115076193a94SSong Liu * u16 ksym_type; 115176193a94SSong Liu * u16 flags; 115276193a94SSong Liu * char name[]; 115376193a94SSong Liu * struct sample_id sample_id; 115476193a94SSong Liu * }; 115576193a94SSong Liu */ 115676193a94SSong Liu PERF_RECORD_KSYMBOL = 17, 115776193a94SSong Liu 11586ee52e2aSSong Liu /* 11596ee52e2aSSong Liu * Record bpf events: 11606ee52e2aSSong Liu * enum perf_bpf_event_type { 11616ee52e2aSSong Liu * PERF_BPF_EVENT_UNKNOWN = 0, 11626ee52e2aSSong Liu * PERF_BPF_EVENT_PROG_LOAD = 1, 11636ee52e2aSSong Liu * PERF_BPF_EVENT_PROG_UNLOAD = 2, 11646ee52e2aSSong Liu * }; 11656ee52e2aSSong Liu * 11666ee52e2aSSong Liu * struct { 11676ee52e2aSSong Liu * struct perf_event_header header; 11686ee52e2aSSong Liu * u16 type; 11696ee52e2aSSong Liu * u16 flags; 11706ee52e2aSSong Liu * u32 id; 11716ee52e2aSSong Liu * u8 tag[BPF_TAG_SIZE]; 11726ee52e2aSSong Liu * struct sample_id sample_id; 11736ee52e2aSSong Liu * }; 11746ee52e2aSSong Liu */ 11756ee52e2aSSong Liu PERF_RECORD_BPF_EVENT = 18, 11766ee52e2aSSong Liu 117796aaab68SNamhyung Kim /* 117896aaab68SNamhyung Kim * struct { 117996aaab68SNamhyung Kim * struct perf_event_header header; 118096aaab68SNamhyung Kim * u64 id; 118196aaab68SNamhyung Kim * char path[]; 118296aaab68SNamhyung Kim * struct sample_id sample_id; 118396aaab68SNamhyung Kim * }; 118496aaab68SNamhyung Kim */ 118596aaab68SNamhyung Kim PERF_RECORD_CGROUP = 19, 118696aaab68SNamhyung Kim 1187e17d43b9SAdrian Hunter /* 1188e17d43b9SAdrian Hunter * Records changes to kernel text i.e. self-modified code. 'old_len' is 1189e17d43b9SAdrian Hunter * the number of old bytes, 'new_len' is the number of new bytes. Either 1190e17d43b9SAdrian Hunter * 'old_len' or 'new_len' may be zero to indicate, for example, the 1191e17d43b9SAdrian Hunter * addition or removal of a trampoline. 'bytes' contains the old bytes 1192e17d43b9SAdrian Hunter * followed immediately by the new bytes. 1193e17d43b9SAdrian Hunter * 1194e17d43b9SAdrian Hunter * struct { 1195e17d43b9SAdrian Hunter * struct perf_event_header header; 1196e17d43b9SAdrian Hunter * u64 addr; 1197e17d43b9SAdrian Hunter * u16 old_len; 1198e17d43b9SAdrian Hunter * u16 new_len; 1199e17d43b9SAdrian Hunter * u8 bytes[]; 1200e17d43b9SAdrian Hunter * struct sample_id sample_id; 1201e17d43b9SAdrian Hunter * }; 1202e17d43b9SAdrian Hunter */ 1203e17d43b9SAdrian Hunter PERF_RECORD_TEXT_POKE = 20, 1204e17d43b9SAdrian Hunter 12058b8ff8ccSAdrian Hunter /* 12068b8ff8ccSAdrian Hunter * Data written to the AUX area by hardware due to aux_output, may need 12078b8ff8ccSAdrian Hunter * to be matched to the event by an architecture-specific hardware ID. 12088b8ff8ccSAdrian Hunter * This records the hardware ID, but requires sample_id to provide the 12098b8ff8ccSAdrian Hunter * event ID. e.g. Intel PT uses this record to disambiguate PEBS-via-PT 12108b8ff8ccSAdrian Hunter * records from multiple events. 12118b8ff8ccSAdrian Hunter * 12128b8ff8ccSAdrian Hunter * struct { 12138b8ff8ccSAdrian Hunter * struct perf_event_header header; 12148b8ff8ccSAdrian Hunter * u64 hw_id; 12158b8ff8ccSAdrian Hunter * struct sample_id sample_id; 12168b8ff8ccSAdrian Hunter * }; 12178b8ff8ccSAdrian Hunter */ 12188b8ff8ccSAdrian Hunter PERF_RECORD_AUX_OUTPUT_HW_ID = 21, 12198b8ff8ccSAdrian Hunter 1220607ca46eSDavid Howells PERF_RECORD_MAX, /* non-ABI */ 1221607ca46eSDavid Howells }; 1222607ca46eSDavid Howells 122376193a94SSong Liu enum perf_record_ksymbol_type { 122476193a94SSong Liu PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 122576193a94SSong Liu PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 122669e49088SAdrian Hunter /* 122769e49088SAdrian Hunter * Out of line code such as kprobe-replaced instructions or optimized 1228dd9ddf46SAdrian Hunter * kprobes or ftrace trampolines. 122969e49088SAdrian Hunter */ 123069e49088SAdrian Hunter PERF_RECORD_KSYMBOL_TYPE_OOL = 2, 123176193a94SSong Liu PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 123276193a94SSong Liu }; 123376193a94SSong Liu 123476193a94SSong Liu #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 123576193a94SSong Liu 12366ee52e2aSSong Liu enum perf_bpf_event_type { 12376ee52e2aSSong Liu PERF_BPF_EVENT_UNKNOWN = 0, 12386ee52e2aSSong Liu PERF_BPF_EVENT_PROG_LOAD = 1, 12396ee52e2aSSong Liu PERF_BPF_EVENT_PROG_UNLOAD = 2, 12406ee52e2aSSong Liu PERF_BPF_EVENT_MAX, /* non-ABI */ 12416ee52e2aSSong Liu }; 12426ee52e2aSSong Liu 1243607ca46eSDavid Howells #define PERF_MAX_STACK_DEPTH 127 1244c85b0334SArnaldo Carvalho de Melo #define PERF_MAX_CONTEXTS_PER_STACK 8 1245607ca46eSDavid Howells 1246607ca46eSDavid Howells enum perf_callchain_context { 1247607ca46eSDavid Howells PERF_CONTEXT_HV = (__u64)-32, 1248607ca46eSDavid Howells PERF_CONTEXT_KERNEL = (__u64)-128, 1249607ca46eSDavid Howells PERF_CONTEXT_USER = (__u64)-512, 1250607ca46eSDavid Howells 1251607ca46eSDavid Howells PERF_CONTEXT_GUEST = (__u64)-2048, 1252607ca46eSDavid Howells PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1253607ca46eSDavid Howells PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1254607ca46eSDavid Howells 1255607ca46eSDavid Howells PERF_CONTEXT_MAX = (__u64)-4095, 1256607ca46eSDavid Howells }; 1257607ca46eSDavid Howells 125868db7e98SAlexander Shishkin /** 125968db7e98SAlexander Shishkin * PERF_RECORD_AUX::flags bits 126068db7e98SAlexander Shishkin */ 126168db7e98SAlexander Shishkin #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 12622023a0d2SAlexander Shishkin #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1263ae0c2d99SAlexander Shishkin #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1264085b3062SWill Deacon #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1265547b6098SSuzuki K Poulose #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ 126668db7e98SAlexander Shishkin 12677dde5176SSuzuki K Poulose /* CoreSight PMU AUX buffer formats */ 12687dde5176SSuzuki K Poulose #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ 12697dde5176SSuzuki K Poulose #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ 1270d6be9ad6SStephane Eranian 1271d6be9ad6SStephane Eranian #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1272d6be9ad6SStephane Eranian #define PERF_FLAG_FD_OUTPUT (1UL << 1) 1273d6be9ad6SStephane Eranian #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1274d6be9ad6SStephane Eranian #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1275d6be9ad6SStephane Eranian 12768c5073dbSSukadev Bhattiprolu #if defined(__LITTLE_ENDIAN_BITFIELD) 1277d6be9ad6SStephane Eranian union perf_mem_data_src { 1278d6be9ad6SStephane Eranian __u64 val; 1279d6be9ad6SStephane Eranian struct { 1280d6be9ad6SStephane Eranian __u64 mem_op:5, /* type of opcode */ 1281d6be9ad6SStephane Eranian mem_lvl:14, /* memory hierarchy level */ 1282d6be9ad6SStephane Eranian mem_snoop:5, /* snoop mode */ 1283d6be9ad6SStephane Eranian mem_lock:2, /* lock instr */ 1284d6be9ad6SStephane Eranian mem_dtlb:7, /* tlb access */ 12856ae5fa61SAndi Kleen mem_lvl_num:4, /* memory hierarchy level number */ 12866ae5fa61SAndi Kleen mem_remote:1, /* remote */ 12876ae5fa61SAndi Kleen mem_snoopx:2, /* snoop mode, ext */ 128861b985e3SKan Liang mem_blk:3, /* access blocked */ 1289fec9cc61SKajol Jain mem_hops:3, /* hop level */ 1290fec9cc61SKajol Jain mem_rsvd:18; 1291d6be9ad6SStephane Eranian }; 1292d6be9ad6SStephane Eranian }; 12938c5073dbSSukadev Bhattiprolu #elif defined(__BIG_ENDIAN_BITFIELD) 12948c5073dbSSukadev Bhattiprolu union perf_mem_data_src { 12958c5073dbSSukadev Bhattiprolu __u64 val; 12968c5073dbSSukadev Bhattiprolu struct { 1297fec9cc61SKajol Jain __u64 mem_rsvd:18, 1298fec9cc61SKajol Jain mem_hops:3, /* hop level */ 129961b985e3SKan Liang mem_blk:3, /* access blocked */ 13006ae5fa61SAndi Kleen mem_snoopx:2, /* snoop mode, ext */ 13016ae5fa61SAndi Kleen mem_remote:1, /* remote */ 13026ae5fa61SAndi Kleen mem_lvl_num:4, /* memory hierarchy level number */ 13038c5073dbSSukadev Bhattiprolu mem_dtlb:7, /* tlb access */ 13048c5073dbSSukadev Bhattiprolu mem_lock:2, /* lock instr */ 13058c5073dbSSukadev Bhattiprolu mem_snoop:5, /* snoop mode */ 13068c5073dbSSukadev Bhattiprolu mem_lvl:14, /* memory hierarchy level */ 13078c5073dbSSukadev Bhattiprolu mem_op:5; /* type of opcode */ 13088c5073dbSSukadev Bhattiprolu }; 13098c5073dbSSukadev Bhattiprolu }; 13108c5073dbSSukadev Bhattiprolu #else 13118c5073dbSSukadev Bhattiprolu #error "Unknown endianness" 13128c5073dbSSukadev Bhattiprolu #endif 1313d6be9ad6SStephane Eranian 1314d6be9ad6SStephane Eranian /* type of opcode (load/store/prefetch,code) */ 1315d6be9ad6SStephane Eranian #define PERF_MEM_OP_NA 0x01 /* not available */ 1316d6be9ad6SStephane Eranian #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1317d6be9ad6SStephane Eranian #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1318d6be9ad6SStephane Eranian #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1319d6be9ad6SStephane Eranian #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1320d6be9ad6SStephane Eranian #define PERF_MEM_OP_SHIFT 0 1321d6be9ad6SStephane Eranian 1322f4c6217fSKajol Jain /* 1323f4c6217fSKajol Jain * PERF_MEM_LVL_* namespace being depricated to some extent in the 1324f4c6217fSKajol Jain * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields. 1325f4c6217fSKajol Jain * Supporting this namespace inorder to not break defined ABIs. 1326f4c6217fSKajol Jain * 1327f4c6217fSKajol Jain * memory hierarchy (memory level, hit or miss) 1328f4c6217fSKajol Jain */ 1329d6be9ad6SStephane Eranian #define PERF_MEM_LVL_NA 0x01 /* not available */ 1330d6be9ad6SStephane Eranian #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1331d6be9ad6SStephane Eranian #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1332d6be9ad6SStephane Eranian #define PERF_MEM_LVL_L1 0x08 /* L1 */ 1333d6be9ad6SStephane Eranian #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1334cc2f5a8aSStephane Eranian #define PERF_MEM_LVL_L2 0x20 /* L2 */ 1335cc2f5a8aSStephane Eranian #define PERF_MEM_LVL_L3 0x40 /* L3 */ 1336d6be9ad6SStephane Eranian #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1337d6be9ad6SStephane Eranian #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1338d6be9ad6SStephane Eranian #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1339d6be9ad6SStephane Eranian #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1340d6be9ad6SStephane Eranian #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1341d6be9ad6SStephane Eranian #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1342d6be9ad6SStephane Eranian #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1343d6be9ad6SStephane Eranian #define PERF_MEM_LVL_SHIFT 5 1344d6be9ad6SStephane Eranian 13456ae5fa61SAndi Kleen #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 13466ae5fa61SAndi Kleen #define PERF_MEM_REMOTE_SHIFT 37 13476ae5fa61SAndi Kleen 13486ae5fa61SAndi Kleen #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 13496ae5fa61SAndi Kleen #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 13506ae5fa61SAndi Kleen #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 13516ae5fa61SAndi Kleen #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1352526fffabSRavi Bangoria /* 5-0x7 available */ 1353526fffabSRavi Bangoria #define PERF_MEM_LVLNUM_UNC 0x08 /* Uncached */ 1354cb6c18b5SRavi Bangoria #define PERF_MEM_LVLNUM_CXL 0x09 /* CXL */ 1355ee3e88dfSRavi Bangoria #define PERF_MEM_LVLNUM_IO 0x0a /* I/O */ 13566ae5fa61SAndi Kleen #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 13576ae5fa61SAndi Kleen #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 13586ae5fa61SAndi Kleen #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 13596ae5fa61SAndi Kleen #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 13606ae5fa61SAndi Kleen #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 13616ae5fa61SAndi Kleen 13626ae5fa61SAndi Kleen #define PERF_MEM_LVLNUM_SHIFT 33 13636ae5fa61SAndi Kleen 1364d6be9ad6SStephane Eranian /* snoop mode */ 1365d6be9ad6SStephane Eranian #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1366d6be9ad6SStephane Eranian #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1367d6be9ad6SStephane Eranian #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1368d6be9ad6SStephane Eranian #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1369d6be9ad6SStephane Eranian #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1370d6be9ad6SStephane Eranian #define PERF_MEM_SNOOP_SHIFT 19 1371d6be9ad6SStephane Eranian 13726ae5fa61SAndi Kleen #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1373cfef80baSRavi Bangoria #define PERF_MEM_SNOOPX_PEER 0x02 /* xfer from peer */ 1374f3d301c1SAl Grant #define PERF_MEM_SNOOPX_SHIFT 38 13756ae5fa61SAndi Kleen 1376d6be9ad6SStephane Eranian /* locked instruction */ 1377d6be9ad6SStephane Eranian #define PERF_MEM_LOCK_NA 0x01 /* not available */ 1378d6be9ad6SStephane Eranian #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1379d6be9ad6SStephane Eranian #define PERF_MEM_LOCK_SHIFT 24 1380d6be9ad6SStephane Eranian 1381d6be9ad6SStephane Eranian /* TLB access */ 1382d6be9ad6SStephane Eranian #define PERF_MEM_TLB_NA 0x01 /* not available */ 1383d6be9ad6SStephane Eranian #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1384d6be9ad6SStephane Eranian #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1385d6be9ad6SStephane Eranian #define PERF_MEM_TLB_L1 0x08 /* L1 */ 1386d6be9ad6SStephane Eranian #define PERF_MEM_TLB_L2 0x10 /* L2 */ 1387d6be9ad6SStephane Eranian #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1388d6be9ad6SStephane Eranian #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1389d6be9ad6SStephane Eranian #define PERF_MEM_TLB_SHIFT 26 1390d6be9ad6SStephane Eranian 139161b985e3SKan Liang /* Access blocked */ 139261b985e3SKan Liang #define PERF_MEM_BLK_NA 0x01 /* not available */ 139361b985e3SKan Liang #define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */ 139461b985e3SKan Liang #define PERF_MEM_BLK_ADDR 0x04 /* address conflict */ 139561b985e3SKan Liang #define PERF_MEM_BLK_SHIFT 40 139661b985e3SKan Liang 1397fec9cc61SKajol Jain /* hop level */ 1398fec9cc61SKajol Jain #define PERF_MEM_HOPS_0 0x01 /* remote core, same node */ 1399cb1c4abaSKajol Jain #define PERF_MEM_HOPS_1 0x02 /* remote node, same socket */ 1400cb1c4abaSKajol Jain #define PERF_MEM_HOPS_2 0x03 /* remote socket, same board */ 1401cb1c4abaSKajol Jain #define PERF_MEM_HOPS_3 0x04 /* remote board */ 1402cb1c4abaSKajol Jain /* 5-7 available */ 1403fec9cc61SKajol Jain #define PERF_MEM_HOPS_SHIFT 43 1404fec9cc61SKajol Jain 1405d6be9ad6SStephane Eranian #define PERF_MEM_S(a, s) \ 14060d9dfc23SMike Frysinger (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1407d6be9ad6SStephane Eranian 1408274481deSVince Weaver /* 1409274481deSVince Weaver * single taken branch record layout: 1410274481deSVince Weaver * 1411274481deSVince Weaver * from: source instruction (may not always be a branch insn) 1412274481deSVince Weaver * to: branch target 1413274481deSVince Weaver * mispred: branch target was mispredicted 1414274481deSVince Weaver * predicted: branch target was predicted 1415274481deSVince Weaver * 1416274481deSVince Weaver * support for mispred, predicted is optional. In case it 1417274481deSVince Weaver * is not supported mispred = predicted = 0. 1418274481deSVince Weaver * 1419274481deSVince Weaver * in_tx: running in a hardware transaction 1420274481deSVince Weaver * abort: aborting a hardware transaction 142171ef3c6bSAndi Kleen * cycles: cycles from last branch (or 0 if not supported) 1422eb0baf8aSJin Yao * type: branch type 142393315e46SSandipan Das * spec: branch speculation info (or 0 if not supported) 1424274481deSVince Weaver */ 1425274481deSVince Weaver struct perf_branch_entry { 1426274481deSVince Weaver __u64 from; 1427274481deSVince Weaver __u64 to; 1428274481deSVince Weaver __u64 mispred:1, /* target mispredicted */ 1429274481deSVince Weaver predicted:1,/* target predicted */ 1430274481deSVince Weaver in_tx:1, /* in transaction */ 1431274481deSVince Weaver abort:1, /* transaction abort */ 143271ef3c6bSAndi Kleen cycles:16, /* cycle count to last branch */ 1433eb0baf8aSJin Yao type:4, /* branch type */ 143493315e46SSandipan Das spec:2, /* branch speculation info */ 1435b190bc4aSAnshuman Khandual new_type:4, /* additional branch type */ 14365402d25aSAnshuman Khandual priv:3, /* privilege level */ 14375402d25aSAnshuman Khandual reserved:31; 1438274481deSVince Weaver }; 1439274481deSVince Weaver 1440*33744916SKan Liang /* Size of used info bits in struct perf_branch_entry */ 1441*33744916SKan Liang #define PERF_BRANCH_ENTRY_INFO_BITS_MAX 33 1442*33744916SKan Liang 14432a6c6b7dSKan Liang union perf_sample_weight { 14442a6c6b7dSKan Liang __u64 full; 14452a6c6b7dSKan Liang #if defined(__LITTLE_ENDIAN_BITFIELD) 14462a6c6b7dSKan Liang struct { 14472a6c6b7dSKan Liang __u32 var1_dw; 14482a6c6b7dSKan Liang __u16 var2_w; 14492a6c6b7dSKan Liang __u16 var3_w; 14502a6c6b7dSKan Liang }; 14512a6c6b7dSKan Liang #elif defined(__BIG_ENDIAN_BITFIELD) 14522a6c6b7dSKan Liang struct { 14532a6c6b7dSKan Liang __u16 var3_w; 14542a6c6b7dSKan Liang __u16 var2_w; 14552a6c6b7dSKan Liang __u32 var1_dw; 14562a6c6b7dSKan Liang }; 14572a6c6b7dSKan Liang #else 14582a6c6b7dSKan Liang #error "Unknown endianness" 14592a6c6b7dSKan Liang #endif 14602a6c6b7dSKan Liang }; 14612a6c6b7dSKan Liang 1462607ca46eSDavid Howells #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1463