1b7facbaeSOded Gabbay /* 2b7facbaeSOded Gabbay * Copyright 2014 Advanced Micro Devices, Inc. 3b7facbaeSOded Gabbay * 4b7facbaeSOded Gabbay * Permission is hereby granted, free of charge, to any person obtaining a 5b7facbaeSOded Gabbay * copy of this software and associated documentation files (the "Software"), 6b7facbaeSOded Gabbay * to deal in the Software without restriction, including without limitation 7b7facbaeSOded Gabbay * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8b7facbaeSOded Gabbay * and/or sell copies of the Software, and to permit persons to whom the 9b7facbaeSOded Gabbay * Software is furnished to do so, subject to the following conditions: 10b7facbaeSOded Gabbay * 11b7facbaeSOded Gabbay * The above copyright notice and this permission notice shall be included in 12b7facbaeSOded Gabbay * all copies or substantial portions of the Software. 13b7facbaeSOded Gabbay * 14b7facbaeSOded Gabbay * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15b7facbaeSOded Gabbay * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16b7facbaeSOded Gabbay * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17b7facbaeSOded Gabbay * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18b7facbaeSOded Gabbay * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19b7facbaeSOded Gabbay * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20b7facbaeSOded Gabbay * OTHER DEALINGS IN THE SOFTWARE. 21b7facbaeSOded Gabbay */ 22b7facbaeSOded Gabbay 23b7facbaeSOded Gabbay #ifndef KFD_IOCTL_H_INCLUDED 24b7facbaeSOded Gabbay #define KFD_IOCTL_H_INCLUDED 25b7facbaeSOded Gabbay 26472b46c3SMikko Rapeli #include <drm/drm.h> 27b7facbaeSOded Gabbay #include <linux/ioctl.h> 28b7facbaeSOded Gabbay 2991e2c191SAmber Lin /* 3091e2c191SAmber Lin * - 1.1 - initial version 3191e2c191SAmber Lin * - 1.3 - Add SMI events support 328c44390dSFelix Kuehling * - 1.4 - Indicate new SRAM EDC bit in device properties 3340ce74d1SPhilip Yang * - 1.5 - Add SVM API 34a43e2a0eSFelix Kuehling * - 1.6 - Query clear flags in SVM get_attr API 35692996f2SRajneesh Bhardwaj * - 1.7 - Checkpoint Restore (CRIU) API 3665722ff6SDavid Yat Sin * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs 37*9731dd4cSDaniel Phillips * - 1.9 - Add available memory ioctl 3891e2c191SAmber Lin */ 39b7facbaeSOded Gabbay #define KFD_IOCTL_MAJOR_VERSION 1 40*9731dd4cSDaniel Phillips #define KFD_IOCTL_MINOR_VERSION 9 41b7facbaeSOded Gabbay 42b7facbaeSOded Gabbay struct kfd_ioctl_get_version_args { 43472b46c3SMikko Rapeli __u32 major_version; /* from KFD */ 44472b46c3SMikko Rapeli __u32 minor_version; /* from KFD */ 45b7facbaeSOded Gabbay }; 46b7facbaeSOded Gabbay 47b7facbaeSOded Gabbay /* For kfd_ioctl_create_queue_args.queue_type. */ 481b4670f6SOak Zeng #define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0 491b4670f6SOak Zeng #define KFD_IOC_QUEUE_TYPE_SDMA 0x1 501b4670f6SOak Zeng #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 511b4670f6SOak Zeng #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 52b7facbaeSOded Gabbay 53b7facbaeSOded Gabbay #define KFD_MAX_QUEUE_PERCENTAGE 100 54b7facbaeSOded Gabbay #define KFD_MAX_QUEUE_PRIORITY 15 55b7facbaeSOded Gabbay 56b7facbaeSOded Gabbay struct kfd_ioctl_create_queue_args { 57472b46c3SMikko Rapeli __u64 ring_base_address; /* to KFD */ 58472b46c3SMikko Rapeli __u64 write_pointer_address; /* from KFD */ 59472b46c3SMikko Rapeli __u64 read_pointer_address; /* from KFD */ 60472b46c3SMikko Rapeli __u64 doorbell_offset; /* from KFD */ 61b7facbaeSOded Gabbay 62472b46c3SMikko Rapeli __u32 ring_size; /* to KFD */ 63472b46c3SMikko Rapeli __u32 gpu_id; /* to KFD */ 64472b46c3SMikko Rapeli __u32 queue_type; /* to KFD */ 65472b46c3SMikko Rapeli __u32 queue_percentage; /* to KFD */ 66472b46c3SMikko Rapeli __u32 queue_priority; /* to KFD */ 67472b46c3SMikko Rapeli __u32 queue_id; /* from KFD */ 68b7facbaeSOded Gabbay 69472b46c3SMikko Rapeli __u64 eop_buffer_address; /* to KFD */ 70472b46c3SMikko Rapeli __u64 eop_buffer_size; /* to KFD */ 71472b46c3SMikko Rapeli __u64 ctx_save_restore_address; /* to KFD */ 72373d7080SFelix Kuehling __u32 ctx_save_restore_size; /* to KFD */ 73373d7080SFelix Kuehling __u32 ctl_stack_size; /* to KFD */ 74b7facbaeSOded Gabbay }; 75b7facbaeSOded Gabbay 76b7facbaeSOded Gabbay struct kfd_ioctl_destroy_queue_args { 77472b46c3SMikko Rapeli __u32 queue_id; /* to KFD */ 78472b46c3SMikko Rapeli __u32 pad; 79b7facbaeSOded Gabbay }; 80b7facbaeSOded Gabbay 81b7facbaeSOded Gabbay struct kfd_ioctl_update_queue_args { 82472b46c3SMikko Rapeli __u64 ring_base_address; /* to KFD */ 83b7facbaeSOded Gabbay 84472b46c3SMikko Rapeli __u32 queue_id; /* to KFD */ 85472b46c3SMikko Rapeli __u32 ring_size; /* to KFD */ 86472b46c3SMikko Rapeli __u32 queue_percentage; /* to KFD */ 87472b46c3SMikko Rapeli __u32 queue_priority; /* to KFD */ 88b7facbaeSOded Gabbay }; 89b7facbaeSOded Gabbay 90a7fe68a1SFelix Kuehling struct kfd_ioctl_set_cu_mask_args { 91a7fe68a1SFelix Kuehling __u32 queue_id; /* to KFD */ 92a7fe68a1SFelix Kuehling __u32 num_cu_mask; /* to KFD */ 93a7fe68a1SFelix Kuehling __u64 cu_mask_ptr; /* to KFD */ 94a7fe68a1SFelix Kuehling }; 95a7fe68a1SFelix Kuehling 965df099e8SJay Cornwall struct kfd_ioctl_get_queue_wave_state_args { 978e7f9171SDmitry V. Levin __u64 ctl_stack_address; /* to KFD */ 988e7f9171SDmitry V. Levin __u32 ctl_stack_used_size; /* from KFD */ 998e7f9171SDmitry V. Levin __u32 save_area_used_size; /* from KFD */ 1008e7f9171SDmitry V. Levin __u32 queue_id; /* to KFD */ 1018e7f9171SDmitry V. Levin __u32 pad; 1025df099e8SJay Cornwall }; 1035df099e8SJay Cornwall 104*9731dd4cSDaniel Phillips struct kfd_ioctl_get_available_memory_args { 105*9731dd4cSDaniel Phillips __u64 available; /* from KFD */ 106*9731dd4cSDaniel Phillips __u32 gpu_id; /* to KFD */ 107*9731dd4cSDaniel Phillips __u32 pad; 108*9731dd4cSDaniel Phillips }; 109*9731dd4cSDaniel Phillips 110b7facbaeSOded Gabbay /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ 111b7facbaeSOded Gabbay #define KFD_IOC_CACHE_POLICY_COHERENT 0 112b7facbaeSOded Gabbay #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 113b7facbaeSOded Gabbay 114b7facbaeSOded Gabbay struct kfd_ioctl_set_memory_policy_args { 115472b46c3SMikko Rapeli __u64 alternate_aperture_base; /* to KFD */ 116472b46c3SMikko Rapeli __u64 alternate_aperture_size; /* to KFD */ 117b7facbaeSOded Gabbay 118472b46c3SMikko Rapeli __u32 gpu_id; /* to KFD */ 119472b46c3SMikko Rapeli __u32 default_policy; /* to KFD */ 120472b46c3SMikko Rapeli __u32 alternate_policy; /* to KFD */ 121472b46c3SMikko Rapeli __u32 pad; 122b7facbaeSOded Gabbay }; 123b7facbaeSOded Gabbay 124b7facbaeSOded Gabbay /* 125b7facbaeSOded Gabbay * All counters are monotonic. They are used for profiling of compute jobs. 126b7facbaeSOded Gabbay * The profiling is done by userspace. 127b7facbaeSOded Gabbay * 128b7facbaeSOded Gabbay * In case of GPU reset, the counter should not be affected. 129b7facbaeSOded Gabbay */ 130b7facbaeSOded Gabbay 131b7facbaeSOded Gabbay struct kfd_ioctl_get_clock_counters_args { 132472b46c3SMikko Rapeli __u64 gpu_clock_counter; /* from KFD */ 133472b46c3SMikko Rapeli __u64 cpu_clock_counter; /* from KFD */ 134472b46c3SMikko Rapeli __u64 system_clock_counter; /* from KFD */ 135472b46c3SMikko Rapeli __u64 system_clock_freq; /* from KFD */ 136b7facbaeSOded Gabbay 137472b46c3SMikko Rapeli __u32 gpu_id; /* to KFD */ 138472b46c3SMikko Rapeli __u32 pad; 139b7facbaeSOded Gabbay }; 140b7facbaeSOded Gabbay 141b7facbaeSOded Gabbay struct kfd_process_device_apertures { 142472b46c3SMikko Rapeli __u64 lds_base; /* from KFD */ 143472b46c3SMikko Rapeli __u64 lds_limit; /* from KFD */ 144472b46c3SMikko Rapeli __u64 scratch_base; /* from KFD */ 145472b46c3SMikko Rapeli __u64 scratch_limit; /* from KFD */ 146472b46c3SMikko Rapeli __u64 gpuvm_base; /* from KFD */ 147472b46c3SMikko Rapeli __u64 gpuvm_limit; /* from KFD */ 148472b46c3SMikko Rapeli __u32 gpu_id; /* from KFD */ 149472b46c3SMikko Rapeli __u32 pad; 150b7facbaeSOded Gabbay }; 151b7facbaeSOded Gabbay 152c7bcbfa4SFelix Kuehling /* 153c7bcbfa4SFelix Kuehling * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use 154c7bcbfa4SFelix Kuehling * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an 155c7bcbfa4SFelix Kuehling * unlimited number of GPUs. 156c7bcbfa4SFelix Kuehling */ 157c7bcbfa4SFelix Kuehling #define NUM_OF_SUPPORTED_GPUS 7 158b7facbaeSOded Gabbay struct kfd_ioctl_get_process_apertures_args { 159b7facbaeSOded Gabbay struct kfd_process_device_apertures 160b7facbaeSOded Gabbay process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */ 161b7facbaeSOded Gabbay 162b7facbaeSOded Gabbay /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */ 163472b46c3SMikko Rapeli __u32 num_of_nodes; 164472b46c3SMikko Rapeli __u32 pad; 165b7facbaeSOded Gabbay }; 166b7facbaeSOded Gabbay 167c7bcbfa4SFelix Kuehling struct kfd_ioctl_get_process_apertures_new_args { 168c7bcbfa4SFelix Kuehling /* User allocated. Pointer to struct kfd_process_device_apertures 169c7bcbfa4SFelix Kuehling * filled in by Kernel 170c7bcbfa4SFelix Kuehling */ 171c7bcbfa4SFelix Kuehling __u64 kfd_process_device_apertures_ptr; 172c7bcbfa4SFelix Kuehling /* to KFD - indicates amount of memory present in 173c7bcbfa4SFelix Kuehling * kfd_process_device_apertures_ptr 174c7bcbfa4SFelix Kuehling * from KFD - Number of entries filled by KFD. 175c7bcbfa4SFelix Kuehling */ 176c7bcbfa4SFelix Kuehling __u32 num_of_nodes; 177c7bcbfa4SFelix Kuehling __u32 pad; 178c7bcbfa4SFelix Kuehling }; 179c7bcbfa4SFelix Kuehling 180aef11009SYair Shachar #define MAX_ALLOWED_NUM_POINTS 100 181aef11009SYair Shachar #define MAX_ALLOWED_AW_BUFF_SIZE 4096 182aef11009SYair Shachar #define MAX_ALLOWED_WAC_BUFF_SIZE 128 183aef11009SYair Shachar 184aef11009SYair Shachar struct kfd_ioctl_dbg_register_args { 185472b46c3SMikko Rapeli __u32 gpu_id; /* to KFD */ 186472b46c3SMikko Rapeli __u32 pad; 187aef11009SYair Shachar }; 188aef11009SYair Shachar 189aef11009SYair Shachar struct kfd_ioctl_dbg_unregister_args { 190472b46c3SMikko Rapeli __u32 gpu_id; /* to KFD */ 191472b46c3SMikko Rapeli __u32 pad; 192aef11009SYair Shachar }; 193aef11009SYair Shachar 194aef11009SYair Shachar struct kfd_ioctl_dbg_address_watch_args { 195472b46c3SMikko Rapeli __u64 content_ptr; /* a pointer to the actual content */ 196472b46c3SMikko Rapeli __u32 gpu_id; /* to KFD */ 197472b46c3SMikko Rapeli __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 198aef11009SYair Shachar }; 199aef11009SYair Shachar 200aef11009SYair Shachar struct kfd_ioctl_dbg_wave_control_args { 201472b46c3SMikko Rapeli __u64 content_ptr; /* a pointer to the actual content */ 202472b46c3SMikko Rapeli __u32 gpu_id; /* to KFD */ 203472b46c3SMikko Rapeli __u32 buf_size_in_bytes; /*including gpu_id and buf_size */ 204aef11009SYair Shachar }; 205aef11009SYair Shachar 20665722ff6SDavid Yat Sin #define KFD_INVALID_FD 0xffffffff 20765722ff6SDavid Yat Sin 20829a5d3ebSAndrew Lewycky /* Matching HSA_EVENTTYPE */ 20929a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_SIGNAL 0 21029a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_NODECHANGE 1 21129a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_DEVICESTATECHANGE 2 21229a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_HW_EXCEPTION 3 21329a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_SYSTEM_EVENT 4 21429a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_DEBUG_EVENT 5 21529a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_PROFILE_EVENT 6 21629a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_QUEUE_EVENT 7 21729a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_MEMORY 8 21829a5d3ebSAndrew Lewycky 21929a5d3ebSAndrew Lewycky #define KFD_IOC_WAIT_RESULT_COMPLETE 0 22029a5d3ebSAndrew Lewycky #define KFD_IOC_WAIT_RESULT_TIMEOUT 1 22129a5d3ebSAndrew Lewycky #define KFD_IOC_WAIT_RESULT_FAIL 2 22229a5d3ebSAndrew Lewycky 2237e86a365SOded Gabbay #define KFD_SIGNAL_EVENT_LIMIT 4096 22429a5d3ebSAndrew Lewycky 2250c119abaSShaoyun Liu /* For kfd_event_data.hw_exception_data.reset_type. */ 2260c119abaSShaoyun Liu #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0 2270c119abaSShaoyun Liu #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1 2280c119abaSShaoyun Liu 2290c119abaSShaoyun Liu /* For kfd_event_data.hw_exception_data.reset_cause. */ 2300c119abaSShaoyun Liu #define KFD_HW_EXCEPTION_GPU_HANG 0 2310c119abaSShaoyun Liu #define KFD_HW_EXCEPTION_ECC 1 2320c119abaSShaoyun Liu 2339b54d201SEric Huang /* For kfd_hsa_memory_exception_data.ErrorType */ 2349b54d201SEric Huang #define KFD_MEM_ERR_NO_RAS 0 2359b54d201SEric Huang #define KFD_MEM_ERR_SRAM_ECC 1 2369b54d201SEric Huang #define KFD_MEM_ERR_POISON_CONSUMED 2 2379b54d201SEric Huang #define KFD_MEM_ERR_GPU_HANG 3 2380c119abaSShaoyun Liu 23929a5d3ebSAndrew Lewycky struct kfd_ioctl_create_event_args { 240472b46c3SMikko Rapeli __u64 event_page_offset; /* from KFD */ 241472b46c3SMikko Rapeli __u32 event_trigger_data; /* from KFD - signal events only */ 242472b46c3SMikko Rapeli __u32 event_type; /* to KFD */ 243472b46c3SMikko Rapeli __u32 auto_reset; /* to KFD */ 244472b46c3SMikko Rapeli __u32 node_id; /* to KFD - only valid for certain 24529a5d3ebSAndrew Lewycky event types */ 246472b46c3SMikko Rapeli __u32 event_id; /* from KFD */ 247472b46c3SMikko Rapeli __u32 event_slot_index; /* from KFD */ 24829a5d3ebSAndrew Lewycky }; 24929a5d3ebSAndrew Lewycky 25029a5d3ebSAndrew Lewycky struct kfd_ioctl_destroy_event_args { 251472b46c3SMikko Rapeli __u32 event_id; /* to KFD */ 252472b46c3SMikko Rapeli __u32 pad; 25329a5d3ebSAndrew Lewycky }; 25429a5d3ebSAndrew Lewycky 25529a5d3ebSAndrew Lewycky struct kfd_ioctl_set_event_args { 256472b46c3SMikko Rapeli __u32 event_id; /* to KFD */ 257472b46c3SMikko Rapeli __u32 pad; 25829a5d3ebSAndrew Lewycky }; 25929a5d3ebSAndrew Lewycky 26029a5d3ebSAndrew Lewycky struct kfd_ioctl_reset_event_args { 261472b46c3SMikko Rapeli __u32 event_id; /* to KFD */ 262472b46c3SMikko Rapeli __u32 pad; 26329a5d3ebSAndrew Lewycky }; 26429a5d3ebSAndrew Lewycky 26529a5d3ebSAndrew Lewycky struct kfd_memory_exception_failure { 266472b46c3SMikko Rapeli __u32 NotPresent; /* Page not present or supervisor privilege */ 267472b46c3SMikko Rapeli __u32 ReadOnly; /* Write access to a read-only page */ 268472b46c3SMikko Rapeli __u32 NoExecute; /* Execute access to a page marked NX */ 2692640c3faSshaoyunl __u32 imprecise; /* Can't determine the exact fault address */ 27029a5d3ebSAndrew Lewycky }; 27129a5d3ebSAndrew Lewycky 27229a5d3ebSAndrew Lewycky /* memory exception data */ 27329a5d3ebSAndrew Lewycky struct kfd_hsa_memory_exception_data { 27429a5d3ebSAndrew Lewycky struct kfd_memory_exception_failure failure; 275472b46c3SMikko Rapeli __u64 va; 276472b46c3SMikko Rapeli __u32 gpu_id; 2779b54d201SEric Huang __u32 ErrorType; /* 0 = no RAS error, 2789b54d201SEric Huang * 1 = ECC_SRAM, 2799b54d201SEric Huang * 2 = Link_SYNFLOOD (poison), 2809b54d201SEric Huang * 3 = GPU hang (not attributable to a specific cause), 2819b54d201SEric Huang * other values reserved 2829b54d201SEric Huang */ 28329a5d3ebSAndrew Lewycky }; 28429a5d3ebSAndrew Lewycky 2850c119abaSShaoyun Liu /* hw exception data */ 2860c119abaSShaoyun Liu struct kfd_hsa_hw_exception_data { 287aba11838SDmitry V. Levin __u32 reset_type; 288aba11838SDmitry V. Levin __u32 reset_cause; 289aba11838SDmitry V. Levin __u32 memory_lost; 290aba11838SDmitry V. Levin __u32 gpu_id; 2910c119abaSShaoyun Liu }; 2920c119abaSShaoyun Liu 29329a5d3ebSAndrew Lewycky /* Event data */ 29429a5d3ebSAndrew Lewycky struct kfd_event_data { 29529a5d3ebSAndrew Lewycky union { 29629a5d3ebSAndrew Lewycky struct kfd_hsa_memory_exception_data memory_exception_data; 2970c119abaSShaoyun Liu struct kfd_hsa_hw_exception_data hw_exception_data; 29829a5d3ebSAndrew Lewycky }; /* From KFD */ 299472b46c3SMikko Rapeli __u64 kfd_event_data_ext; /* pointer to an extension structure 30029a5d3ebSAndrew Lewycky for future exception types */ 301472b46c3SMikko Rapeli __u32 event_id; /* to KFD */ 302472b46c3SMikko Rapeli __u32 pad; 30329a5d3ebSAndrew Lewycky }; 30429a5d3ebSAndrew Lewycky 30529a5d3ebSAndrew Lewycky struct kfd_ioctl_wait_events_args { 306472b46c3SMikko Rapeli __u64 events_ptr; /* pointed to struct 307aef11009SYair Shachar kfd_event_data array, to KFD */ 308472b46c3SMikko Rapeli __u32 num_events; /* to KFD */ 309472b46c3SMikko Rapeli __u32 wait_for_all; /* to KFD */ 310472b46c3SMikko Rapeli __u32 timeout; /* to KFD */ 311472b46c3SMikko Rapeli __u32 wait_result; /* from KFD */ 31229a5d3ebSAndrew Lewycky }; 31329a5d3ebSAndrew Lewycky 3146a1c9510SMoses Reuben struct kfd_ioctl_set_scratch_backing_va_args { 315b4d08520SDmitry V. Levin __u64 va_addr; /* to KFD */ 316b4d08520SDmitry V. Levin __u32 gpu_id; /* to KFD */ 317b4d08520SDmitry V. Levin __u32 pad; 3186a1c9510SMoses Reuben }; 3196a1c9510SMoses Reuben 3205d71dbc3SYong Zhao struct kfd_ioctl_get_tile_config_args { 3215d71dbc3SYong Zhao /* to KFD: pointer to tile array */ 322b4d08520SDmitry V. Levin __u64 tile_config_ptr; 3235d71dbc3SYong Zhao /* to KFD: pointer to macro tile array */ 324b4d08520SDmitry V. Levin __u64 macro_tile_config_ptr; 3255d71dbc3SYong Zhao /* to KFD: array size allocated by user mode 3265d71dbc3SYong Zhao * from KFD: array size filled by kernel 3275d71dbc3SYong Zhao */ 328b4d08520SDmitry V. Levin __u32 num_tile_configs; 3295d71dbc3SYong Zhao /* to KFD: array size allocated by user mode 3305d71dbc3SYong Zhao * from KFD: array size filled by kernel 3315d71dbc3SYong Zhao */ 332b4d08520SDmitry V. Levin __u32 num_macro_tile_configs; 3335d71dbc3SYong Zhao 334b4d08520SDmitry V. Levin __u32 gpu_id; /* to KFD */ 335b4d08520SDmitry V. Levin __u32 gb_addr_config; /* from KFD */ 336b4d08520SDmitry V. Levin __u32 num_banks; /* from KFD */ 337b4d08520SDmitry V. Levin __u32 num_ranks; /* from KFD */ 3385d71dbc3SYong Zhao /* struct size can be extended later if needed 3395d71dbc3SYong Zhao * without breaking ABI compatibility 3405d71dbc3SYong Zhao */ 3415d71dbc3SYong Zhao }; 3425d71dbc3SYong Zhao 343d7b9bd22SFelix Kuehling struct kfd_ioctl_set_trap_handler_args { 344a1102445SFelix Kuehling __u64 tba_addr; /* to KFD */ 345a1102445SFelix Kuehling __u64 tma_addr; /* to KFD */ 346a1102445SFelix Kuehling __u32 gpu_id; /* to KFD */ 347a1102445SFelix Kuehling __u32 pad; 348d7b9bd22SFelix Kuehling }; 349d7b9bd22SFelix Kuehling 3505ec7e028SFelix Kuehling struct kfd_ioctl_acquire_vm_args { 3515ec7e028SFelix Kuehling __u32 drm_fd; /* to KFD */ 3525ec7e028SFelix Kuehling __u32 gpu_id; /* to KFD */ 3535ec7e028SFelix Kuehling }; 3545ec7e028SFelix Kuehling 3555ec7e028SFelix Kuehling /* Allocation flags: memory types */ 3565ec7e028SFelix Kuehling #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0) 3575ec7e028SFelix Kuehling #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1) 3585ec7e028SFelix Kuehling #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2) 3595ec7e028SFelix Kuehling #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3) 360d8e408a8SOak Zeng #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4) 3615ec7e028SFelix Kuehling /* Allocation flags: attributes/access options */ 3625ec7e028SFelix Kuehling #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31) 3635ec7e028SFelix Kuehling #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) 3645ec7e028SFelix Kuehling #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29) 3655ec7e028SFelix Kuehling #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) 3665ec7e028SFelix Kuehling #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) 3675ec7e028SFelix Kuehling #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) 36898291d6dSEric Huang #define KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED (1 << 25) 3695ec7e028SFelix Kuehling 3705ec7e028SFelix Kuehling /* Allocate memory for later SVM (shared virtual memory) mapping. 3715ec7e028SFelix Kuehling * 3725ec7e028SFelix Kuehling * @va_addr: virtual address of the memory to be allocated 3735ec7e028SFelix Kuehling * all later mappings on all GPUs will use this address 3745ec7e028SFelix Kuehling * @size: size in bytes 3755ec7e028SFelix Kuehling * @handle: buffer handle returned to user mode, used to refer to 3765ec7e028SFelix Kuehling * this allocation for mapping, unmapping and freeing 3775ec7e028SFelix Kuehling * @mmap_offset: for CPU-mapping the allocation by mmapping a render node 3785ec7e028SFelix Kuehling * for userptrs this is overloaded to specify the CPU address 3795ec7e028SFelix Kuehling * @gpu_id: device identifier 3805ec7e028SFelix Kuehling * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above 3815ec7e028SFelix Kuehling */ 3825ec7e028SFelix Kuehling struct kfd_ioctl_alloc_memory_of_gpu_args { 3835ec7e028SFelix Kuehling __u64 va_addr; /* to KFD */ 3845ec7e028SFelix Kuehling __u64 size; /* to KFD */ 3855ec7e028SFelix Kuehling __u64 handle; /* from KFD */ 3865ec7e028SFelix Kuehling __u64 mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */ 3875ec7e028SFelix Kuehling __u32 gpu_id; /* to KFD */ 3885ec7e028SFelix Kuehling __u32 flags; 3895ec7e028SFelix Kuehling }; 3905ec7e028SFelix Kuehling 3915ec7e028SFelix Kuehling /* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu 3925ec7e028SFelix Kuehling * 3935ec7e028SFelix Kuehling * @handle: memory handle returned by alloc 3945ec7e028SFelix Kuehling */ 3955ec7e028SFelix Kuehling struct kfd_ioctl_free_memory_of_gpu_args { 3965ec7e028SFelix Kuehling __u64 handle; /* to KFD */ 3975ec7e028SFelix Kuehling }; 3985ec7e028SFelix Kuehling 3995ec7e028SFelix Kuehling /* Map memory to one or more GPUs 4005ec7e028SFelix Kuehling * 4015ec7e028SFelix Kuehling * @handle: memory handle returned by alloc 4025ec7e028SFelix Kuehling * @device_ids_array_ptr: array of gpu_ids (__u32 per device) 4035ec7e028SFelix Kuehling * @n_devices: number of devices in the array 4045ec7e028SFelix Kuehling * @n_success: number of devices mapped successfully 4055ec7e028SFelix Kuehling * 4065ec7e028SFelix Kuehling * @n_success returns information to the caller how many devices from 4075ec7e028SFelix Kuehling * the start of the array have mapped the buffer successfully. It can 4085ec7e028SFelix Kuehling * be passed into a subsequent retry call to skip those devices. For 4095ec7e028SFelix Kuehling * the first call the caller should initialize it to 0. 4105ec7e028SFelix Kuehling * 4115ec7e028SFelix Kuehling * If the ioctl completes with return code 0 (success), n_success == 4125ec7e028SFelix Kuehling * n_devices. 4135ec7e028SFelix Kuehling */ 4145ec7e028SFelix Kuehling struct kfd_ioctl_map_memory_to_gpu_args { 4155ec7e028SFelix Kuehling __u64 handle; /* to KFD */ 4165ec7e028SFelix Kuehling __u64 device_ids_array_ptr; /* to KFD */ 4175ec7e028SFelix Kuehling __u32 n_devices; /* to KFD */ 4185ec7e028SFelix Kuehling __u32 n_success; /* to/from KFD */ 4195ec7e028SFelix Kuehling }; 4205ec7e028SFelix Kuehling 4215ec7e028SFelix Kuehling /* Unmap memory from one or more GPUs 4225ec7e028SFelix Kuehling * 4235ec7e028SFelix Kuehling * same arguments as for mapping 4245ec7e028SFelix Kuehling */ 4255ec7e028SFelix Kuehling struct kfd_ioctl_unmap_memory_from_gpu_args { 4265ec7e028SFelix Kuehling __u64 handle; /* to KFD */ 4275ec7e028SFelix Kuehling __u64 device_ids_array_ptr; /* to KFD */ 4285ec7e028SFelix Kuehling __u32 n_devices; /* to KFD */ 4295ec7e028SFelix Kuehling __u32 n_success; /* to/from KFD */ 4305ec7e028SFelix Kuehling }; 4315ec7e028SFelix Kuehling 4325bb4b78bSOak Zeng /* Allocate GWS for specific queue 4335bb4b78bSOak Zeng * 4345bb4b78bSOak Zeng * @queue_id: queue's id that GWS is allocated for 4355bb4b78bSOak Zeng * @num_gws: how many GWS to allocate 4365bb4b78bSOak Zeng * @first_gws: index of the first GWS allocated. 4375bb4b78bSOak Zeng * only support contiguous GWS allocation 4385bb4b78bSOak Zeng */ 4395bb4b78bSOak Zeng struct kfd_ioctl_alloc_queue_gws_args { 4405bb4b78bSOak Zeng __u32 queue_id; /* to KFD */ 4415bb4b78bSOak Zeng __u32 num_gws; /* to KFD */ 4425bb4b78bSOak Zeng __u32 first_gws; /* from KFD */ 4435bb4b78bSOak Zeng __u32 pad; 4445bb4b78bSOak Zeng }; 4455bb4b78bSOak Zeng 4461dde0ea9SFelix Kuehling struct kfd_ioctl_get_dmabuf_info_args { 4471dde0ea9SFelix Kuehling __u64 size; /* from KFD */ 4481dde0ea9SFelix Kuehling __u64 metadata_ptr; /* to KFD */ 4491dde0ea9SFelix Kuehling __u32 metadata_size; /* to KFD (space allocated by user) 4501dde0ea9SFelix Kuehling * from KFD (actual metadata size) 4511dde0ea9SFelix Kuehling */ 4521dde0ea9SFelix Kuehling __u32 gpu_id; /* from KFD */ 4531dde0ea9SFelix Kuehling __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */ 4541dde0ea9SFelix Kuehling __u32 dmabuf_fd; /* to KFD */ 4551dde0ea9SFelix Kuehling }; 4561dde0ea9SFelix Kuehling 4571dde0ea9SFelix Kuehling struct kfd_ioctl_import_dmabuf_args { 4581dde0ea9SFelix Kuehling __u64 va_addr; /* to KFD */ 4591dde0ea9SFelix Kuehling __u64 handle; /* from KFD */ 4601dde0ea9SFelix Kuehling __u32 gpu_id; /* to KFD */ 4611dde0ea9SFelix Kuehling __u32 dmabuf_fd; /* to KFD */ 4621dde0ea9SFelix Kuehling }; 4631dde0ea9SFelix Kuehling 464938a0650SAmber Lin /* 465938a0650SAmber Lin * KFD SMI(System Management Interface) events 466938a0650SAmber Lin */ 467522ec6e0SMukul Joshi enum kfd_smi_event { 468522ec6e0SMukul Joshi KFD_SMI_EVENT_NONE = 0, /* not used */ 469522ec6e0SMukul Joshi KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */ 470522ec6e0SMukul Joshi KFD_SMI_EVENT_THERMAL_THROTTLE = 2, 47155977744SMukul Joshi KFD_SMI_EVENT_GPU_PRE_RESET = 3, 47255977744SMukul Joshi KFD_SMI_EVENT_GPU_POST_RESET = 4, 473522ec6e0SMukul Joshi }; 474522ec6e0SMukul Joshi 475522ec6e0SMukul Joshi #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1)) 476d58b8a99SPhilip Yang #define KFD_SMI_EVENT_MSG_SIZE 96 477938a0650SAmber Lin 478938a0650SAmber Lin struct kfd_ioctl_smi_events_args { 479938a0650SAmber Lin __u32 gpuid; /* to KFD */ 480938a0650SAmber Lin __u32 anon_fd; /* from KFD */ 481938a0650SAmber Lin }; 482938a0650SAmber Lin 48336988070SRajneesh Bhardwaj /************************************************************************************************** 48436988070SRajneesh Bhardwaj * CRIU IOCTLs (Checkpoint Restore In Userspace) 48536988070SRajneesh Bhardwaj * 48636988070SRajneesh Bhardwaj * When checkpointing a process, the userspace application will perform: 48736988070SRajneesh Bhardwaj * 1. PROCESS_INFO op to determine current process information. This pauses execution and evicts 48836988070SRajneesh Bhardwaj * all the queues. 48936988070SRajneesh Bhardwaj * 2. CHECKPOINT op to checkpoint process contents (BOs, queues, events, svm-ranges) 49036988070SRajneesh Bhardwaj * 3. UNPAUSE op to un-evict all the queues 49136988070SRajneesh Bhardwaj * 49236988070SRajneesh Bhardwaj * When restoring a process, the CRIU userspace application will perform: 49336988070SRajneesh Bhardwaj * 49436988070SRajneesh Bhardwaj * 1. RESTORE op to restore process contents 49536988070SRajneesh Bhardwaj * 2. RESUME op to start the process 49636988070SRajneesh Bhardwaj * 49736988070SRajneesh Bhardwaj * Note: Queues are forced into an evicted state after a successful PROCESS_INFO. User 49836988070SRajneesh Bhardwaj * application needs to perform an UNPAUSE operation after calling PROCESS_INFO. 49936988070SRajneesh Bhardwaj */ 50036988070SRajneesh Bhardwaj 50136988070SRajneesh Bhardwaj enum kfd_criu_op { 50236988070SRajneesh Bhardwaj KFD_CRIU_OP_PROCESS_INFO, 50336988070SRajneesh Bhardwaj KFD_CRIU_OP_CHECKPOINT, 50436988070SRajneesh Bhardwaj KFD_CRIU_OP_UNPAUSE, 50536988070SRajneesh Bhardwaj KFD_CRIU_OP_RESTORE, 50636988070SRajneesh Bhardwaj KFD_CRIU_OP_RESUME, 50736988070SRajneesh Bhardwaj }; 50836988070SRajneesh Bhardwaj 50936988070SRajneesh Bhardwaj /** 51036988070SRajneesh Bhardwaj * kfd_ioctl_criu_args - Arguments perform CRIU operation 51136988070SRajneesh Bhardwaj * @devices: [in/out] User pointer to memory location for devices information. 51236988070SRajneesh Bhardwaj * This is an array of type kfd_criu_device_bucket. 51336988070SRajneesh Bhardwaj * @bos: [in/out] User pointer to memory location for BOs information 51436988070SRajneesh Bhardwaj * This is an array of type kfd_criu_bo_bucket. 51536988070SRajneesh Bhardwaj * @priv_data: [in/out] User pointer to memory location for private data 51636988070SRajneesh Bhardwaj * @priv_data_size: [in/out] Size of priv_data in bytes 51736988070SRajneesh Bhardwaj * @num_devices: [in/out] Number of GPUs used by process. Size of @devices array. 51836988070SRajneesh Bhardwaj * @num_bos [in/out] Number of BOs used by process. Size of @bos array. 51936988070SRajneesh Bhardwaj * @num_objects: [in/out] Number of objects used by process. Objects are opaque to 52036988070SRajneesh Bhardwaj * user application. 52136988070SRajneesh Bhardwaj * @pid: [in/out] PID of the process being checkpointed 52236988070SRajneesh Bhardwaj * @op [in] Type of operation (kfd_criu_op) 52336988070SRajneesh Bhardwaj * 52436988070SRajneesh Bhardwaj * Return: 0 on success, -errno on failure 52536988070SRajneesh Bhardwaj */ 52636988070SRajneesh Bhardwaj struct kfd_ioctl_criu_args { 52736988070SRajneesh Bhardwaj __u64 devices; /* Used during ops: CHECKPOINT, RESTORE */ 52836988070SRajneesh Bhardwaj __u64 bos; /* Used during ops: CHECKPOINT, RESTORE */ 52936988070SRajneesh Bhardwaj __u64 priv_data; /* Used during ops: CHECKPOINT, RESTORE */ 53036988070SRajneesh Bhardwaj __u64 priv_data_size; /* Used during ops: PROCESS_INFO, RESTORE */ 53136988070SRajneesh Bhardwaj __u32 num_devices; /* Used during ops: PROCESS_INFO, RESTORE */ 53236988070SRajneesh Bhardwaj __u32 num_bos; /* Used during ops: PROCESS_INFO, RESTORE */ 53336988070SRajneesh Bhardwaj __u32 num_objects; /* Used during ops: PROCESS_INFO, RESTORE */ 53436988070SRajneesh Bhardwaj __u32 pid; /* Used during ops: PROCESS_INFO, RESUME */ 53536988070SRajneesh Bhardwaj __u32 op; 53636988070SRajneesh Bhardwaj }; 53736988070SRajneesh Bhardwaj 53836988070SRajneesh Bhardwaj struct kfd_criu_device_bucket { 53936988070SRajneesh Bhardwaj __u32 user_gpu_id; 54036988070SRajneesh Bhardwaj __u32 actual_gpu_id; 54136988070SRajneesh Bhardwaj __u32 drm_fd; 54236988070SRajneesh Bhardwaj __u32 pad; 54336988070SRajneesh Bhardwaj }; 54436988070SRajneesh Bhardwaj 54536988070SRajneesh Bhardwaj struct kfd_criu_bo_bucket { 54636988070SRajneesh Bhardwaj __u64 addr; 54736988070SRajneesh Bhardwaj __u64 size; 54836988070SRajneesh Bhardwaj __u64 offset; 54936988070SRajneesh Bhardwaj __u64 restored_offset; /* During restore, updated offset for BO */ 55036988070SRajneesh Bhardwaj __u32 gpu_id; /* This is the user_gpu_id */ 55136988070SRajneesh Bhardwaj __u32 alloc_flags; 55236988070SRajneesh Bhardwaj __u32 dmabuf_fd; 55336988070SRajneesh Bhardwaj __u32 pad; 55436988070SRajneesh Bhardwaj }; 55536988070SRajneesh Bhardwaj 55636988070SRajneesh Bhardwaj /* CRIU IOCTLs - END */ 55736988070SRajneesh Bhardwaj /**************************************************************************************************/ 55836988070SRajneesh Bhardwaj 55988807dc8SOak Zeng /* Register offset inside the remapped mmio page 56088807dc8SOak Zeng */ 56188807dc8SOak Zeng enum kfd_mmio_remap { 56288807dc8SOak Zeng KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, 56388807dc8SOak Zeng KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, 56488807dc8SOak Zeng }; 56588807dc8SOak Zeng 56640ce74d1SPhilip Yang /* Guarantee host access to memory */ 56740ce74d1SPhilip Yang #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 56840ce74d1SPhilip Yang /* Fine grained coherency between all devices with access */ 56940ce74d1SPhilip Yang #define KFD_IOCTL_SVM_FLAG_COHERENT 0x00000002 57040ce74d1SPhilip Yang /* Use any GPU in same hive as preferred device */ 57140ce74d1SPhilip Yang #define KFD_IOCTL_SVM_FLAG_HIVE_LOCAL 0x00000004 57240ce74d1SPhilip Yang /* GPUs only read, allows replication */ 57340ce74d1SPhilip Yang #define KFD_IOCTL_SVM_FLAG_GPU_RO 0x00000008 57440ce74d1SPhilip Yang /* Allow execution on GPU */ 57540ce74d1SPhilip Yang #define KFD_IOCTL_SVM_FLAG_GPU_EXEC 0x00000010 57640ce74d1SPhilip Yang /* GPUs mostly read, may allow similar optimizations as RO, but writes fault */ 57740ce74d1SPhilip Yang #define KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY 0x00000020 57840ce74d1SPhilip Yang 57940ce74d1SPhilip Yang /** 58040ce74d1SPhilip Yang * kfd_ioctl_svm_op - SVM ioctl operations 58140ce74d1SPhilip Yang * 58240ce74d1SPhilip Yang * @KFD_IOCTL_SVM_OP_SET_ATTR: Modify one or more attributes 58340ce74d1SPhilip Yang * @KFD_IOCTL_SVM_OP_GET_ATTR: Query one or more attributes 58440ce74d1SPhilip Yang */ 58540ce74d1SPhilip Yang enum kfd_ioctl_svm_op { 58640ce74d1SPhilip Yang KFD_IOCTL_SVM_OP_SET_ATTR, 58740ce74d1SPhilip Yang KFD_IOCTL_SVM_OP_GET_ATTR 58840ce74d1SPhilip Yang }; 58940ce74d1SPhilip Yang 59040ce74d1SPhilip Yang /** kfd_ioctl_svm_location - Enum for preferred and prefetch locations 59140ce74d1SPhilip Yang * 59240ce74d1SPhilip Yang * GPU IDs are used to specify GPUs as preferred and prefetch locations. 59340ce74d1SPhilip Yang * Below definitions are used for system memory or for leaving the preferred 59440ce74d1SPhilip Yang * location unspecified. 59540ce74d1SPhilip Yang */ 59640ce74d1SPhilip Yang enum kfd_ioctl_svm_location { 59740ce74d1SPhilip Yang KFD_IOCTL_SVM_LOCATION_SYSMEM = 0, 59840ce74d1SPhilip Yang KFD_IOCTL_SVM_LOCATION_UNDEFINED = 0xffffffff 59940ce74d1SPhilip Yang }; 60040ce74d1SPhilip Yang 60140ce74d1SPhilip Yang /** 60240ce74d1SPhilip Yang * kfd_ioctl_svm_attr_type - SVM attribute types 60340ce74d1SPhilip Yang * 60440ce74d1SPhilip Yang * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: gpuid of the preferred location, 0 for 60540ce74d1SPhilip Yang * system memory 60640ce74d1SPhilip Yang * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: gpuid of the prefetch location, 0 for 60740ce74d1SPhilip Yang * system memory. Setting this triggers an 60840ce74d1SPhilip Yang * immediate prefetch (migration). 60940ce74d1SPhilip Yang * @KFD_IOCTL_SVM_ATTR_ACCESS: 61040ce74d1SPhilip Yang * @KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE: 61140ce74d1SPhilip Yang * @KFD_IOCTL_SVM_ATTR_NO_ACCESS: specify memory access for the gpuid given 61240ce74d1SPhilip Yang * by the attribute value 61340ce74d1SPhilip Yang * @KFD_IOCTL_SVM_ATTR_SET_FLAGS: bitmask of flags to set (see 61440ce74d1SPhilip Yang * KFD_IOCTL_SVM_FLAG_...) 61540ce74d1SPhilip Yang * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS: bitmask of flags to clear 61640ce74d1SPhilip Yang * @KFD_IOCTL_SVM_ATTR_GRANULARITY: migration granularity 61740ce74d1SPhilip Yang * (log2 num pages) 61840ce74d1SPhilip Yang */ 61940ce74d1SPhilip Yang enum kfd_ioctl_svm_attr_type { 62040ce74d1SPhilip Yang KFD_IOCTL_SVM_ATTR_PREFERRED_LOC, 62140ce74d1SPhilip Yang KFD_IOCTL_SVM_ATTR_PREFETCH_LOC, 62240ce74d1SPhilip Yang KFD_IOCTL_SVM_ATTR_ACCESS, 62340ce74d1SPhilip Yang KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE, 62440ce74d1SPhilip Yang KFD_IOCTL_SVM_ATTR_NO_ACCESS, 62540ce74d1SPhilip Yang KFD_IOCTL_SVM_ATTR_SET_FLAGS, 62640ce74d1SPhilip Yang KFD_IOCTL_SVM_ATTR_CLR_FLAGS, 62740ce74d1SPhilip Yang KFD_IOCTL_SVM_ATTR_GRANULARITY 62840ce74d1SPhilip Yang }; 62940ce74d1SPhilip Yang 63040ce74d1SPhilip Yang /** 63140ce74d1SPhilip Yang * kfd_ioctl_svm_attribute - Attributes as pairs of type and value 63240ce74d1SPhilip Yang * 63340ce74d1SPhilip Yang * The meaning of the @value depends on the attribute type. 63440ce74d1SPhilip Yang * 63540ce74d1SPhilip Yang * @type: attribute type (see enum @kfd_ioctl_svm_attr_type) 63640ce74d1SPhilip Yang * @value: attribute value 63740ce74d1SPhilip Yang */ 63840ce74d1SPhilip Yang struct kfd_ioctl_svm_attribute { 63940ce74d1SPhilip Yang __u32 type; 64040ce74d1SPhilip Yang __u32 value; 64140ce74d1SPhilip Yang }; 64240ce74d1SPhilip Yang 64340ce74d1SPhilip Yang /** 64440ce74d1SPhilip Yang * kfd_ioctl_svm_args - Arguments for SVM ioctl 64540ce74d1SPhilip Yang * 64640ce74d1SPhilip Yang * @op specifies the operation to perform (see enum 64740ce74d1SPhilip Yang * @kfd_ioctl_svm_op). @start_addr and @size are common for all 64840ce74d1SPhilip Yang * operations. 64940ce74d1SPhilip Yang * 65040ce74d1SPhilip Yang * A variable number of attributes can be given in @attrs. 65140ce74d1SPhilip Yang * @nattr specifies the number of attributes. New attributes can be 65240ce74d1SPhilip Yang * added in the future without breaking the ABI. If unknown attributes 65340ce74d1SPhilip Yang * are given, the function returns -EINVAL. 65440ce74d1SPhilip Yang * 65540ce74d1SPhilip Yang * @KFD_IOCTL_SVM_OP_SET_ATTR sets attributes for a virtual address 65640ce74d1SPhilip Yang * range. It may overlap existing virtual address ranges. If it does, 65740ce74d1SPhilip Yang * the existing ranges will be split such that the attribute changes 65840ce74d1SPhilip Yang * only apply to the specified address range. 65940ce74d1SPhilip Yang * 66040ce74d1SPhilip Yang * @KFD_IOCTL_SVM_OP_GET_ATTR returns the intersection of attributes 66140ce74d1SPhilip Yang * over all memory in the given range and returns the result as the 66240ce74d1SPhilip Yang * attribute value. If different pages have different preferred or 66340ce74d1SPhilip Yang * prefetch locations, 0xffffffff will be returned for 66440ce74d1SPhilip Yang * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or 66540ce74d1SPhilip Yang * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For 66640ce74d1SPhilip Yang * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be 667a43e2a0eSFelix Kuehling * aggregated by bitwise AND. That means, a flag will be set in the 668a43e2a0eSFelix Kuehling * output, if that flag is set for all pages in the range. For 669a43e2a0eSFelix Kuehling * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS, flags of all pages will be 670a43e2a0eSFelix Kuehling * aggregated by bitwise NOR. That means, a flag will be set in the 671a43e2a0eSFelix Kuehling * output, if that flag is clear for all pages in the range. 672a43e2a0eSFelix Kuehling * The minimum migration granularity throughout the range will be 673a43e2a0eSFelix Kuehling * returned for @KFD_IOCTL_SVM_ATTR_GRANULARITY. 67440ce74d1SPhilip Yang * 67540ce74d1SPhilip Yang * Querying of accessibility attributes works by initializing the 67640ce74d1SPhilip Yang * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the 67740ce74d1SPhilip Yang * GPUID being queried. Multiple attributes can be given to allow 67840ce74d1SPhilip Yang * querying multiple GPUIDs. The ioctl function overwrites the 67940ce74d1SPhilip Yang * attribute type to indicate the access for the specified GPU. 68040ce74d1SPhilip Yang */ 68140ce74d1SPhilip Yang struct kfd_ioctl_svm_args { 68240ce74d1SPhilip Yang __u64 start_addr; 68340ce74d1SPhilip Yang __u64 size; 68440ce74d1SPhilip Yang __u32 op; 68540ce74d1SPhilip Yang __u32 nattr; 68640ce74d1SPhilip Yang /* Variable length array of attributes */ 68779aa0367SFelix Kuehling struct kfd_ioctl_svm_attribute attrs[]; 68840ce74d1SPhilip Yang }; 68940ce74d1SPhilip Yang 6900f7b5c44SAlex Sierra /** 6910f7b5c44SAlex Sierra * kfd_ioctl_set_xnack_mode_args - Arguments for set_xnack_mode 6920f7b5c44SAlex Sierra * 6930f7b5c44SAlex Sierra * @xnack_enabled: [in/out] Whether to enable XNACK mode for this process 6940f7b5c44SAlex Sierra * 6950f7b5c44SAlex Sierra * @xnack_enabled indicates whether recoverable page faults should be 6960f7b5c44SAlex Sierra * enabled for the current process. 0 means disabled, positive means 6970f7b5c44SAlex Sierra * enabled, negative means leave unchanged. If enabled, virtual address 6980f7b5c44SAlex Sierra * translations on GFXv9 and later AMD GPUs can return XNACK and retry 6990f7b5c44SAlex Sierra * the access until a valid PTE is available. This is used to implement 7000f7b5c44SAlex Sierra * device page faults. 7010f7b5c44SAlex Sierra * 7020f7b5c44SAlex Sierra * On output, @xnack_enabled returns the (new) current mode (0 or 7030f7b5c44SAlex Sierra * positive). Therefore, a negative input value can be used to query 7040f7b5c44SAlex Sierra * the current mode without changing it. 7050f7b5c44SAlex Sierra * 7060f7b5c44SAlex Sierra * The XNACK mode fundamentally changes the way SVM managed memory works 7070f7b5c44SAlex Sierra * in the driver, with subtle effects on application performance and 7080f7b5c44SAlex Sierra * functionality. 7090f7b5c44SAlex Sierra * 7100f7b5c44SAlex Sierra * Enabling XNACK mode requires shader programs to be compiled 7110f7b5c44SAlex Sierra * differently. Furthermore, not all GPUs support changing the mode 7120f7b5c44SAlex Sierra * per-process. Therefore changing the mode is only allowed while no 7130f7b5c44SAlex Sierra * user mode queues exist in the process. This ensure that no shader 7140f7b5c44SAlex Sierra * code is running that may be compiled for the wrong mode. And GPUs 7150f7b5c44SAlex Sierra * that cannot change to the requested mode will prevent the XNACK 7160f7b5c44SAlex Sierra * mode from occurring. All GPUs used by the process must be in the 7170f7b5c44SAlex Sierra * same XNACK mode. 7180f7b5c44SAlex Sierra * 7190f7b5c44SAlex Sierra * GFXv8 or older GPUs do not support 48 bit virtual addresses or SVM. 7200f7b5c44SAlex Sierra * Therefore those GPUs are not considered for the XNACK mode switch. 7210f7b5c44SAlex Sierra * 7220f7b5c44SAlex Sierra * Return: 0 on success, -errno on failure 7230f7b5c44SAlex Sierra */ 7240f7b5c44SAlex Sierra struct kfd_ioctl_set_xnack_mode_args { 7250f7b5c44SAlex Sierra __s32 xnack_enabled; 7260f7b5c44SAlex Sierra }; 7270f7b5c44SAlex Sierra 728b81c55dbSOded Gabbay #define AMDKFD_IOCTL_BASE 'K' 729b81c55dbSOded Gabbay #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 730b81c55dbSOded Gabbay #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 731b81c55dbSOded Gabbay #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type) 732b81c55dbSOded Gabbay #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) 733b7facbaeSOded Gabbay 734b81c55dbSOded Gabbay #define AMDKFD_IOC_GET_VERSION \ 735b81c55dbSOded Gabbay AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) 736b7facbaeSOded Gabbay 737b81c55dbSOded Gabbay #define AMDKFD_IOC_CREATE_QUEUE \ 738b81c55dbSOded Gabbay AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) 739b7facbaeSOded Gabbay 740b81c55dbSOded Gabbay #define AMDKFD_IOC_DESTROY_QUEUE \ 741b81c55dbSOded Gabbay AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) 742b7facbaeSOded Gabbay 743b81c55dbSOded Gabbay #define AMDKFD_IOC_SET_MEMORY_POLICY \ 744b81c55dbSOded Gabbay AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) 745b7facbaeSOded Gabbay 746b81c55dbSOded Gabbay #define AMDKFD_IOC_GET_CLOCK_COUNTERS \ 747b81c55dbSOded Gabbay AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) 748b7facbaeSOded Gabbay 749b81c55dbSOded Gabbay #define AMDKFD_IOC_GET_PROCESS_APERTURES \ 750b81c55dbSOded Gabbay AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) 751b7facbaeSOded Gabbay 752b81c55dbSOded Gabbay #define AMDKFD_IOC_UPDATE_QUEUE \ 753b81c55dbSOded Gabbay AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 754b81c55dbSOded Gabbay 75529a5d3ebSAndrew Lewycky #define AMDKFD_IOC_CREATE_EVENT \ 75629a5d3ebSAndrew Lewycky AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) 75729a5d3ebSAndrew Lewycky 75829a5d3ebSAndrew Lewycky #define AMDKFD_IOC_DESTROY_EVENT \ 75929a5d3ebSAndrew Lewycky AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) 76029a5d3ebSAndrew Lewycky 76129a5d3ebSAndrew Lewycky #define AMDKFD_IOC_SET_EVENT \ 76229a5d3ebSAndrew Lewycky AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) 76329a5d3ebSAndrew Lewycky 76429a5d3ebSAndrew Lewycky #define AMDKFD_IOC_RESET_EVENT \ 76529a5d3ebSAndrew Lewycky AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) 76629a5d3ebSAndrew Lewycky 76729a5d3ebSAndrew Lewycky #define AMDKFD_IOC_WAIT_EVENTS \ 76829a5d3ebSAndrew Lewycky AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) 76929a5d3ebSAndrew Lewycky 7705bdd3eb2SMukul Joshi #define AMDKFD_IOC_DBG_REGISTER_DEPRECATED \ 771aef11009SYair Shachar AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) 772aef11009SYair Shachar 7735bdd3eb2SMukul Joshi #define AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED \ 774aef11009SYair Shachar AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) 775aef11009SYair Shachar 7765bdd3eb2SMukul Joshi #define AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED \ 777aef11009SYair Shachar AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) 778aef11009SYair Shachar 7795bdd3eb2SMukul Joshi #define AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED \ 780aef11009SYair Shachar AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) 781aef11009SYair Shachar 7826a1c9510SMoses Reuben #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \ 7836a1c9510SMoses Reuben AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) 7846a1c9510SMoses Reuben 7855d71dbc3SYong Zhao #define AMDKFD_IOC_GET_TILE_CONFIG \ 7865d71dbc3SYong Zhao AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) 7875d71dbc3SYong Zhao 788d7b9bd22SFelix Kuehling #define AMDKFD_IOC_SET_TRAP_HANDLER \ 789d7b9bd22SFelix Kuehling AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) 790d7b9bd22SFelix Kuehling 791c7bcbfa4SFelix Kuehling #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \ 792c7bcbfa4SFelix Kuehling AMDKFD_IOWR(0x14, \ 793c7bcbfa4SFelix Kuehling struct kfd_ioctl_get_process_apertures_new_args) 794c7bcbfa4SFelix Kuehling 7955ec7e028SFelix Kuehling #define AMDKFD_IOC_ACQUIRE_VM \ 7965ec7e028SFelix Kuehling AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args) 7975ec7e028SFelix Kuehling 7985ec7e028SFelix Kuehling #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \ 7995ec7e028SFelix Kuehling AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args) 8005ec7e028SFelix Kuehling 8015ec7e028SFelix Kuehling #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \ 8025ec7e028SFelix Kuehling AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args) 8035ec7e028SFelix Kuehling 8045ec7e028SFelix Kuehling #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \ 8055ec7e028SFelix Kuehling AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args) 8065ec7e028SFelix Kuehling 8075ec7e028SFelix Kuehling #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \ 8085ec7e028SFelix Kuehling AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args) 8095ec7e028SFelix Kuehling 810a7fe68a1SFelix Kuehling #define AMDKFD_IOC_SET_CU_MASK \ 811a7fe68a1SFelix Kuehling AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) 812a7fe68a1SFelix Kuehling 8135df099e8SJay Cornwall #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \ 8145df099e8SJay Cornwall AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) 8155df099e8SJay Cornwall 8161dde0ea9SFelix Kuehling #define AMDKFD_IOC_GET_DMABUF_INFO \ 8171dde0ea9SFelix Kuehling AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args) 8181dde0ea9SFelix Kuehling 8191dde0ea9SFelix Kuehling #define AMDKFD_IOC_IMPORT_DMABUF \ 8201dde0ea9SFelix Kuehling AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) 8211dde0ea9SFelix Kuehling 8225bb4b78bSOak Zeng #define AMDKFD_IOC_ALLOC_QUEUE_GWS \ 8235bb4b78bSOak Zeng AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args) 8245bb4b78bSOak Zeng 825938a0650SAmber Lin #define AMDKFD_IOC_SMI_EVENTS \ 826938a0650SAmber Lin AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args) 827938a0650SAmber Lin 82840ce74d1SPhilip Yang #define AMDKFD_IOC_SVM AMDKFD_IOWR(0x20, struct kfd_ioctl_svm_args) 82940ce74d1SPhilip Yang 8300f7b5c44SAlex Sierra #define AMDKFD_IOC_SET_XNACK_MODE \ 8310f7b5c44SAlex Sierra AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args) 8320f7b5c44SAlex Sierra 83336988070SRajneesh Bhardwaj #define AMDKFD_IOC_CRIU_OP \ 83436988070SRajneesh Bhardwaj AMDKFD_IOWR(0x22, struct kfd_ioctl_criu_args) 83536988070SRajneesh Bhardwaj 836*9731dd4cSDaniel Phillips #define AMDKFD_IOC_AVAILABLE_MEMORY \ 837*9731dd4cSDaniel Phillips AMDKFD_IOWR(0x23, struct kfd_ioctl_get_available_memory_args) 838*9731dd4cSDaniel Phillips 839b81c55dbSOded Gabbay #define AMDKFD_COMMAND_START 0x01 840*9731dd4cSDaniel Phillips #define AMDKFD_COMMAND_END 0x24 841b7facbaeSOded Gabbay 842b7facbaeSOded Gabbay #endif 843