1b7facbaeSOded Gabbay /* 2b7facbaeSOded Gabbay * Copyright 2014 Advanced Micro Devices, Inc. 3b7facbaeSOded Gabbay * 4b7facbaeSOded Gabbay * Permission is hereby granted, free of charge, to any person obtaining a 5b7facbaeSOded Gabbay * copy of this software and associated documentation files (the "Software"), 6b7facbaeSOded Gabbay * to deal in the Software without restriction, including without limitation 7b7facbaeSOded Gabbay * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8b7facbaeSOded Gabbay * and/or sell copies of the Software, and to permit persons to whom the 9b7facbaeSOded Gabbay * Software is furnished to do so, subject to the following conditions: 10b7facbaeSOded Gabbay * 11b7facbaeSOded Gabbay * The above copyright notice and this permission notice shall be included in 12b7facbaeSOded Gabbay * all copies or substantial portions of the Software. 13b7facbaeSOded Gabbay * 14b7facbaeSOded Gabbay * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15b7facbaeSOded Gabbay * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16b7facbaeSOded Gabbay * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17b7facbaeSOded Gabbay * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18b7facbaeSOded Gabbay * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19b7facbaeSOded Gabbay * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20b7facbaeSOded Gabbay * OTHER DEALINGS IN THE SOFTWARE. 21b7facbaeSOded Gabbay */ 22b7facbaeSOded Gabbay 23b7facbaeSOded Gabbay #ifndef KFD_IOCTL_H_INCLUDED 24b7facbaeSOded Gabbay #define KFD_IOCTL_H_INCLUDED 25b7facbaeSOded Gabbay 26b7facbaeSOded Gabbay #include <linux/types.h> 27b7facbaeSOded Gabbay #include <linux/ioctl.h> 28b7facbaeSOded Gabbay 29b7facbaeSOded Gabbay #define KFD_IOCTL_MAJOR_VERSION 1 30*29a5d3ebSAndrew Lewycky #define KFD_IOCTL_MINOR_VERSION 1 31b7facbaeSOded Gabbay 32b7facbaeSOded Gabbay struct kfd_ioctl_get_version_args { 33b7facbaeSOded Gabbay uint32_t major_version; /* from KFD */ 34b7facbaeSOded Gabbay uint32_t minor_version; /* from KFD */ 35b7facbaeSOded Gabbay }; 36b7facbaeSOded Gabbay 37b7facbaeSOded Gabbay /* For kfd_ioctl_create_queue_args.queue_type. */ 38b7facbaeSOded Gabbay #define KFD_IOC_QUEUE_TYPE_COMPUTE 0 39b7facbaeSOded Gabbay #define KFD_IOC_QUEUE_TYPE_SDMA 1 40b7facbaeSOded Gabbay #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2 41b7facbaeSOded Gabbay 42b7facbaeSOded Gabbay #define KFD_MAX_QUEUE_PERCENTAGE 100 43b7facbaeSOded Gabbay #define KFD_MAX_QUEUE_PRIORITY 15 44b7facbaeSOded Gabbay 45b7facbaeSOded Gabbay struct kfd_ioctl_create_queue_args { 46b7facbaeSOded Gabbay uint64_t ring_base_address; /* to KFD */ 47b7facbaeSOded Gabbay uint64_t write_pointer_address; /* from KFD */ 48b7facbaeSOded Gabbay uint64_t read_pointer_address; /* from KFD */ 49b7facbaeSOded Gabbay uint64_t doorbell_offset; /* from KFD */ 50b7facbaeSOded Gabbay 51b7facbaeSOded Gabbay uint32_t ring_size; /* to KFD */ 52b7facbaeSOded Gabbay uint32_t gpu_id; /* to KFD */ 53b7facbaeSOded Gabbay uint32_t queue_type; /* to KFD */ 54b7facbaeSOded Gabbay uint32_t queue_percentage; /* to KFD */ 55b7facbaeSOded Gabbay uint32_t queue_priority; /* to KFD */ 56b7facbaeSOded Gabbay uint32_t queue_id; /* from KFD */ 57b7facbaeSOded Gabbay 58b7facbaeSOded Gabbay uint64_t eop_buffer_address; /* to KFD */ 59b7facbaeSOded Gabbay uint64_t eop_buffer_size; /* to KFD */ 60b7facbaeSOded Gabbay uint64_t ctx_save_restore_address; /* to KFD */ 61b7facbaeSOded Gabbay uint64_t ctx_save_restore_size; /* to KFD */ 62b7facbaeSOded Gabbay }; 63b7facbaeSOded Gabbay 64b7facbaeSOded Gabbay struct kfd_ioctl_destroy_queue_args { 65b7facbaeSOded Gabbay uint32_t queue_id; /* to KFD */ 66b7facbaeSOded Gabbay uint32_t pad; 67b7facbaeSOded Gabbay }; 68b7facbaeSOded Gabbay 69b7facbaeSOded Gabbay struct kfd_ioctl_update_queue_args { 70b7facbaeSOded Gabbay uint64_t ring_base_address; /* to KFD */ 71b7facbaeSOded Gabbay 72b7facbaeSOded Gabbay uint32_t queue_id; /* to KFD */ 73b7facbaeSOded Gabbay uint32_t ring_size; /* to KFD */ 74b7facbaeSOded Gabbay uint32_t queue_percentage; /* to KFD */ 75b7facbaeSOded Gabbay uint32_t queue_priority; /* to KFD */ 76b7facbaeSOded Gabbay }; 77b7facbaeSOded Gabbay 78b7facbaeSOded Gabbay /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ 79b7facbaeSOded Gabbay #define KFD_IOC_CACHE_POLICY_COHERENT 0 80b7facbaeSOded Gabbay #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 81b7facbaeSOded Gabbay 82b7facbaeSOded Gabbay struct kfd_ioctl_set_memory_policy_args { 83b7facbaeSOded Gabbay uint64_t alternate_aperture_base; /* to KFD */ 84b7facbaeSOded Gabbay uint64_t alternate_aperture_size; /* to KFD */ 85b7facbaeSOded Gabbay 86b7facbaeSOded Gabbay uint32_t gpu_id; /* to KFD */ 87b7facbaeSOded Gabbay uint32_t default_policy; /* to KFD */ 88b7facbaeSOded Gabbay uint32_t alternate_policy; /* to KFD */ 89b7facbaeSOded Gabbay uint32_t pad; 90b7facbaeSOded Gabbay }; 91b7facbaeSOded Gabbay 92b7facbaeSOded Gabbay /* 93b7facbaeSOded Gabbay * All counters are monotonic. They are used for profiling of compute jobs. 94b7facbaeSOded Gabbay * The profiling is done by userspace. 95b7facbaeSOded Gabbay * 96b7facbaeSOded Gabbay * In case of GPU reset, the counter should not be affected. 97b7facbaeSOded Gabbay */ 98b7facbaeSOded Gabbay 99b7facbaeSOded Gabbay struct kfd_ioctl_get_clock_counters_args { 100b7facbaeSOded Gabbay uint64_t gpu_clock_counter; /* from KFD */ 101b7facbaeSOded Gabbay uint64_t cpu_clock_counter; /* from KFD */ 102b7facbaeSOded Gabbay uint64_t system_clock_counter; /* from KFD */ 103b7facbaeSOded Gabbay uint64_t system_clock_freq; /* from KFD */ 104b7facbaeSOded Gabbay 105b7facbaeSOded Gabbay uint32_t gpu_id; /* to KFD */ 106b7facbaeSOded Gabbay uint32_t pad; 107b7facbaeSOded Gabbay }; 108b7facbaeSOded Gabbay 109b7facbaeSOded Gabbay #define NUM_OF_SUPPORTED_GPUS 7 110b7facbaeSOded Gabbay 111b7facbaeSOded Gabbay struct kfd_process_device_apertures { 112b7facbaeSOded Gabbay uint64_t lds_base; /* from KFD */ 113b7facbaeSOded Gabbay uint64_t lds_limit; /* from KFD */ 114b7facbaeSOded Gabbay uint64_t scratch_base; /* from KFD */ 115b7facbaeSOded Gabbay uint64_t scratch_limit; /* from KFD */ 116b7facbaeSOded Gabbay uint64_t gpuvm_base; /* from KFD */ 117b7facbaeSOded Gabbay uint64_t gpuvm_limit; /* from KFD */ 118b7facbaeSOded Gabbay uint32_t gpu_id; /* from KFD */ 119b7facbaeSOded Gabbay uint32_t pad; 120b7facbaeSOded Gabbay }; 121b7facbaeSOded Gabbay 122b7facbaeSOded Gabbay struct kfd_ioctl_get_process_apertures_args { 123b7facbaeSOded Gabbay struct kfd_process_device_apertures 124b7facbaeSOded Gabbay process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */ 125b7facbaeSOded Gabbay 126b7facbaeSOded Gabbay /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */ 127b7facbaeSOded Gabbay uint32_t num_of_nodes; 128b7facbaeSOded Gabbay uint32_t pad; 129b7facbaeSOded Gabbay }; 130b7facbaeSOded Gabbay 131*29a5d3ebSAndrew Lewycky /* Matching HSA_EVENTTYPE */ 132*29a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_SIGNAL 0 133*29a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_NODECHANGE 1 134*29a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_DEVICESTATECHANGE 2 135*29a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_HW_EXCEPTION 3 136*29a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_SYSTEM_EVENT 4 137*29a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_DEBUG_EVENT 5 138*29a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_PROFILE_EVENT 6 139*29a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_QUEUE_EVENT 7 140*29a5d3ebSAndrew Lewycky #define KFD_IOC_EVENT_MEMORY 8 141*29a5d3ebSAndrew Lewycky 142*29a5d3ebSAndrew Lewycky #define KFD_IOC_WAIT_RESULT_COMPLETE 0 143*29a5d3ebSAndrew Lewycky #define KFD_IOC_WAIT_RESULT_TIMEOUT 1 144*29a5d3ebSAndrew Lewycky #define KFD_IOC_WAIT_RESULT_FAIL 2 145*29a5d3ebSAndrew Lewycky 146*29a5d3ebSAndrew Lewycky #define KFD_SIGNAL_EVENT_LIMIT 256 147*29a5d3ebSAndrew Lewycky 148*29a5d3ebSAndrew Lewycky struct kfd_ioctl_create_event_args { 149*29a5d3ebSAndrew Lewycky uint64_t event_page_offset; /* from KFD */ 150*29a5d3ebSAndrew Lewycky uint32_t event_trigger_data; /* from KFD - signal events only */ 151*29a5d3ebSAndrew Lewycky uint32_t event_type; /* to KFD */ 152*29a5d3ebSAndrew Lewycky uint32_t auto_reset; /* to KFD */ 153*29a5d3ebSAndrew Lewycky uint32_t node_id; /* to KFD - only valid for certain 154*29a5d3ebSAndrew Lewycky event types */ 155*29a5d3ebSAndrew Lewycky uint32_t event_id; /* from KFD */ 156*29a5d3ebSAndrew Lewycky uint32_t event_slot_index; /* from KFD */ 157*29a5d3ebSAndrew Lewycky }; 158*29a5d3ebSAndrew Lewycky 159*29a5d3ebSAndrew Lewycky struct kfd_ioctl_destroy_event_args { 160*29a5d3ebSAndrew Lewycky uint32_t event_id; /* to KFD */ 161*29a5d3ebSAndrew Lewycky uint32_t pad; 162*29a5d3ebSAndrew Lewycky }; 163*29a5d3ebSAndrew Lewycky 164*29a5d3ebSAndrew Lewycky struct kfd_ioctl_set_event_args { 165*29a5d3ebSAndrew Lewycky uint32_t event_id; /* to KFD */ 166*29a5d3ebSAndrew Lewycky uint32_t pad; 167*29a5d3ebSAndrew Lewycky }; 168*29a5d3ebSAndrew Lewycky 169*29a5d3ebSAndrew Lewycky struct kfd_ioctl_reset_event_args { 170*29a5d3ebSAndrew Lewycky uint32_t event_id; /* to KFD */ 171*29a5d3ebSAndrew Lewycky uint32_t pad; 172*29a5d3ebSAndrew Lewycky }; 173*29a5d3ebSAndrew Lewycky 174*29a5d3ebSAndrew Lewycky struct kfd_memory_exception_failure { 175*29a5d3ebSAndrew Lewycky uint32_t NotPresent; /* Page not present or supervisor privilege */ 176*29a5d3ebSAndrew Lewycky uint32_t ReadOnly; /* Write access to a read-only page */ 177*29a5d3ebSAndrew Lewycky uint32_t NoExecute; /* Execute access to a page marked NX */ 178*29a5d3ebSAndrew Lewycky uint32_t pad; 179*29a5d3ebSAndrew Lewycky }; 180*29a5d3ebSAndrew Lewycky 181*29a5d3ebSAndrew Lewycky /* memory exception data*/ 182*29a5d3ebSAndrew Lewycky struct kfd_hsa_memory_exception_data { 183*29a5d3ebSAndrew Lewycky struct kfd_memory_exception_failure failure; 184*29a5d3ebSAndrew Lewycky uint64_t va; 185*29a5d3ebSAndrew Lewycky uint32_t gpu_id; 186*29a5d3ebSAndrew Lewycky uint32_t pad; 187*29a5d3ebSAndrew Lewycky }; 188*29a5d3ebSAndrew Lewycky 189*29a5d3ebSAndrew Lewycky /* Event data*/ 190*29a5d3ebSAndrew Lewycky struct kfd_event_data { 191*29a5d3ebSAndrew Lewycky union { 192*29a5d3ebSAndrew Lewycky struct kfd_hsa_memory_exception_data memory_exception_data; 193*29a5d3ebSAndrew Lewycky }; /* From KFD */ 194*29a5d3ebSAndrew Lewycky uint64_t kfd_event_data_ext; /* pointer to an extension structure 195*29a5d3ebSAndrew Lewycky for future exception types */ 196*29a5d3ebSAndrew Lewycky uint32_t event_id; /* to KFD */ 197*29a5d3ebSAndrew Lewycky uint32_t pad; 198*29a5d3ebSAndrew Lewycky }; 199*29a5d3ebSAndrew Lewycky 200*29a5d3ebSAndrew Lewycky struct kfd_ioctl_wait_events_args { 201*29a5d3ebSAndrew Lewycky uint64_t events_ptr; /* to KFD */ 202*29a5d3ebSAndrew Lewycky uint32_t num_events; /* to KFD */ 203*29a5d3ebSAndrew Lewycky uint32_t wait_for_all; /* to KFD */ 204*29a5d3ebSAndrew Lewycky uint32_t timeout; /* to KFD */ 205*29a5d3ebSAndrew Lewycky uint32_t wait_result; /* from KFD */ 206*29a5d3ebSAndrew Lewycky }; 207*29a5d3ebSAndrew Lewycky 208b81c55dbSOded Gabbay #define AMDKFD_IOCTL_BASE 'K' 209b81c55dbSOded Gabbay #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 210b81c55dbSOded Gabbay #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 211b81c55dbSOded Gabbay #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type) 212b81c55dbSOded Gabbay #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) 213b7facbaeSOded Gabbay 214b81c55dbSOded Gabbay #define AMDKFD_IOC_GET_VERSION \ 215b81c55dbSOded Gabbay AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) 216b7facbaeSOded Gabbay 217b81c55dbSOded Gabbay #define AMDKFD_IOC_CREATE_QUEUE \ 218b81c55dbSOded Gabbay AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) 219b7facbaeSOded Gabbay 220b81c55dbSOded Gabbay #define AMDKFD_IOC_DESTROY_QUEUE \ 221b81c55dbSOded Gabbay AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) 222b7facbaeSOded Gabbay 223b81c55dbSOded Gabbay #define AMDKFD_IOC_SET_MEMORY_POLICY \ 224b81c55dbSOded Gabbay AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) 225b7facbaeSOded Gabbay 226b81c55dbSOded Gabbay #define AMDKFD_IOC_GET_CLOCK_COUNTERS \ 227b81c55dbSOded Gabbay AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) 228b7facbaeSOded Gabbay 229b81c55dbSOded Gabbay #define AMDKFD_IOC_GET_PROCESS_APERTURES \ 230b81c55dbSOded Gabbay AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) 231b7facbaeSOded Gabbay 232b81c55dbSOded Gabbay #define AMDKFD_IOC_UPDATE_QUEUE \ 233b81c55dbSOded Gabbay AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 234b81c55dbSOded Gabbay 235*29a5d3ebSAndrew Lewycky #define AMDKFD_IOC_CREATE_EVENT \ 236*29a5d3ebSAndrew Lewycky AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) 237*29a5d3ebSAndrew Lewycky 238*29a5d3ebSAndrew Lewycky #define AMDKFD_IOC_DESTROY_EVENT \ 239*29a5d3ebSAndrew Lewycky AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) 240*29a5d3ebSAndrew Lewycky 241*29a5d3ebSAndrew Lewycky #define AMDKFD_IOC_SET_EVENT \ 242*29a5d3ebSAndrew Lewycky AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) 243*29a5d3ebSAndrew Lewycky 244*29a5d3ebSAndrew Lewycky #define AMDKFD_IOC_RESET_EVENT \ 245*29a5d3ebSAndrew Lewycky AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) 246*29a5d3ebSAndrew Lewycky 247*29a5d3ebSAndrew Lewycky #define AMDKFD_IOC_WAIT_EVENTS \ 248*29a5d3ebSAndrew Lewycky AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) 249*29a5d3ebSAndrew Lewycky 250b81c55dbSOded Gabbay #define AMDKFD_COMMAND_START 0x01 251*29a5d3ebSAndrew Lewycky #define AMDKFD_COMMAND_END 0x0D 252b7facbaeSOded Gabbay 253b7facbaeSOded Gabbay #endif 254