125905f60STony Luck /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */ 2bfe1d560SDave Jiang /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3bfe1d560SDave Jiang #ifndef _USR_IDXD_H_ 4bfe1d560SDave Jiang #define _USR_IDXD_H_ 5bfe1d560SDave Jiang 6bfe1d560SDave Jiang #ifdef __KERNEL__ 7bfe1d560SDave Jiang #include <linux/types.h> 8bfe1d560SDave Jiang #else 9bfe1d560SDave Jiang #include <stdint.h> 10bfe1d560SDave Jiang #endif 11bfe1d560SDave Jiang 12125d1037SDave Jiang /* Driver command error status */ 13125d1037SDave Jiang enum idxd_scmd_stat { 14125d1037SDave Jiang IDXD_SCMD_DEV_ENABLED = 0x80000010, 15125d1037SDave Jiang IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020, 16125d1037SDave Jiang IDXD_SCMD_WQ_ENABLED = 0x80000021, 17125d1037SDave Jiang IDXD_SCMD_DEV_DMA_ERR = 0x80020000, 18125d1037SDave Jiang IDXD_SCMD_WQ_NO_GRP = 0x80030000, 19125d1037SDave Jiang IDXD_SCMD_WQ_NO_NAME = 0x80040000, 20125d1037SDave Jiang IDXD_SCMD_WQ_NO_SVM = 0x80050000, 21125d1037SDave Jiang IDXD_SCMD_WQ_NO_THRESH = 0x80060000, 22125d1037SDave Jiang IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000, 23125d1037SDave Jiang IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000, 24125d1037SDave Jiang IDXD_SCMD_PERCPU_ERR = 0x80090000, 25125d1037SDave Jiang IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000, 26125d1037SDave Jiang IDXD_SCMD_CDEV_ERR = 0x800b0000, 27125d1037SDave Jiang IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000, 28125d1037SDave Jiang IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000, 29125d1037SDave Jiang IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, 30d8071323SDave Jiang IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, 31403a2e23SDave Jiang IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, 320ec8ce07SFenghua Yu IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000, 33244da66cSDave Jiang IDXD_SCMD_DEV_EVL_ERR = 0x80120000, 34*7af1e0acSDave Jiang IDXD_SCMD_WQ_NO_DRV_NAME = 0x80200000, 35125d1037SDave Jiang }; 36125d1037SDave Jiang 37125d1037SDave Jiang #define IDXD_SCMD_SOFTERR_MASK 0x80000000 38125d1037SDave Jiang #define IDXD_SCMD_SOFTERR_SHIFT 16 39125d1037SDave Jiang 40bfe1d560SDave Jiang /* Descriptor flags */ 41bfe1d560SDave Jiang #define IDXD_OP_FLAG_FENCE 0x0001 42bfe1d560SDave Jiang #define IDXD_OP_FLAG_BOF 0x0002 43bfe1d560SDave Jiang #define IDXD_OP_FLAG_CRAV 0x0004 44bfe1d560SDave Jiang #define IDXD_OP_FLAG_RCR 0x0008 45bfe1d560SDave Jiang #define IDXD_OP_FLAG_RCI 0x0010 46bfe1d560SDave Jiang #define IDXD_OP_FLAG_CRSTS 0x0020 47bfe1d560SDave Jiang #define IDXD_OP_FLAG_CR 0x0080 48bfe1d560SDave Jiang #define IDXD_OP_FLAG_CC 0x0100 49bfe1d560SDave Jiang #define IDXD_OP_FLAG_ADDR1_TCS 0x0200 50bfe1d560SDave Jiang #define IDXD_OP_FLAG_ADDR2_TCS 0x0400 51bfe1d560SDave Jiang #define IDXD_OP_FLAG_ADDR3_TCS 0x0800 52bfe1d560SDave Jiang #define IDXD_OP_FLAG_CR_TCS 0x1000 53bfe1d560SDave Jiang #define IDXD_OP_FLAG_STORD 0x2000 54bfe1d560SDave Jiang #define IDXD_OP_FLAG_DRDBK 0x4000 55bfe1d560SDave Jiang #define IDXD_OP_FLAG_DSTS 0x8000 56bfe1d560SDave Jiang 57f25b4638SDave Jiang /* IAX */ 58f25b4638SDave Jiang #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 592d7991feSDave Jiang #define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000 602d7991feSDave Jiang #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000 612d7991feSDave Jiang #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000 622d7991feSDave Jiang #define IDXD_OP_FLAG_SRC2_STS 0x100000 632d7991feSDave Jiang #define IDXD_OP_FLAG_CRC_RFC3720 0x200000 64f25b4638SDave Jiang 65bfe1d560SDave Jiang /* Opcode */ 66bfe1d560SDave Jiang enum dsa_opcode { 67bfe1d560SDave Jiang DSA_OPCODE_NOOP = 0, 68bfe1d560SDave Jiang DSA_OPCODE_BATCH, 69bfe1d560SDave Jiang DSA_OPCODE_DRAIN, 70bfe1d560SDave Jiang DSA_OPCODE_MEMMOVE, 71bfe1d560SDave Jiang DSA_OPCODE_MEMFILL, 72bfe1d560SDave Jiang DSA_OPCODE_COMPARE, 73bfe1d560SDave Jiang DSA_OPCODE_COMPVAL, 74bfe1d560SDave Jiang DSA_OPCODE_CR_DELTA, 75bfe1d560SDave Jiang DSA_OPCODE_AP_DELTA, 76bfe1d560SDave Jiang DSA_OPCODE_DUALCAST, 776fec8938SFenghua Yu DSA_OPCODE_TRANSL_FETCH, 78bfe1d560SDave Jiang DSA_OPCODE_CRCGEN = 0x10, 79bfe1d560SDave Jiang DSA_OPCODE_COPY_CRC, 80bfe1d560SDave Jiang DSA_OPCODE_DIF_CHECK, 81bfe1d560SDave Jiang DSA_OPCODE_DIF_INS, 82bfe1d560SDave Jiang DSA_OPCODE_DIF_STRP, 83bfe1d560SDave Jiang DSA_OPCODE_DIF_UPDT, 8412bbc2c2SFenghua Yu DSA_OPCODE_DIX_GEN = 0x17, 85bfe1d560SDave Jiang DSA_OPCODE_CFLUSH = 0x20, 86bfe1d560SDave Jiang }; 87bfe1d560SDave Jiang 88f25b4638SDave Jiang enum iax_opcode { 89f25b4638SDave Jiang IAX_OPCODE_NOOP = 0, 90f25b4638SDave Jiang IAX_OPCODE_DRAIN = 2, 91f25b4638SDave Jiang IAX_OPCODE_MEMMOVE, 92f25b4638SDave Jiang IAX_OPCODE_DECOMPRESS = 0x42, 93f25b4638SDave Jiang IAX_OPCODE_COMPRESS, 942d7991feSDave Jiang IAX_OPCODE_CRC64, 952d7991feSDave Jiang IAX_OPCODE_ZERO_DECOMP_32 = 0x48, 962d7991feSDave Jiang IAX_OPCODE_ZERO_DECOMP_16, 97d0b55afaSFenghua Yu IAX_OPCODE_ZERO_COMP_32 = 0x4c, 98d0b55afaSFenghua Yu IAX_OPCODE_ZERO_COMP_16, 992d7991feSDave Jiang IAX_OPCODE_SCAN = 0x50, 1002d7991feSDave Jiang IAX_OPCODE_SET_MEMBER, 1012d7991feSDave Jiang IAX_OPCODE_EXTRACT, 1022d7991feSDave Jiang IAX_OPCODE_SELECT, 1032d7991feSDave Jiang IAX_OPCODE_RLE_BURST, 104d0b55afaSFenghua Yu IAX_OPCODE_FIND_UNIQUE, 1052d7991feSDave Jiang IAX_OPCODE_EXPAND, 106f25b4638SDave Jiang }; 107f25b4638SDave Jiang 108bfe1d560SDave Jiang /* Completion record status */ 109bfe1d560SDave Jiang enum dsa_completion_status { 110bfe1d560SDave Jiang DSA_COMP_NONE = 0, 111bfe1d560SDave Jiang DSA_COMP_SUCCESS, 112bfe1d560SDave Jiang DSA_COMP_SUCCESS_PRED, 113bfe1d560SDave Jiang DSA_COMP_PAGE_FAULT_NOBOF, 114bfe1d560SDave Jiang DSA_COMP_PAGE_FAULT_IR, 115bfe1d560SDave Jiang DSA_COMP_BATCH_FAIL, 116bfe1d560SDave Jiang DSA_COMP_BATCH_PAGE_FAULT, 117bfe1d560SDave Jiang DSA_COMP_DR_OFFSET_NOINC, 118bfe1d560SDave Jiang DSA_COMP_DR_OFFSET_ERANGE, 119bfe1d560SDave Jiang DSA_COMP_DIF_ERR, 120bfe1d560SDave Jiang DSA_COMP_BAD_OPCODE = 0x10, 121bfe1d560SDave Jiang DSA_COMP_INVALID_FLAGS, 122bfe1d560SDave Jiang DSA_COMP_NOZERO_RESERVE, 123bfe1d560SDave Jiang DSA_COMP_XFER_ERANGE, 124bfe1d560SDave Jiang DSA_COMP_DESC_CNT_ERANGE, 125bfe1d560SDave Jiang DSA_COMP_DR_ERANGE, 126bfe1d560SDave Jiang DSA_COMP_OVERLAP_BUFFERS, 127bfe1d560SDave Jiang DSA_COMP_DCAST_ERR, 128bfe1d560SDave Jiang DSA_COMP_DESCLIST_ALIGN, 129bfe1d560SDave Jiang DSA_COMP_INT_HANDLE_INVAL, 130bfe1d560SDave Jiang DSA_COMP_CRA_XLAT, 131bfe1d560SDave Jiang DSA_COMP_CRA_ALIGN, 132bfe1d560SDave Jiang DSA_COMP_ADDR_ALIGN, 133bfe1d560SDave Jiang DSA_COMP_PRIV_BAD, 134bfe1d560SDave Jiang DSA_COMP_TRAFFIC_CLASS_CONF, 135bfe1d560SDave Jiang DSA_COMP_PFAULT_RDBA, 136bfe1d560SDave Jiang DSA_COMP_HW_ERR1, 137bfe1d560SDave Jiang DSA_COMP_HW_ERR_DRB, 138bfe1d560SDave Jiang DSA_COMP_TRANSLATION_FAIL, 139c40bd7d9SDave Jiang DSA_COMP_DRAIN_EVL = 0x26, 1402442b747SDave Jiang DSA_COMP_BATCH_EVL_ERR, 141bfe1d560SDave Jiang }; 142bfe1d560SDave Jiang 143f25b4638SDave Jiang enum iax_completion_status { 144f25b4638SDave Jiang IAX_COMP_NONE = 0, 145f25b4638SDave Jiang IAX_COMP_SUCCESS, 146f25b4638SDave Jiang IAX_COMP_PAGE_FAULT_IR = 0x04, 1472d7991feSDave Jiang IAX_COMP_ANALYTICS_ERROR = 0x0a, 148f25b4638SDave Jiang IAX_COMP_OUTBUF_OVERFLOW, 149f25b4638SDave Jiang IAX_COMP_BAD_OPCODE = 0x10, 150f25b4638SDave Jiang IAX_COMP_INVALID_FLAGS, 151f25b4638SDave Jiang IAX_COMP_NOZERO_RESERVE, 152f25b4638SDave Jiang IAX_COMP_INVALID_SIZE, 153f25b4638SDave Jiang IAX_COMP_OVERLAP_BUFFERS = 0x16, 154f25b4638SDave Jiang IAX_COMP_INT_HANDLE_INVAL = 0x19, 155f25b4638SDave Jiang IAX_COMP_CRA_XLAT, 156f25b4638SDave Jiang IAX_COMP_CRA_ALIGN, 157f25b4638SDave Jiang IAX_COMP_ADDR_ALIGN, 158f25b4638SDave Jiang IAX_COMP_PRIV_BAD, 159f25b4638SDave Jiang IAX_COMP_TRAFFIC_CLASS_CONF, 160f25b4638SDave Jiang IAX_COMP_PFAULT_RDBA, 161f25b4638SDave Jiang IAX_COMP_HW_ERR1, 162f25b4638SDave Jiang IAX_COMP_HW_ERR_DRB, 163f25b4638SDave Jiang IAX_COMP_TRANSLATION_FAIL, 164f25b4638SDave Jiang IAX_COMP_PRS_TIMEOUT, 165f25b4638SDave Jiang IAX_COMP_WATCHDOG, 166f25b4638SDave Jiang IAX_COMP_INVALID_COMP_FLAG = 0x30, 167f25b4638SDave Jiang IAX_COMP_INVALID_FILTER_FLAG, 1682d7991feSDave Jiang IAX_COMP_INVALID_INPUT_SIZE, 1692d7991feSDave Jiang IAX_COMP_INVALID_NUM_ELEMS, 1702d7991feSDave Jiang IAX_COMP_INVALID_SRC1_WIDTH, 1712d7991feSDave Jiang IAX_COMP_INVALID_INVERT_OUT, 172f25b4638SDave Jiang }; 173f25b4638SDave Jiang 174bfe1d560SDave Jiang #define DSA_COMP_STATUS_MASK 0x7f 175bfe1d560SDave Jiang #define DSA_COMP_STATUS_WRITE 0x80 1762f431ba9SDave Jiang #define DSA_COMP_STATUS(status) ((status) & DSA_COMP_STATUS_MASK) 177bfe1d560SDave Jiang 178bfe1d560SDave Jiang struct dsa_hw_desc { 179bfe1d560SDave Jiang uint32_t pasid:20; 180bfe1d560SDave Jiang uint32_t rsvd:11; 181bfe1d560SDave Jiang uint32_t priv:1; 182bfe1d560SDave Jiang uint32_t flags:24; 183bfe1d560SDave Jiang uint32_t opcode:8; 184bfe1d560SDave Jiang uint64_t completion_addr; 185bfe1d560SDave Jiang union { 186bfe1d560SDave Jiang uint64_t src_addr; 187bfe1d560SDave Jiang uint64_t rdback_addr; 188bfe1d560SDave Jiang uint64_t pattern; 1897c4a4d08STony Luck uint64_t desc_list_addr; 1909e410fe3SFenghua Yu uint64_t pattern_lower; 1916fec8938SFenghua Yu uint64_t transl_fetch_addr; 192bfe1d560SDave Jiang }; 193bfe1d560SDave Jiang union { 194bfe1d560SDave Jiang uint64_t dst_addr; 195bfe1d560SDave Jiang uint64_t rdback_addr2; 196bfe1d560SDave Jiang uint64_t src2_addr; 197bfe1d560SDave Jiang uint64_t comp_pattern; 198bfe1d560SDave Jiang }; 1997c4a4d08STony Luck union { 200bfe1d560SDave Jiang uint32_t xfer_size; 2017c4a4d08STony Luck uint32_t desc_count; 2026fec8938SFenghua Yu uint32_t region_size; 2037c4a4d08STony Luck }; 204bfe1d560SDave Jiang uint16_t int_handle; 205bfe1d560SDave Jiang uint16_t rsvd1; 206bfe1d560SDave Jiang union { 207bfe1d560SDave Jiang uint8_t expected_res; 2080b8975bdSDave Jiang /* create delta record */ 209bfe1d560SDave Jiang struct { 210bfe1d560SDave Jiang uint64_t delta_addr; 211bfe1d560SDave Jiang uint32_t max_delta_size; 2120b8975bdSDave Jiang uint32_t delt_rsvd; 2130b8975bdSDave Jiang uint8_t expected_res_mask; 214bfe1d560SDave Jiang }; 215bfe1d560SDave Jiang uint32_t delta_rec_size; 216bfe1d560SDave Jiang uint64_t dest2; 217bfe1d560SDave Jiang /* CRC */ 218bfe1d560SDave Jiang struct { 219bfe1d560SDave Jiang uint32_t crc_seed; 220bfe1d560SDave Jiang uint32_t crc_rsvd; 221bfe1d560SDave Jiang uint64_t seed_addr; 222bfe1d560SDave Jiang }; 223bfe1d560SDave Jiang /* DIF check or strip */ 224bfe1d560SDave Jiang struct { 225bfe1d560SDave Jiang uint8_t src_dif_flags; 226bfe1d560SDave Jiang uint8_t dif_chk_res; 227bfe1d560SDave Jiang uint8_t dif_chk_flags; 228bfe1d560SDave Jiang uint8_t dif_chk_res2[5]; 229bfe1d560SDave Jiang uint32_t chk_ref_tag_seed; 230bfe1d560SDave Jiang uint16_t chk_app_tag_mask; 231bfe1d560SDave Jiang uint16_t chk_app_tag_seed; 232bfe1d560SDave Jiang }; 233bfe1d560SDave Jiang /* DIF insert */ 234bfe1d560SDave Jiang struct { 235bfe1d560SDave Jiang uint8_t dif_ins_res; 236bfe1d560SDave Jiang uint8_t dest_dif_flag; 237bfe1d560SDave Jiang uint8_t dif_ins_flags; 238bfe1d560SDave Jiang uint8_t dif_ins_res2[13]; 239bfe1d560SDave Jiang uint32_t ins_ref_tag_seed; 240bfe1d560SDave Jiang uint16_t ins_app_tag_mask; 241bfe1d560SDave Jiang uint16_t ins_app_tag_seed; 242bfe1d560SDave Jiang }; 243bfe1d560SDave Jiang /* DIF update */ 244bfe1d560SDave Jiang struct { 245bfe1d560SDave Jiang uint8_t src_upd_flags; 246bfe1d560SDave Jiang uint8_t upd_dest_flags; 247bfe1d560SDave Jiang uint8_t dif_upd_flags; 248bfe1d560SDave Jiang uint8_t dif_upd_res[5]; 249bfe1d560SDave Jiang uint32_t src_ref_tag_seed; 250bfe1d560SDave Jiang uint16_t src_app_tag_mask; 251bfe1d560SDave Jiang uint16_t src_app_tag_seed; 252bfe1d560SDave Jiang uint32_t dest_ref_tag_seed; 253bfe1d560SDave Jiang uint16_t dest_app_tag_mask; 254bfe1d560SDave Jiang uint16_t dest_app_tag_seed; 255bfe1d560SDave Jiang }; 256bfe1d560SDave Jiang 2579e410fe3SFenghua Yu /* Fill */ 2589e410fe3SFenghua Yu uint64_t pattern_upper; 2599e410fe3SFenghua Yu 2606fec8938SFenghua Yu /* Translation fetch */ 2616fec8938SFenghua Yu struct { 2626fec8938SFenghua Yu uint64_t transl_fetch_res; 2636fec8938SFenghua Yu uint32_t region_stride; 2646fec8938SFenghua Yu }; 2656fec8938SFenghua Yu 26612bbc2c2SFenghua Yu /* DIX generate */ 26712bbc2c2SFenghua Yu struct { 26812bbc2c2SFenghua Yu uint8_t dix_gen_res; 26912bbc2c2SFenghua Yu uint8_t dest_dif_flags; 27012bbc2c2SFenghua Yu uint8_t dif_flags; 27112bbc2c2SFenghua Yu uint8_t dix_gen_res2[13]; 27212bbc2c2SFenghua Yu uint32_t ref_tag_seed; 27312bbc2c2SFenghua Yu uint16_t app_tag_mask; 27412bbc2c2SFenghua Yu uint16_t app_tag_seed; 27512bbc2c2SFenghua Yu }; 27612bbc2c2SFenghua Yu 277bfe1d560SDave Jiang uint8_t op_specific[24]; 278bfe1d560SDave Jiang }; 279bfe1d560SDave Jiang } __attribute__((packed)); 280bfe1d560SDave Jiang 281f25b4638SDave Jiang struct iax_hw_desc { 282f25b4638SDave Jiang uint32_t pasid:20; 283f25b4638SDave Jiang uint32_t rsvd:11; 284f25b4638SDave Jiang uint32_t priv:1; 285f25b4638SDave Jiang uint32_t flags:24; 286f25b4638SDave Jiang uint32_t opcode:8; 287f25b4638SDave Jiang uint64_t completion_addr; 288f25b4638SDave Jiang uint64_t src1_addr; 289f25b4638SDave Jiang uint64_t dst_addr; 290f25b4638SDave Jiang uint32_t src1_size; 291f25b4638SDave Jiang uint16_t int_handle; 292f25b4638SDave Jiang union { 293f25b4638SDave Jiang uint16_t compr_flags; 294f25b4638SDave Jiang uint16_t decompr_flags; 295f25b4638SDave Jiang }; 296f25b4638SDave Jiang uint64_t src2_addr; 297f25b4638SDave Jiang uint32_t max_dst_size; 298f25b4638SDave Jiang uint32_t src2_size; 299f25b4638SDave Jiang uint32_t filter_flags; 300f25b4638SDave Jiang uint32_t num_inputs; 301f25b4638SDave Jiang } __attribute__((packed)); 302f25b4638SDave Jiang 303bfe1d560SDave Jiang struct dsa_raw_desc { 304bfe1d560SDave Jiang uint64_t field[8]; 305bfe1d560SDave Jiang } __attribute__((packed)); 306bfe1d560SDave Jiang 307bfe1d560SDave Jiang /* 308bfe1d560SDave Jiang * The status field will be modified by hardware, therefore it should be 309bfe1d560SDave Jiang * volatile and prevent the compiler from optimize the read. 310bfe1d560SDave Jiang */ 311bfe1d560SDave Jiang struct dsa_completion_record { 312bfe1d560SDave Jiang volatile uint8_t status; 313bfe1d560SDave Jiang union { 314bfe1d560SDave Jiang uint8_t result; 315bfe1d560SDave Jiang uint8_t dif_status; 316bfe1d560SDave Jiang }; 3175fbe6503SDave Jiang uint8_t fault_info; 3185fbe6503SDave Jiang uint8_t rsvd; 31969269871SDave Jiang union { 320bfe1d560SDave Jiang uint32_t bytes_completed; 32169269871SDave Jiang uint32_t descs_completed; 32269269871SDave Jiang }; 323bfe1d560SDave Jiang uint64_t fault_addr; 324bfe1d560SDave Jiang union { 3251a0c02baSDave Jiang /* common record */ 3261a0c02baSDave Jiang struct { 3271a0c02baSDave Jiang uint32_t invalid_flags:24; 3281a0c02baSDave Jiang uint32_t rsvd2:8; 3291a0c02baSDave Jiang }; 3301a0c02baSDave Jiang 3314ac823e9SDave Jiang uint32_t delta_rec_size; 332dc901d98SFenghua Yu uint64_t crc_val; 333bfe1d560SDave Jiang 334bfe1d560SDave Jiang /* DIF check & strip */ 335bfe1d560SDave Jiang struct { 336bfe1d560SDave Jiang uint32_t dif_chk_ref_tag; 337bfe1d560SDave Jiang uint16_t dif_chk_app_tag_mask; 338bfe1d560SDave Jiang uint16_t dif_chk_app_tag; 339bfe1d560SDave Jiang }; 340bfe1d560SDave Jiang 341bfe1d560SDave Jiang /* DIF insert */ 342bfe1d560SDave Jiang struct { 343bfe1d560SDave Jiang uint64_t dif_ins_res; 344bfe1d560SDave Jiang uint32_t dif_ins_ref_tag; 345bfe1d560SDave Jiang uint16_t dif_ins_app_tag_mask; 346bfe1d560SDave Jiang uint16_t dif_ins_app_tag; 347bfe1d560SDave Jiang }; 348bfe1d560SDave Jiang 349bfe1d560SDave Jiang /* DIF update */ 350bfe1d560SDave Jiang struct { 351bfe1d560SDave Jiang uint32_t dif_upd_src_ref_tag; 352bfe1d560SDave Jiang uint16_t dif_upd_src_app_tag_mask; 353bfe1d560SDave Jiang uint16_t dif_upd_src_app_tag; 354bfe1d560SDave Jiang uint32_t dif_upd_dest_ref_tag; 355bfe1d560SDave Jiang uint16_t dif_upd_dest_app_tag_mask; 356bfe1d560SDave Jiang uint16_t dif_upd_dest_app_tag; 357bfe1d560SDave Jiang }; 358bfe1d560SDave Jiang 35912bbc2c2SFenghua Yu /* DIX generate */ 36012bbc2c2SFenghua Yu struct { 36112bbc2c2SFenghua Yu uint64_t dix_gen_res; 36212bbc2c2SFenghua Yu uint32_t dix_ref_tag; 36312bbc2c2SFenghua Yu uint16_t dix_app_tag_mask; 36412bbc2c2SFenghua Yu uint16_t dix_app_tag; 36512bbc2c2SFenghua Yu }; 36612bbc2c2SFenghua Yu 367bfe1d560SDave Jiang uint8_t op_specific[16]; 368bfe1d560SDave Jiang }; 369bfe1d560SDave Jiang } __attribute__((packed)); 370bfe1d560SDave Jiang 371bfe1d560SDave Jiang struct dsa_raw_completion_record { 372bfe1d560SDave Jiang uint64_t field[4]; 373bfe1d560SDave Jiang } __attribute__((packed)); 374bfe1d560SDave Jiang 375f25b4638SDave Jiang struct iax_completion_record { 376f25b4638SDave Jiang volatile uint8_t status; 377f25b4638SDave Jiang uint8_t error_code; 3785fbe6503SDave Jiang uint8_t fault_info; 3795fbe6503SDave Jiang uint8_t rsvd; 380f25b4638SDave Jiang uint32_t bytes_completed; 381f25b4638SDave Jiang uint64_t fault_addr; 382f25b4638SDave Jiang uint32_t invalid_flags; 383f25b4638SDave Jiang uint32_t rsvd2; 384f25b4638SDave Jiang uint32_t output_size; 385f25b4638SDave Jiang uint8_t output_bits; 386f25b4638SDave Jiang uint8_t rsvd3; 3872d7991feSDave Jiang uint16_t xor_csum; 3882d7991feSDave Jiang uint32_t crc; 3892d7991feSDave Jiang uint32_t min; 3902d7991feSDave Jiang uint32_t max; 3912d7991feSDave Jiang uint32_t sum; 3922d7991feSDave Jiang uint64_t rsvd4[2]; 393f25b4638SDave Jiang } __attribute__((packed)); 394f25b4638SDave Jiang 395f25b4638SDave Jiang struct iax_raw_completion_record { 396f25b4638SDave Jiang uint64_t field[8]; 397f25b4638SDave Jiang } __attribute__((packed)); 398f25b4638SDave Jiang 399bfe1d560SDave Jiang #endif 400