1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _UAPI_XE_DRM_H_ 7 #define _UAPI_XE_DRM_H_ 8 9 #include "drm.h" 10 11 #if defined(__cplusplus) 12 extern "C" { 13 #endif 14 15 /* Please note that modifications to all structs defined here are 16 * subject to backwards-compatibility constraints. 17 */ 18 19 /** 20 * DOC: uevent generated by xe on it's pci node. 21 * 22 * DRM_XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt 23 * fails. The value supplied with the event is always "NEEDS_RESET". 24 * Additional information supplied is tile id and gt id of the gt unit for 25 * which reset has failed. 26 */ 27 #define DRM_XE_RESET_FAILED_UEVENT "DEVICE_STATUS" 28 29 /** 30 * struct xe_user_extension - Base class for defining a chain of extensions 31 * 32 * Many interfaces need to grow over time. In most cases we can simply 33 * extend the struct and have userspace pass in more data. Another option, 34 * as demonstrated by Vulkan's approach to providing extensions for forward 35 * and backward compatibility, is to use a list of optional structs to 36 * provide those extra details. 37 * 38 * The key advantage to using an extension chain is that it allows us to 39 * redefine the interface more easily than an ever growing struct of 40 * increasing complexity, and for large parts of that interface to be 41 * entirely optional. The downside is more pointer chasing; chasing across 42 * the __user boundary with pointers encapsulated inside u64. 43 * 44 * Example chaining: 45 * 46 * .. code-block:: C 47 * 48 * struct xe_user_extension ext3 { 49 * .next_extension = 0, // end 50 * .name = ..., 51 * }; 52 * struct xe_user_extension ext2 { 53 * .next_extension = (uintptr_t)&ext3, 54 * .name = ..., 55 * }; 56 * struct xe_user_extension ext1 { 57 * .next_extension = (uintptr_t)&ext2, 58 * .name = ..., 59 * }; 60 * 61 * Typically the struct xe_user_extension would be embedded in some uAPI 62 * struct, and in this case we would feed it the head of the chain(i.e ext1), 63 * which would then apply all of the above extensions. 64 * 65 */ 66 struct xe_user_extension { 67 /** 68 * @next_extension: 69 * 70 * Pointer to the next struct xe_user_extension, or zero if the end. 71 */ 72 __u64 next_extension; 73 74 /** 75 * @name: Name of the extension. 76 * 77 * Note that the name here is just some integer. 78 * 79 * Also note that the name space for this is not global for the whole 80 * driver, but rather its scope/meaning is limited to the specific piece 81 * of uAPI which has embedded the struct xe_user_extension. 82 */ 83 __u32 name; 84 85 /** 86 * @pad: MBZ 87 * 88 * All undefined bits must be zero. 89 */ 90 __u32 pad; 91 }; 92 93 /* 94 * xe specific ioctls. 95 * 96 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 97 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 98 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 99 */ 100 #define DRM_XE_DEVICE_QUERY 0x00 101 #define DRM_XE_GEM_CREATE 0x01 102 #define DRM_XE_GEM_MMAP_OFFSET 0x02 103 #define DRM_XE_VM_CREATE 0x03 104 #define DRM_XE_VM_DESTROY 0x04 105 #define DRM_XE_VM_BIND 0x05 106 #define DRM_XE_EXEC 0x06 107 #define DRM_XE_EXEC_QUEUE_CREATE 0x07 108 #define DRM_XE_EXEC_QUEUE_DESTROY 0x08 109 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x09 110 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x0a 111 #define DRM_XE_WAIT_USER_FENCE 0x0b 112 /* Must be kept compact -- no holes */ 113 114 #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) 115 #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) 116 #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) 117 #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) 118 #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) 119 #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) 120 #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) 121 #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) 122 #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) 123 #define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property) 124 #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) 125 #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) 126 127 /** struct drm_xe_engine_class_instance - instance of an engine class */ 128 struct drm_xe_engine_class_instance { 129 #define DRM_XE_ENGINE_CLASS_RENDER 0 130 #define DRM_XE_ENGINE_CLASS_COPY 1 131 #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 132 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 133 #define DRM_XE_ENGINE_CLASS_COMPUTE 4 134 /* 135 * Kernel only classes (not actual hardware engine class). Used for 136 * creating ordered queues of VM bind operations. 137 */ 138 #define DRM_XE_ENGINE_CLASS_VM_BIND_ASYNC 5 139 #define DRM_XE_ENGINE_CLASS_VM_BIND_SYNC 6 140 __u16 engine_class; 141 142 __u16 engine_instance; 143 __u16 gt_id; 144 /** @pad: MBZ */ 145 __u16 pad; 146 }; 147 148 /** 149 * enum drm_xe_memory_class - Supported memory classes. 150 */ 151 enum drm_xe_memory_class { 152 /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */ 153 DRM_XE_MEM_REGION_CLASS_SYSMEM = 0, 154 /** 155 * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this 156 * represents the memory that is local to the device, which we 157 * call VRAM. Not valid on integrated platforms. 158 */ 159 DRM_XE_MEM_REGION_CLASS_VRAM 160 }; 161 162 /** 163 * struct drm_xe_query_mem_region - Describes some region as known to 164 * the driver. 165 */ 166 struct drm_xe_query_mem_region { 167 /** 168 * @mem_class: The memory class describing this region. 169 * 170 * See enum drm_xe_memory_class for supported values. 171 */ 172 __u16 mem_class; 173 /** 174 * @instance: The instance for this region. 175 * 176 * The @mem_class and @instance taken together will always give 177 * a unique pair. 178 */ 179 __u16 instance; 180 /** @pad: MBZ */ 181 __u32 pad; 182 /** 183 * @min_page_size: Min page-size in bytes for this region. 184 * 185 * When the kernel allocates memory for this region, the 186 * underlying pages will be at least @min_page_size in size. 187 * 188 * Important note: When userspace allocates a GTT address which 189 * can point to memory allocated from this region, it must also 190 * respect this minimum alignment. This is enforced by the 191 * kernel. 192 */ 193 __u32 min_page_size; 194 /** 195 * @total_size: The usable size in bytes for this region. 196 */ 197 __u64 total_size; 198 /** 199 * @used: Estimate of the memory used in bytes for this region. 200 * 201 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable 202 * accounting. Without this the value here will always equal 203 * zero. 204 */ 205 __u64 used; 206 /** 207 * @cpu_visible_size: How much of this region can be CPU 208 * accessed, in bytes. 209 * 210 * This will always be <= @total_size, and the remainder (if 211 * any) will not be CPU accessible. If the CPU accessible part 212 * is smaller than @total_size then this is referred to as a 213 * small BAR system. 214 * 215 * On systems without small BAR (full BAR), the probed_size will 216 * always equal the @total_size, since all of it will be CPU 217 * accessible. 218 * 219 * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM 220 * regions (for other types the value here will always equal 221 * zero). 222 */ 223 __u64 cpu_visible_size; 224 /** 225 * @cpu_visible_used: Estimate of CPU visible memory used, in 226 * bytes. 227 * 228 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable 229 * accounting. Without this the value here will always equal 230 * zero. Note this is only currently tracked for 231 * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value 232 * here will always be zero). 233 */ 234 __u64 cpu_visible_used; 235 /** @reserved: MBZ */ 236 __u64 reserved[6]; 237 }; 238 239 /** 240 * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps 241 * 242 * If a query is made with a struct drm_xe_device_query where .query is equal to 243 * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles 244 * in .data. struct drm_xe_query_engine_cycles is allocated by the user and 245 * .data points to this allocated structure. 246 * 247 * The query returns the engine cycles and the frequency that can 248 * be used to calculate the engine timestamp. In addition the 249 * query returns a set of cpu timestamps that indicate when the command 250 * streamer cycle count was captured. 251 */ 252 struct drm_xe_query_engine_cycles { 253 /** 254 * @eci: This is input by the user and is the engine for which command 255 * streamer cycles is queried. 256 */ 257 struct drm_xe_engine_class_instance eci; 258 259 /** 260 * @clockid: This is input by the user and is the reference clock id for 261 * CPU timestamp. For definition, see clock_gettime(2) and 262 * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, 263 * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. 264 */ 265 __s32 clockid; 266 267 /** @width: Width of the engine cycle counter in bits. */ 268 __u32 width; 269 270 /** 271 * @engine_cycles: Engine cycles as read from its register 272 * at 0x358 offset. 273 */ 274 __u64 engine_cycles; 275 276 /** @engine_frequency: Frequency of the engine cycles in Hz. */ 277 __u64 engine_frequency; 278 279 /** 280 * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before 281 * reading the engine_cycles register using the reference clockid set by the 282 * user. 283 */ 284 __u64 cpu_timestamp; 285 286 /** 287 * @cpu_delta: Time delta in ns captured around reading the lower dword 288 * of the engine_cycles register. 289 */ 290 __u64 cpu_delta; 291 }; 292 293 /** 294 * struct drm_xe_query_mem_regions - describe memory regions 295 * 296 * If a query is made with a struct drm_xe_device_query where .query 297 * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses 298 * struct drm_xe_query_mem_regions in .data. 299 */ 300 struct drm_xe_query_mem_regions { 301 /** @num_regions: number of memory regions returned in @regions */ 302 __u32 num_regions; 303 /** @pad: MBZ */ 304 __u32 pad; 305 /** @regions: The returned regions for this device */ 306 struct drm_xe_query_mem_region regions[]; 307 }; 308 309 /** 310 * struct drm_xe_query_config - describe the device configuration 311 * 312 * If a query is made with a struct drm_xe_device_query where .query 313 * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses 314 * struct drm_xe_query_config in .data. 315 * 316 */ 317 struct drm_xe_query_config { 318 /** @num_params: number of parameters returned in info */ 319 __u32 num_params; 320 321 /** @pad: MBZ */ 322 __u32 pad; 323 324 #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 325 #define DRM_XE_QUERY_CONFIG_FLAGS 1 326 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0) 327 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2 328 #define DRM_XE_QUERY_CONFIG_VA_BITS 3 329 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 330 /** @info: array of elements containing the config info */ 331 __u64 info[]; 332 }; 333 334 /** 335 * struct drm_xe_query_gt - describe an individual GT. 336 * 337 * To be used with drm_xe_query_gt_list, which will return a list with all the 338 * existing GT individual descriptions. 339 * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for 340 * implementing graphics and/or media operations. 341 */ 342 struct drm_xe_query_gt { 343 #define DRM_XE_QUERY_GT_TYPE_MAIN 0 344 #define DRM_XE_QUERY_GT_TYPE_MEDIA 1 345 /** @type: GT type: Main or Media */ 346 __u16 type; 347 /** @gt_id: Unique ID of this GT within the PCI Device */ 348 __u16 gt_id; 349 /** @clock_freq: A clock frequency for timestamp */ 350 __u32 clock_freq; 351 /** 352 * @near_mem_regions: Bit mask of instances from 353 * drm_xe_query_mem_regions that are nearest to the current engines 354 * of this GT. 355 */ 356 __u64 near_mem_regions; 357 /** 358 * @far_mem_regions: Bit mask of instances from 359 * drm_xe_query_mem_regions that are far from the engines of this GT. 360 * In general, they have extra indirections when compared to the 361 * @near_mem_regions. For a discrete device this could mean system 362 * memory and memory living in a different tile. 363 */ 364 __u64 far_mem_regions; 365 /** @reserved: Reserved */ 366 __u64 reserved[8]; 367 }; 368 369 /** 370 * struct drm_xe_query_gt_list - A list with GT description items. 371 * 372 * If a query is made with a struct drm_xe_device_query where .query 373 * is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct 374 * drm_xe_query_gt_list in .data. 375 */ 376 struct drm_xe_query_gt_list { 377 /** @num_gt: number of GT items returned in gt_list */ 378 __u32 num_gt; 379 /** @pad: MBZ */ 380 __u32 pad; 381 /** @gt_list: The GT list returned for this device */ 382 struct drm_xe_query_gt gt_list[]; 383 }; 384 385 /** 386 * struct drm_xe_query_topology_mask - describe the topology mask of a GT 387 * 388 * This is the hardware topology which reflects the internal physical 389 * structure of the GPU. 390 * 391 * If a query is made with a struct drm_xe_device_query where .query 392 * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses 393 * struct drm_xe_query_topology_mask in .data. 394 */ 395 struct drm_xe_query_topology_mask { 396 /** @gt_id: GT ID the mask is associated with */ 397 __u16 gt_id; 398 399 /* 400 * To query the mask of Dual Sub Slices (DSS) available for geometry 401 * operations. For example a query response containing the following 402 * in mask: 403 * DSS_GEOMETRY ff ff ff ff 00 00 00 00 404 * means 32 DSS are available for geometry. 405 */ 406 #define DRM_XE_TOPO_DSS_GEOMETRY (1 << 0) 407 /* 408 * To query the mask of Dual Sub Slices (DSS) available for compute 409 * operations. For example a query response containing the following 410 * in mask: 411 * DSS_COMPUTE ff ff ff ff 00 00 00 00 412 * means 32 DSS are available for compute. 413 */ 414 #define DRM_XE_TOPO_DSS_COMPUTE (1 << 1) 415 /* 416 * To query the mask of Execution Units (EU) available per Dual Sub 417 * Slices (DSS). For example a query response containing the following 418 * in mask: 419 * EU_PER_DSS ff ff 00 00 00 00 00 00 420 * means each DSS has 16 EU. 421 */ 422 #define DRM_XE_TOPO_EU_PER_DSS (1 << 2) 423 /** @type: type of mask */ 424 __u16 type; 425 426 /** @num_bytes: number of bytes in requested mask */ 427 __u32 num_bytes; 428 429 /** @mask: little-endian mask of @num_bytes */ 430 __u8 mask[]; 431 }; 432 433 /** 434 * struct drm_xe_device_query - main structure to query device information 435 * 436 * If size is set to 0, the driver fills it with the required size for the 437 * requested type of data to query. If size is equal to the required size, 438 * the queried information is copied into data. 439 * 440 * For example the following code snippet allows retrieving and printing 441 * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES: 442 * 443 * .. code-block:: C 444 * 445 * struct drm_xe_engine_class_instance *hwe; 446 * struct drm_xe_device_query query = { 447 * .extensions = 0, 448 * .query = DRM_XE_DEVICE_QUERY_ENGINES, 449 * .size = 0, 450 * .data = 0, 451 * }; 452 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 453 * hwe = malloc(query.size); 454 * query.data = (uintptr_t)hwe; 455 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 456 * int num_engines = query.size / sizeof(*hwe); 457 * for (int i = 0; i < num_engines; i++) { 458 * printf("Engine %d: %s\n", i, 459 * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": 460 * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_COPY ? "COPY": 461 * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": 462 * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": 463 * hwe[i].engine_class == DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": 464 * "UNKNOWN"); 465 * } 466 * free(hwe); 467 */ 468 struct drm_xe_device_query { 469 /** @extensions: Pointer to the first extension struct, if any */ 470 __u64 extensions; 471 472 #define DRM_XE_DEVICE_QUERY_ENGINES 0 473 #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1 474 #define DRM_XE_DEVICE_QUERY_CONFIG 2 475 #define DRM_XE_DEVICE_QUERY_GT_LIST 3 476 #define DRM_XE_DEVICE_QUERY_HWCONFIG 4 477 #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 478 #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 479 /** @query: The type of data to query */ 480 __u32 query; 481 482 /** @size: Size of the queried data */ 483 __u32 size; 484 485 /** @data: Queried data is placed here */ 486 __u64 data; 487 488 /** @reserved: Reserved */ 489 __u64 reserved[2]; 490 }; 491 492 struct drm_xe_gem_create { 493 /** @extensions: Pointer to the first extension struct, if any */ 494 __u64 extensions; 495 496 /** 497 * @size: Requested size for the object 498 * 499 * The (page-aligned) allocated size for the object will be returned. 500 */ 501 __u64 size; 502 503 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24) 504 #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25) 505 /* 506 * When using VRAM as a possible placement, ensure that the corresponding VRAM 507 * allocation will always use the CPU accessible part of VRAM. This is important 508 * for small-bar systems (on full-bar systems this gets turned into a noop). 509 * 510 * Note: System memory can be used as an extra placement if the kernel should 511 * spill the allocation to system memory, if space can't be made available in 512 * the CPU accessible part of VRAM (giving the same behaviour as the i915 513 * interface, see I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). 514 * 515 * Note: For clear-color CCS surfaces the kernel needs to read the clear-color 516 * value stored in the buffer, and on discrete platforms we need to use VRAM for 517 * display surfaces, therefore the kernel requires setting this flag for such 518 * objects, otherwise an error is thrown on small-bar systems. 519 */ 520 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26) 521 /** 522 * @flags: Flags, currently a mask of memory instances of where BO can 523 * be placed 524 */ 525 __u32 flags; 526 527 /** 528 * @vm_id: Attached VM, if any 529 * 530 * If a VM is specified, this BO must: 531 * 532 * 1. Only ever be bound to that VM. 533 * 2. Cannot be exported as a PRIME fd. 534 */ 535 __u32 vm_id; 536 537 /** 538 * @handle: Returned handle for the object. 539 * 540 * Object handles are nonzero. 541 */ 542 __u32 handle; 543 544 /** 545 * @cpu_caching: The CPU caching mode to select for this object. If 546 * mmaping the object the mode selected here will also be used. 547 * 548 * Supported values: 549 * 550 * DRM_XE_GEM_CPU_CACHING_WB: Allocate the pages with write-back 551 * caching. On iGPU this can't be used for scanout surfaces. Currently 552 * not allowed for objects placed in VRAM. 553 * 554 * DRM_XE_GEM_CPU_CACHING_WC: Allocate the pages as write-combined. This 555 * is uncached. Scanout surfaces should likely use this. All objects 556 * that can be placed in VRAM must use this. 557 */ 558 #define DRM_XE_GEM_CPU_CACHING_WB 1 559 #define DRM_XE_GEM_CPU_CACHING_WC 2 560 __u16 cpu_caching; 561 /** @pad: MBZ */ 562 __u16 pad; 563 564 /** @reserved: Reserved */ 565 __u64 reserved[2]; 566 }; 567 568 struct drm_xe_gem_mmap_offset { 569 /** @extensions: Pointer to the first extension struct, if any */ 570 __u64 extensions; 571 572 /** @handle: Handle for the object being mapped. */ 573 __u32 handle; 574 575 /** @flags: Must be zero */ 576 __u32 flags; 577 578 /** @offset: The fake offset to use for subsequent mmap call */ 579 __u64 offset; 580 581 /** @reserved: Reserved */ 582 __u64 reserved[2]; 583 }; 584 585 /** struct drm_xe_ext_set_property - XE set property extension */ 586 struct drm_xe_ext_set_property { 587 /** @base: base user extension */ 588 struct xe_user_extension base; 589 590 /** @property: property to set */ 591 __u32 property; 592 593 /** @pad: MBZ */ 594 __u32 pad; 595 596 /** @value: property value */ 597 __u64 value; 598 599 /** @reserved: Reserved */ 600 __u64 reserved[2]; 601 }; 602 603 struct drm_xe_vm_create { 604 #define DRM_XE_VM_EXTENSION_SET_PROPERTY 0 605 /** @extensions: Pointer to the first extension struct, if any */ 606 __u64 extensions; 607 608 #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0) 609 #define DRM_XE_VM_CREATE_FLAG_COMPUTE_MODE (1 << 1) 610 #define DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT (1 << 2) 611 #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 3) 612 /** @flags: Flags */ 613 __u32 flags; 614 615 /** @vm_id: Returned VM ID */ 616 __u32 vm_id; 617 618 /** @reserved: Reserved */ 619 __u64 reserved[2]; 620 }; 621 622 struct drm_xe_vm_destroy { 623 /** @vm_id: VM ID */ 624 __u32 vm_id; 625 626 /** @pad: MBZ */ 627 __u32 pad; 628 629 /** @reserved: Reserved */ 630 __u64 reserved[2]; 631 }; 632 633 struct drm_xe_vm_bind_op { 634 /** 635 * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP 636 */ 637 __u32 obj; 638 639 /** 640 * @pat_index: The platform defined @pat_index to use for this mapping. 641 * The index basically maps to some predefined memory attributes, 642 * including things like caching, coherency, compression etc. The exact 643 * meaning of the pat_index is platform specific and defined in the 644 * Bspec and PRMs. When the KMD sets up the binding the index here is 645 * encoded into the ppGTT PTE. 646 * 647 * For coherency the @pat_index needs to be at least 1way coherent when 648 * drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD 649 * will extract the coherency mode from the @pat_index and reject if 650 * there is a mismatch (see note below for pre-MTL platforms). 651 * 652 * Note: On pre-MTL platforms there is only a caching mode and no 653 * explicit coherency mode, but on such hardware there is always a 654 * shared-LLC (or is dgpu) so all GT memory accesses are coherent with 655 * CPU caches even with the caching mode set as uncached. It's only the 656 * display engine that is incoherent (on dgpu it must be in VRAM which 657 * is always mapped as WC on the CPU). However to keep the uapi somewhat 658 * consistent with newer platforms the KMD groups the different cache 659 * levels into the following coherency buckets on all pre-MTL platforms: 660 * 661 * ppGTT UC -> COH_NONE 662 * ppGTT WC -> COH_NONE 663 * ppGTT WT -> COH_NONE 664 * ppGTT WB -> COH_AT_LEAST_1WAY 665 * 666 * In practice UC/WC/WT should only ever used for scanout surfaces on 667 * such platforms (or perhaps in general for dma-buf if shared with 668 * another device) since it is only the display engine that is actually 669 * incoherent. Everything else should typically use WB given that we 670 * have a shared-LLC. On MTL+ this completely changes and the HW 671 * defines the coherency mode as part of the @pat_index, where 672 * incoherent GT access is possible. 673 * 674 * Note: For userptr and externally imported dma-buf the kernel expects 675 * either 1WAY or 2WAY for the @pat_index. 676 * 677 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions 678 * on the @pat_index. For such mappings there is no actual memory being 679 * mapped (the address in the PTE is invalid), so the various PAT memory 680 * attributes likely do not apply. Simply leaving as zero is one 681 * option (still a valid pat_index). 682 */ 683 __u16 pat_index; 684 685 /** @pad: MBZ */ 686 __u16 pad; 687 688 union { 689 /** 690 * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE, 691 * ignored for unbind 692 */ 693 __u64 obj_offset; 694 695 /** @userptr: user pointer to bind on */ 696 __u64 userptr; 697 }; 698 699 /** 700 * @range: Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL 701 */ 702 __u64 range; 703 704 /** @addr: Address to operate on, MBZ for UNMAP_ALL */ 705 __u64 addr; 706 707 /** 708 * @tile_mask: Mask for which tiles to create binds for, 0 == All tiles, 709 * only applies to creating new VMAs 710 */ 711 __u64 tile_mask; 712 713 #define DRM_XE_VM_BIND_OP_MAP 0x0 714 #define DRM_XE_VM_BIND_OP_UNMAP 0x1 715 #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2 716 #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3 717 #define DRM_XE_VM_BIND_OP_PREFETCH 0x4 718 /** @op: Bind operation to perform */ 719 __u32 op; 720 721 #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0) 722 #define DRM_XE_VM_BIND_FLAG_ASYNC (1 << 1) 723 /* 724 * Valid on a faulting VM only, do the MAP operation immediately rather 725 * than deferring the MAP to the page fault handler. 726 */ 727 #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 2) 728 /* 729 * When the NULL flag is set, the page tables are setup with a special 730 * bit which indicates writes are dropped and all reads return zero. In 731 * the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP 732 * operations, the BO handle MBZ, and the BO offset MBZ. This flag is 733 * intended to implement VK sparse bindings. 734 */ 735 #define DRM_XE_VM_BIND_FLAG_NULL (1 << 3) 736 /** @flags: Bind flags */ 737 __u32 flags; 738 739 /** 740 * @prefetch_mem_region_instance: Memory region to prefetch VMA to. 741 * It is a region instance, not a mask. 742 * To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation. 743 */ 744 __u32 prefetch_mem_region_instance; 745 746 /** @reserved: Reserved */ 747 __u64 reserved[2]; 748 }; 749 750 struct drm_xe_vm_bind { 751 /** @extensions: Pointer to the first extension struct, if any */ 752 __u64 extensions; 753 754 /** @vm_id: The ID of the VM to bind to */ 755 __u32 vm_id; 756 757 /** 758 * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND 759 * and exec queue must have same vm_id. If zero, the default VM bind engine 760 * is used. 761 */ 762 __u32 exec_queue_id; 763 764 /** @num_binds: number of binds in this IOCTL */ 765 __u32 num_binds; 766 767 /** @pad: MBZ */ 768 __u32 pad; 769 770 union { 771 /** @bind: used if num_binds == 1 */ 772 struct drm_xe_vm_bind_op bind; 773 774 /** 775 * @vector_of_binds: userptr to array of struct 776 * drm_xe_vm_bind_op if num_binds > 1 777 */ 778 __u64 vector_of_binds; 779 }; 780 781 /** @num_syncs: amount of syncs to wait on */ 782 __u32 num_syncs; 783 784 /** @pad2: MBZ */ 785 __u32 pad2; 786 787 /** @syncs: pointer to struct drm_xe_sync array */ 788 __u64 syncs; 789 790 /** @reserved: Reserved */ 791 __u64 reserved[2]; 792 }; 793 794 /* For use with DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY */ 795 796 /* Monitor 128KB contiguous region with 4K sub-granularity */ 797 #define DRM_XE_ACC_GRANULARITY_128K 0 798 799 /* Monitor 2MB contiguous region with 64KB sub-granularity */ 800 #define DRM_XE_ACC_GRANULARITY_2M 1 801 802 /* Monitor 16MB contiguous region with 512KB sub-granularity */ 803 #define DRM_XE_ACC_GRANULARITY_16M 2 804 805 /* Monitor 64MB contiguous region with 2M sub-granularity */ 806 #define DRM_XE_ACC_GRANULARITY_64M 3 807 808 /** 809 * struct drm_xe_exec_queue_set_property - exec queue set property 810 * 811 * Same namespace for extensions as drm_xe_exec_queue_create 812 */ 813 struct drm_xe_exec_queue_set_property { 814 /** @extensions: Pointer to the first extension struct, if any */ 815 __u64 extensions; 816 817 /** @exec_queue_id: Exec queue ID */ 818 __u32 exec_queue_id; 819 820 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 821 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 822 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2 823 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 3 824 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 4 825 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 5 826 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 6 827 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 7 828 /** @property: property to set */ 829 __u32 property; 830 831 /** @value: property value */ 832 __u64 value; 833 834 /** @reserved: Reserved */ 835 __u64 reserved[2]; 836 }; 837 838 struct drm_xe_exec_queue_create { 839 #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 840 /** @extensions: Pointer to the first extension struct, if any */ 841 __u64 extensions; 842 843 /** @width: submission width (number BB per exec) for this exec queue */ 844 __u16 width; 845 846 /** @num_placements: number of valid placements for this exec queue */ 847 __u16 num_placements; 848 849 /** @vm_id: VM to use for this exec queue */ 850 __u32 vm_id; 851 852 /** @flags: MBZ */ 853 __u32 flags; 854 855 /** @exec_queue_id: Returned exec queue ID */ 856 __u32 exec_queue_id; 857 858 /** 859 * @instances: user pointer to a 2-d array of struct 860 * drm_xe_engine_class_instance 861 * 862 * length = width (i) * num_placements (j) 863 * index = j + i * width 864 */ 865 __u64 instances; 866 867 /** @reserved: Reserved */ 868 __u64 reserved[2]; 869 }; 870 871 struct drm_xe_exec_queue_get_property { 872 /** @extensions: Pointer to the first extension struct, if any */ 873 __u64 extensions; 874 875 /** @exec_queue_id: Exec queue ID */ 876 __u32 exec_queue_id; 877 878 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 879 /** @property: property to get */ 880 __u32 property; 881 882 /** @value: property value */ 883 __u64 value; 884 885 /** @reserved: Reserved */ 886 __u64 reserved[2]; 887 }; 888 889 struct drm_xe_exec_queue_destroy { 890 /** @exec_queue_id: Exec queue ID */ 891 __u32 exec_queue_id; 892 893 /** @pad: MBZ */ 894 __u32 pad; 895 896 /** @reserved: Reserved */ 897 __u64 reserved[2]; 898 }; 899 900 struct drm_xe_sync { 901 /** @extensions: Pointer to the first extension struct, if any */ 902 __u64 extensions; 903 904 #define DRM_XE_SYNC_FLAG_SYNCOBJ 0x0 905 #define DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ 0x1 906 #define DRM_XE_SYNC_FLAG_DMA_BUF 0x2 907 #define DRM_XE_SYNC_FLAG_USER_FENCE 0x3 908 #define DRM_XE_SYNC_FLAG_SIGNAL 0x10 909 __u32 flags; 910 911 /** @pad: MBZ */ 912 __u32 pad; 913 914 union { 915 __u32 handle; 916 917 /** 918 * @addr: Address of user fence. When sync passed in via exec 919 * IOCTL this a GPU address in the VM. When sync passed in via 920 * VM bind IOCTL this is a user pointer. In either case, it is 921 * the users responsibility that this address is present and 922 * mapped when the user fence is signalled. Must be qword 923 * aligned. 924 */ 925 __u64 addr; 926 }; 927 928 __u64 timeline_value; 929 930 /** @reserved: Reserved */ 931 __u64 reserved[2]; 932 }; 933 934 struct drm_xe_exec { 935 /** @extensions: Pointer to the first extension struct, if any */ 936 __u64 extensions; 937 938 /** @exec_queue_id: Exec queue ID for the batch buffer */ 939 __u32 exec_queue_id; 940 941 /** @num_syncs: Amount of struct drm_xe_sync in array. */ 942 __u32 num_syncs; 943 944 /** @syncs: Pointer to struct drm_xe_sync array. */ 945 __u64 syncs; 946 947 /** 948 * @address: address of batch buffer if num_batch_buffer == 1 or an 949 * array of batch buffer addresses 950 */ 951 __u64 address; 952 953 /** 954 * @num_batch_buffer: number of batch buffer in this exec, must match 955 * the width of the engine 956 */ 957 __u16 num_batch_buffer; 958 959 /** @pad: MBZ */ 960 __u16 pad[3]; 961 962 /** @reserved: Reserved */ 963 __u64 reserved[2]; 964 }; 965 966 /** 967 * struct drm_xe_wait_user_fence - wait user fence 968 * 969 * Wait on user fence, XE will wake-up on every HW engine interrupt in the 970 * instances list and check if user fence is complete:: 971 * 972 * (*addr & MASK) OP (VALUE & MASK) 973 * 974 * Returns to user on user fence completion or timeout. 975 */ 976 struct drm_xe_wait_user_fence { 977 /** @extensions: Pointer to the first extension struct, if any */ 978 __u64 extensions; 979 980 /** 981 * @addr: user pointer address to wait on, must qword aligned 982 */ 983 __u64 addr; 984 985 #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0 986 #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1 987 #define DRM_XE_UFENCE_WAIT_OP_GT 0x2 988 #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3 989 #define DRM_XE_UFENCE_WAIT_OP_LT 0x4 990 #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5 991 /** @op: wait operation (type of comparison) */ 992 __u16 op; 993 994 #define DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */ 995 #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 1) 996 /** @flags: wait flags */ 997 __u16 flags; 998 999 /** @pad: MBZ */ 1000 __u32 pad; 1001 1002 /** @value: compare value */ 1003 __u64 value; 1004 1005 #define DRM_XE_UFENCE_WAIT_MASK_U8 0xffu 1006 #define DRM_XE_UFENCE_WAIT_MASK_U16 0xffffu 1007 #define DRM_XE_UFENCE_WAIT_MASK_U32 0xffffffffu 1008 #define DRM_XE_UFENCE_WAIT_MASK_U64 0xffffffffffffffffu 1009 /** @mask: comparison mask */ 1010 __u64 mask; 1011 1012 /** 1013 * @timeout: how long to wait before bailing, value in nanoseconds. 1014 * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) 1015 * it contains timeout expressed in nanoseconds to wait (fence will 1016 * expire at now() + timeout). 1017 * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait 1018 * will end at timeout (uses system MONOTONIC_CLOCK). 1019 * Passing negative timeout leads to neverending wait. 1020 * 1021 * On relative timeout this value is updated with timeout left 1022 * (for restarting the call in case of signal delivery). 1023 * On absolute timeout this value stays intact (restarted call still 1024 * expire at the same point of time). 1025 */ 1026 __s64 timeout; 1027 1028 /** 1029 * @num_engines: number of engine instances to wait on, must be zero 1030 * when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set 1031 */ 1032 __u64 num_engines; 1033 1034 /** 1035 * @instances: user pointer to array of drm_xe_engine_class_instance to 1036 * wait on, must be NULL when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set 1037 */ 1038 __u64 instances; 1039 1040 /** @reserved: Reserved */ 1041 __u64 reserved[2]; 1042 }; 1043 1044 /** 1045 * DOC: XE PMU event config IDs 1046 * 1047 * Check 'man perf_event_open' to use the ID's DRM_XE_PMU_XXXX listed in xe_drm.h 1048 * in 'struct perf_event_attr' as part of perf_event_open syscall to read a 1049 * particular event. 1050 * 1051 * For example to open the DRMXE_PMU_RENDER_GROUP_BUSY(0): 1052 * 1053 * .. code-block:: C 1054 * 1055 * struct perf_event_attr attr; 1056 * long long count; 1057 * int cpu = 0; 1058 * int fd; 1059 * 1060 * memset(&attr, 0, sizeof(struct perf_event_attr)); 1061 * attr.type = type; // eg: /sys/bus/event_source/devices/xe_0000_56_00.0/type 1062 * attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED; 1063 * attr.use_clockid = 1; 1064 * attr.clockid = CLOCK_MONOTONIC; 1065 * attr.config = DRM_XE_PMU_RENDER_GROUP_BUSY(0); 1066 * 1067 * fd = syscall(__NR_perf_event_open, &attr, -1, cpu, -1, 0); 1068 */ 1069 1070 /* 1071 * Top bits of every counter are GT id. 1072 */ 1073 #define __DRM_XE_PMU_GT_SHIFT (56) 1074 1075 #define ___DRM_XE_PMU_OTHER(gt, x) \ 1076 (((__u64)(x)) | ((__u64)(gt) << __DRM_XE_PMU_GT_SHIFT)) 1077 1078 #define DRM_XE_PMU_RENDER_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 0) 1079 #define DRM_XE_PMU_COPY_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 1) 1080 #define DRM_XE_PMU_MEDIA_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 2) 1081 #define DRM_XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 3) 1082 1083 #if defined(__cplusplus) 1084 } 1085 #endif 1086 1087 #endif /* _UAPI_XE_DRM_H_ */ 1088