1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _UAPI_XE_DRM_H_ 7 #define _UAPI_XE_DRM_H_ 8 9 #include "drm.h" 10 11 #if defined(__cplusplus) 12 extern "C" { 13 #endif 14 15 /* 16 * Please note that modifications to all structs defined here are 17 * subject to backwards-compatibility constraints. 18 * Sections in this file are organized as follows: 19 * 1. IOCTL definition 20 * 2. Extension definition and helper structs 21 * 3. IOCTL's Query structs in the order of the Query's entries. 22 * 4. The rest of IOCTL structs in the order of IOCTL declaration. 23 */ 24 25 /** 26 * DOC: Xe Device Block Diagram 27 * 28 * The diagram below represents a high-level simplification of a discrete 29 * GPU supported by the Xe driver. It shows some device components which 30 * are necessary to understand this API, as well as how their relations 31 * to each other. This diagram does not represent real hardware:: 32 * 33 * ┌──────────────────────────────────────────────────────────────────┐ 34 * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ 35 * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ 36 * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ 37 * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ 38 * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ 39 * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ 40 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 41 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ 42 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 43 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 44 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ 45 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 46 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 47 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ 48 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 49 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 50 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ 51 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 52 * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 53 * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ 54 * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 55 * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ 56 * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ 57 * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ 58 * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ 59 * └─────────────────────────────Device0───────┬──────────────────────┘ 60 * │ 61 * ───────────────────────┴────────── PCI bus 62 */ 63 64 /** 65 * DOC: Xe uAPI Overview 66 * 67 * This section aims to describe the Xe's IOCTL entries, its structs, and other 68 * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related 69 * entries and usage. 70 * 71 * List of supported IOCTLs: 72 * - &DRM_IOCTL_XE_DEVICE_QUERY 73 * - &DRM_IOCTL_XE_GEM_CREATE 74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET 75 * - &DRM_IOCTL_XE_VM_CREATE 76 * - &DRM_IOCTL_XE_VM_DESTROY 77 * - &DRM_IOCTL_XE_VM_BIND 78 * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE 79 * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY 80 * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY 81 * - &DRM_IOCTL_XE_EXEC 82 * - &DRM_IOCTL_XE_WAIT_USER_FENCE 83 * - &DRM_IOCTL_XE_OBSERVATION 84 * - &DRM_IOCTL_XE_MADVISE 85 * - &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS 86 */ 87 88 /* 89 * xe specific ioctls. 90 * 91 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 92 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 93 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 94 */ 95 #define DRM_XE_DEVICE_QUERY 0x00 96 #define DRM_XE_GEM_CREATE 0x01 97 #define DRM_XE_GEM_MMAP_OFFSET 0x02 98 #define DRM_XE_VM_CREATE 0x03 99 #define DRM_XE_VM_DESTROY 0x04 100 #define DRM_XE_VM_BIND 0x05 101 #define DRM_XE_EXEC_QUEUE_CREATE 0x06 102 #define DRM_XE_EXEC_QUEUE_DESTROY 0x07 103 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08 104 #define DRM_XE_EXEC 0x09 105 #define DRM_XE_WAIT_USER_FENCE 0x0a 106 #define DRM_XE_OBSERVATION 0x0b 107 #define DRM_XE_MADVISE 0x0c 108 #define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS 0x0d 109 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0e 110 111 /* Must be kept compact -- no holes */ 112 113 #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) 114 #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) 115 #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) 116 #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) 117 #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) 118 #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) 119 #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) 120 #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) 121 #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) 122 #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) 123 #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) 124 #define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param) 125 #define DRM_IOCTL_XE_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_MADVISE, struct drm_xe_madvise) 126 #define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr) 127 #define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property) 128 129 /** 130 * DOC: Xe IOCTL Extensions 131 * 132 * Before detailing the IOCTLs and its structs, it is important to highlight 133 * that every IOCTL in Xe is extensible. 134 * 135 * Many interfaces need to grow over time. In most cases we can simply 136 * extend the struct and have userspace pass in more data. Another option, 137 * as demonstrated by Vulkan's approach to providing extensions for forward 138 * and backward compatibility, is to use a list of optional structs to 139 * provide those extra details. 140 * 141 * The key advantage to using an extension chain is that it allows us to 142 * redefine the interface more easily than an ever growing struct of 143 * increasing complexity, and for large parts of that interface to be 144 * entirely optional. The downside is more pointer chasing; chasing across 145 * the __user boundary with pointers encapsulated inside u64. 146 * 147 * Example chaining: 148 * 149 * .. code-block:: C 150 * 151 * struct drm_xe_user_extension ext3 { 152 * .next_extension = 0, // end 153 * .name = ..., 154 * }; 155 * struct drm_xe_user_extension ext2 { 156 * .next_extension = (uintptr_t)&ext3, 157 * .name = ..., 158 * }; 159 * struct drm_xe_user_extension ext1 { 160 * .next_extension = (uintptr_t)&ext2, 161 * .name = ..., 162 * }; 163 * 164 * Typically the struct drm_xe_user_extension would be embedded in some uAPI 165 * struct, and in this case we would feed it the head of the chain(i.e ext1), 166 * which would then apply all of the above extensions. 167 */ 168 169 /** 170 * struct drm_xe_user_extension - Base class for defining a chain of extensions 171 */ 172 struct drm_xe_user_extension { 173 /** 174 * @next_extension: 175 * 176 * Pointer to the next struct drm_xe_user_extension, or zero if the end. 177 */ 178 __u64 next_extension; 179 180 /** 181 * @name: Name of the extension. 182 * 183 * Note that the name here is just some integer. 184 * 185 * Also note that the name space for this is not global for the whole 186 * driver, but rather its scope/meaning is limited to the specific piece 187 * of uAPI which has embedded the struct drm_xe_user_extension. 188 */ 189 __u32 name; 190 191 /** 192 * @pad: MBZ 193 * 194 * All undefined bits must be zero. 195 */ 196 __u32 pad; 197 }; 198 199 /** 200 * struct drm_xe_ext_set_property - Generic set property extension 201 * 202 * A generic struct that allows any of the Xe's IOCTL to be extended 203 * with a set_property operation. 204 */ 205 struct drm_xe_ext_set_property { 206 /** @base: base user extension */ 207 struct drm_xe_user_extension base; 208 209 /** @property: property to set */ 210 __u32 property; 211 212 /** @pad: MBZ */ 213 __u32 pad; 214 215 union { 216 /** @value: property value */ 217 __u64 value; 218 /** @ptr: pointer to user value */ 219 __u64 ptr; 220 }; 221 222 /** @reserved: Reserved */ 223 __u64 reserved[2]; 224 }; 225 226 /** 227 * struct drm_xe_engine_class_instance - instance of an engine class 228 * 229 * It is returned as part of the @drm_xe_engine, but it also is used as 230 * the input of engine selection for both @drm_xe_exec_queue_create and 231 * @drm_xe_query_engine_cycles 232 * 233 * The @engine_class can be: 234 * - %DRM_XE_ENGINE_CLASS_RENDER 235 * - %DRM_XE_ENGINE_CLASS_COPY 236 * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE 237 * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 238 * - %DRM_XE_ENGINE_CLASS_COMPUTE 239 * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual 240 * hardware engine class). Used for creating ordered queues of VM 241 * bind operations. 242 */ 243 struct drm_xe_engine_class_instance { 244 #define DRM_XE_ENGINE_CLASS_RENDER 0 245 #define DRM_XE_ENGINE_CLASS_COPY 1 246 #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 247 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 248 #define DRM_XE_ENGINE_CLASS_COMPUTE 4 249 #define DRM_XE_ENGINE_CLASS_VM_BIND 5 250 /** @engine_class: engine class id */ 251 __u16 engine_class; 252 /** @engine_instance: engine instance id */ 253 __u16 engine_instance; 254 /** @gt_id: Unique ID of this GT within the PCI Device */ 255 __u16 gt_id; 256 /** @pad: MBZ */ 257 __u16 pad; 258 }; 259 260 /** 261 * struct drm_xe_engine - describe hardware engine 262 */ 263 struct drm_xe_engine { 264 /** @instance: The @drm_xe_engine_class_instance */ 265 struct drm_xe_engine_class_instance instance; 266 267 /** @reserved: Reserved */ 268 __u64 reserved[3]; 269 }; 270 271 /** 272 * struct drm_xe_query_engines - describe engines 273 * 274 * If a query is made with a struct @drm_xe_device_query where .query 275 * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of 276 * struct @drm_xe_query_engines in .data. 277 */ 278 struct drm_xe_query_engines { 279 /** @num_engines: number of engines returned in @engines */ 280 __u32 num_engines; 281 /** @pad: MBZ */ 282 __u32 pad; 283 /** @engines: The returned engines for this device */ 284 struct drm_xe_engine engines[]; 285 }; 286 287 /** 288 * enum drm_xe_memory_class - Supported memory classes. 289 */ 290 enum drm_xe_memory_class { 291 /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */ 292 DRM_XE_MEM_REGION_CLASS_SYSMEM = 0, 293 /** 294 * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this 295 * represents the memory that is local to the device, which we 296 * call VRAM. Not valid on integrated platforms. 297 */ 298 DRM_XE_MEM_REGION_CLASS_VRAM 299 }; 300 301 /** 302 * struct drm_xe_mem_region - Describes some region as known to 303 * the driver. 304 */ 305 struct drm_xe_mem_region { 306 /** 307 * @mem_class: The memory class describing this region. 308 * 309 * See enum drm_xe_memory_class for supported values. 310 */ 311 __u16 mem_class; 312 /** 313 * @instance: The unique ID for this region, which serves as the 314 * index in the placement bitmask used as argument for 315 * &DRM_IOCTL_XE_GEM_CREATE 316 */ 317 __u16 instance; 318 /** 319 * @min_page_size: Min page-size in bytes for this region. 320 * 321 * When the kernel allocates memory for this region, the 322 * underlying pages will be at least @min_page_size in size. 323 * Buffer objects with an allowable placement in this region must be 324 * created with a size aligned to this value. 325 * GPU virtual address mappings of (parts of) buffer objects that 326 * may be placed in this region must also have their GPU virtual 327 * address and range aligned to this value. 328 * Affected IOCTLS will return %-EINVAL if alignment restrictions are 329 * not met. 330 */ 331 __u32 min_page_size; 332 /** 333 * @total_size: The usable size in bytes for this region. 334 */ 335 __u64 total_size; 336 /** 337 * @used: Estimate of the memory used in bytes for this region. 338 */ 339 __u64 used; 340 /** 341 * @cpu_visible_size: How much of this region can be CPU 342 * accessed, in bytes. 343 * 344 * This will always be <= @total_size, and the remainder (if 345 * any) will not be CPU accessible. If the CPU accessible part 346 * is smaller than @total_size then this is referred to as a 347 * small BAR system. 348 * 349 * On systems without small BAR (full BAR), the probed_size will 350 * always equal the @total_size, since all of it will be CPU 351 * accessible. 352 * 353 * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM 354 * regions (for other types the value here will always equal 355 * zero). 356 */ 357 __u64 cpu_visible_size; 358 /** 359 * @cpu_visible_used: Estimate of CPU visible memory used, in 360 * bytes. 361 * 362 * Note this is only currently tracked for 363 * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value 364 * here will always be zero). 365 */ 366 __u64 cpu_visible_used; 367 /** @reserved: Reserved */ 368 __u64 reserved[6]; 369 }; 370 371 /** 372 * struct drm_xe_query_mem_regions - describe memory regions 373 * 374 * If a query is made with a struct drm_xe_device_query where .query 375 * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses 376 * struct drm_xe_query_mem_regions in .data. 377 */ 378 struct drm_xe_query_mem_regions { 379 /** @num_mem_regions: number of memory regions returned in @mem_regions */ 380 __u32 num_mem_regions; 381 /** @pad: MBZ */ 382 __u32 pad; 383 /** @mem_regions: The returned memory regions for this device */ 384 struct drm_xe_mem_region mem_regions[]; 385 }; 386 387 /** 388 * struct drm_xe_query_config - describe the device configuration 389 * 390 * If a query is made with a struct drm_xe_device_query where .query 391 * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses 392 * struct drm_xe_query_config in .data. 393 * 394 * The index in @info can be: 395 * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits) 396 * and the device revision (next 8 bits) 397 * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device 398 * configuration, see list below 399 * 400 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device 401 * has usable VRAM 402 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - Flag is set if the device 403 * has low latency hint support 404 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the 405 * device has CPU address mirroring support 406 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT - Flag is set if the 407 * device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION. 408 * This is exposed only on Xe2+. 409 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX - Flag is set 410 * if a queue can be creaed with 411 * %DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 412 * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment 413 * required by this device, typically SZ_4K or SZ_64K 414 * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address 415 * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest 416 * available exec queue priority 417 */ 418 struct drm_xe_query_config { 419 /** @num_params: number of parameters returned in info */ 420 __u32 num_params; 421 422 /** @pad: MBZ */ 423 __u32 pad; 424 425 #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 426 #define DRM_XE_QUERY_CONFIG_FLAGS 1 427 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0) 428 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1) 429 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2) 430 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_NO_COMPRESSION_HINT (1 << 3) 431 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX (1 << 4) 432 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2 433 #define DRM_XE_QUERY_CONFIG_VA_BITS 3 434 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 435 /** @info: array of elements containing the config info */ 436 __u64 info[]; 437 }; 438 439 /** 440 * struct drm_xe_gt - describe an individual GT. 441 * 442 * To be used with drm_xe_query_gt_list, which will return a list with all the 443 * existing GT individual descriptions. 444 * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for 445 * implementing graphics and/or media operations. 446 * 447 * The index in @type can be: 448 * - %DRM_XE_QUERY_GT_TYPE_MAIN 449 * - %DRM_XE_QUERY_GT_TYPE_MEDIA 450 */ 451 struct drm_xe_gt { 452 #define DRM_XE_QUERY_GT_TYPE_MAIN 0 453 #define DRM_XE_QUERY_GT_TYPE_MEDIA 1 454 /** @type: GT type: Main or Media */ 455 __u16 type; 456 /** @tile_id: Tile ID where this GT lives (Information only) */ 457 __u16 tile_id; 458 /** @gt_id: Unique ID of this GT within the PCI Device */ 459 __u16 gt_id; 460 /** @pad: MBZ */ 461 __u16 pad[3]; 462 /** @reference_clock: A clock frequency for timestamp */ 463 __u32 reference_clock; 464 /** 465 * @near_mem_regions: Bit mask of instances from 466 * drm_xe_query_mem_regions that are nearest to the current engines 467 * of this GT. 468 * Each index in this mask refers directly to the struct 469 * drm_xe_query_mem_regions' instance, no assumptions should 470 * be made about order. The type of each region is described 471 * by struct drm_xe_query_mem_regions' mem_class. 472 */ 473 __u64 near_mem_regions; 474 /** 475 * @far_mem_regions: Bit mask of instances from 476 * drm_xe_query_mem_regions that are far from the engines of this GT. 477 * In general, they have extra indirections when compared to the 478 * @near_mem_regions. For a discrete device this could mean system 479 * memory and memory living in a different tile. 480 * Each index in this mask refers directly to the struct 481 * drm_xe_query_mem_regions' instance, no assumptions should 482 * be made about order. The type of each region is described 483 * by struct drm_xe_query_mem_regions' mem_class. 484 */ 485 __u64 far_mem_regions; 486 /** @ip_ver_major: Graphics/media IP major version on GMD_ID platforms */ 487 __u16 ip_ver_major; 488 /** @ip_ver_minor: Graphics/media IP minor version on GMD_ID platforms */ 489 __u16 ip_ver_minor; 490 /** @ip_ver_rev: Graphics/media IP revision version on GMD_ID platforms */ 491 __u16 ip_ver_rev; 492 /** @pad2: MBZ */ 493 __u16 pad2; 494 /** @reserved: Reserved */ 495 __u64 reserved[7]; 496 }; 497 498 /** 499 * struct drm_xe_query_gt_list - A list with GT description items. 500 * 501 * If a query is made with a struct drm_xe_device_query where .query 502 * is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct 503 * drm_xe_query_gt_list in .data. 504 */ 505 struct drm_xe_query_gt_list { 506 /** @num_gt: number of GT items returned in gt_list */ 507 __u32 num_gt; 508 /** @pad: MBZ */ 509 __u32 pad; 510 /** @gt_list: The GT list returned for this device */ 511 struct drm_xe_gt gt_list[]; 512 }; 513 514 /** 515 * struct drm_xe_query_topology_mask - describe the topology mask of a GT 516 * 517 * This is the hardware topology which reflects the internal physical 518 * structure of the GPU. 519 * 520 * If a query is made with a struct drm_xe_device_query where .query 521 * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses 522 * struct drm_xe_query_topology_mask in .data. 523 * 524 * The @type can be: 525 * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices 526 * (DSS) available for geometry operations. For example a query response 527 * containing the following in mask: 528 * ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` 529 * means 32 DSS are available for geometry. 530 * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices 531 * (DSS) available for compute operations. For example a query response 532 * containing the following in mask: 533 * ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` 534 * means 32 DSS are available for compute. 535 * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type 536 * may be omitted if the driver is unable to query the mask from the 537 * hardware. 538 * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU) 539 * available per Dual Sub Slices (DSS). For example a query response 540 * containing the following in mask: 541 * ``EU_PER_DSS ff ff 00 00 00 00 00 00`` 542 * means each DSS has 16 SIMD8 EUs. This type may be omitted if device 543 * doesn't have SIMD8 EUs. 544 * - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution 545 * Units (EU) available per Dual Sub Slices (DSS). For example a query 546 * response containing the following in mask: 547 * ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` 548 * means each DSS has 16 SIMD16 EUs. This type may be omitted if device 549 * doesn't have SIMD16 EUs. 550 */ 551 struct drm_xe_query_topology_mask { 552 /** @gt_id: GT ID the mask is associated with */ 553 __u16 gt_id; 554 555 #define DRM_XE_TOPO_DSS_GEOMETRY 1 556 #define DRM_XE_TOPO_DSS_COMPUTE 2 557 #define DRM_XE_TOPO_L3_BANK 3 558 #define DRM_XE_TOPO_EU_PER_DSS 4 559 #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5 560 /** @type: type of mask */ 561 __u16 type; 562 563 /** @num_bytes: number of bytes in requested mask */ 564 __u32 num_bytes; 565 566 /** @mask: little-endian mask of @num_bytes */ 567 __u8 mask[]; 568 }; 569 570 /** 571 * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps 572 * 573 * If a query is made with a struct drm_xe_device_query where .query is equal to 574 * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles 575 * in .data. struct drm_xe_query_engine_cycles is allocated by the user and 576 * .data points to this allocated structure. 577 * 578 * The query returns the engine cycles, which along with GT's @reference_clock, 579 * can be used to calculate the engine timestamp. In addition the 580 * query returns a set of cpu timestamps that indicate when the command 581 * streamer cycle count was captured. 582 */ 583 struct drm_xe_query_engine_cycles { 584 /** 585 * @eci: This is input by the user and is the engine for which command 586 * streamer cycles is queried. 587 */ 588 struct drm_xe_engine_class_instance eci; 589 590 /** 591 * @clockid: This is input by the user and is the reference clock id for 592 * CPU timestamp. For definition, see clock_gettime(2) and 593 * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, 594 * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. 595 */ 596 __s32 clockid; 597 598 /** @width: Width of the engine cycle counter in bits. */ 599 __u32 width; 600 601 /** 602 * @engine_cycles: Engine cycles as read from its register 603 * at 0x358 offset. 604 */ 605 __u64 engine_cycles; 606 607 /** 608 * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before 609 * reading the engine_cycles register using the reference clockid set by the 610 * user. 611 */ 612 __u64 cpu_timestamp; 613 614 /** 615 * @cpu_delta: Time delta in ns captured around reading the lower dword 616 * of the engine_cycles register. 617 */ 618 __u64 cpu_delta; 619 }; 620 621 /** 622 * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version 623 * 624 * Given a uc_type this will return the branch, major, minor and patch version 625 * of the micro-controller firmware. 626 */ 627 struct drm_xe_query_uc_fw_version { 628 /** @uc_type: The micro-controller type to query firmware version */ 629 #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0 630 #define XE_QUERY_UC_TYPE_HUC 1 631 __u16 uc_type; 632 633 /** @pad: MBZ */ 634 __u16 pad; 635 636 /** @branch_ver: branch uc fw version */ 637 __u32 branch_ver; 638 /** @major_ver: major uc fw version */ 639 __u32 major_ver; 640 /** @minor_ver: minor uc fw version */ 641 __u32 minor_ver; 642 /** @patch_ver: patch uc fw version */ 643 __u32 patch_ver; 644 645 /** @pad2: MBZ */ 646 __u32 pad2; 647 648 /** @reserved: Reserved */ 649 __u64 reserved; 650 }; 651 652 /** 653 * struct drm_xe_query_pxp_status - query if PXP is ready 654 * 655 * If PXP is enabled and no fatal error has occurred, the status will be set to 656 * one of the following values: 657 * 0: PXP init still in progress 658 * 1: PXP init complete 659 * 660 * If PXP is not enabled or something has gone wrong, the query will be failed 661 * with one of the following error codes: 662 * -ENODEV: PXP not supported or disabled; 663 * -EIO: fatal error occurred during init, so PXP will never be enabled; 664 * -EINVAL: incorrect value provided as part of the query; 665 * -EFAULT: error copying the memory between kernel and userspace. 666 * 667 * The status can only be 0 in the first few seconds after driver load. If 668 * everything works as expected, the status will transition to init complete in 669 * less than 1 second, while in case of errors the driver might take longer to 670 * start returning an error code, but it should still take less than 10 seconds. 671 * 672 * The supported session type bitmask is based on the values in 673 * enum drm_xe_pxp_session_type. TYPE_NONE is always supported and therefore 674 * is not reported in the bitmask. 675 * 676 */ 677 struct drm_xe_query_pxp_status { 678 /** @status: current PXP status */ 679 __u32 status; 680 681 /** @supported_session_types: bitmask of supported PXP session types */ 682 __u32 supported_session_types; 683 }; 684 685 /** 686 * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main 687 * structure to query device information 688 * 689 * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_* 690 * and sets the value in the query member. This determines the type of 691 * the structure provided by the driver in data, among struct drm_xe_query_*. 692 * 693 * The @query can be: 694 * - %DRM_XE_DEVICE_QUERY_ENGINES 695 * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS 696 * - %DRM_XE_DEVICE_QUERY_CONFIG 697 * - %DRM_XE_DEVICE_QUERY_GT_LIST 698 * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware 699 * configuration of the device such as information on slices, memory, 700 * caches, and so on. It is provided as a table of key / value 701 * attributes. 702 * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 703 * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 704 * - %DRM_XE_DEVICE_QUERY_PXP_STATUS 705 * 706 * If size is set to 0, the driver fills it with the required size for 707 * the requested type of data to query. If size is equal to the required 708 * size, the queried information is copied into data. If size is set to 709 * a value different from 0 and different from the required size, the 710 * IOCTL call returns -EINVAL. 711 * 712 * For example the following code snippet allows retrieving and printing 713 * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES: 714 * 715 * .. code-block:: C 716 * 717 * struct drm_xe_query_engines *engines; 718 * struct drm_xe_device_query query = { 719 * .extensions = 0, 720 * .query = DRM_XE_DEVICE_QUERY_ENGINES, 721 * .size = 0, 722 * .data = 0, 723 * }; 724 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 725 * engines = malloc(query.size); 726 * query.data = (uintptr_t)engines; 727 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 728 * for (int i = 0; i < engines->num_engines; i++) { 729 * printf("Engine %d: %s\n", i, 730 * engines->engines[i].instance.engine_class == 731 * DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": 732 * engines->engines[i].instance.engine_class == 733 * DRM_XE_ENGINE_CLASS_COPY ? "COPY": 734 * engines->engines[i].instance.engine_class == 735 * DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": 736 * engines->engines[i].instance.engine_class == 737 * DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": 738 * engines->engines[i].instance.engine_class == 739 * DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": 740 * "UNKNOWN"); 741 * } 742 * free(engines); 743 */ 744 struct drm_xe_device_query { 745 /** @extensions: Pointer to the first extension struct, if any */ 746 __u64 extensions; 747 748 #define DRM_XE_DEVICE_QUERY_ENGINES 0 749 #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1 750 #define DRM_XE_DEVICE_QUERY_CONFIG 2 751 #define DRM_XE_DEVICE_QUERY_GT_LIST 3 752 #define DRM_XE_DEVICE_QUERY_HWCONFIG 4 753 #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 754 #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 755 #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7 756 #define DRM_XE_DEVICE_QUERY_OA_UNITS 8 757 #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9 758 #define DRM_XE_DEVICE_QUERY_EU_STALL 10 759 /** @query: The type of data to query */ 760 __u32 query; 761 762 /** @size: Size of the queried data */ 763 __u32 size; 764 765 /** @data: Queried data is placed here */ 766 __u64 data; 767 768 /** @reserved: Reserved */ 769 __u64 reserved[2]; 770 }; 771 772 /** 773 * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for 774 * gem creation 775 * 776 * The @flags can be: 777 * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING - Modify the GEM object 778 * allocation strategy by deferring physical memory allocation 779 * until the object is either bound to a virtual memory region via 780 * VM_BIND or accessed by the CPU. As a result, no backing memory is 781 * reserved at the time of GEM object creation. 782 * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT - Indicates that the GEM object is 783 * intended for scanout via the display engine. When set, kernel ensures 784 * that the allocation is placed in a memory region compatible with the 785 * display engine requirements. This may impose restrictions on tiling, 786 * alignment, and memory placement to guarantee proper display functionality. 787 * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a 788 * possible placement, ensure that the corresponding VRAM allocation 789 * will always use the CPU accessible part of VRAM. This is important 790 * for small-bar systems (on full-bar systems this gets turned into a 791 * noop). 792 * Note1: System memory can be used as an extra placement if the kernel 793 * should spill the allocation to system memory, if space can't be made 794 * available in the CPU accessible part of VRAM (giving the same 795 * behaviour as the i915 interface, see 796 * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). 797 * Note2: For clear-color CCS surfaces the kernel needs to read the 798 * clear-color value stored in the buffer, and on discrete platforms we 799 * need to use VRAM for display surfaces, therefore the kernel requires 800 * setting this flag for such objects, otherwise an error is thrown on 801 * small-bar systems. 802 * - %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION - Allows userspace to 803 * hint that compression (CCS) should be disabled for the buffer being 804 * created. This can avoid unnecessary memory operations and CCS state 805 * management. 806 * On pre-Xe2 platforms, this flag is currently rejected as compression 807 * control is not supported via PAT index. On Xe2+ platforms, compression 808 * is controlled via PAT entries. If this flag is set, the driver will reject 809 * any VM bind that requests a PAT index enabling compression for this BO. 810 * Note: On dGPU platforms, there is currently no change in behavior with 811 * this flag, but future improvements may leverage it. The current benefit is 812 * primarily applicable to iGPU platforms. 813 * 814 * @cpu_caching supports the following values: 815 * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back 816 * caching. On iGPU this can't be used for scanout surfaces. Currently 817 * not allowed for objects placed in VRAM. 818 * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This 819 * is uncached. Scanout surfaces should likely use this. All objects 820 * that can be placed in VRAM must use this. 821 * 822 * This ioctl supports setting the following properties via the 823 * %DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY extension, which uses the 824 * generic @drm_xe_ext_set_property struct: 825 * 826 * - %DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE - set the type of PXP session 827 * this object will be used with. Valid values are listed in enum 828 * drm_xe_pxp_session_type. %DRM_XE_PXP_TYPE_NONE is the default behavior, so 829 * there is no need to explicitly set that. Objects used with session of type 830 * %DRM_XE_PXP_TYPE_HWDRM will be marked as invalid if a PXP invalidation 831 * event occurs after their creation. Attempting to flip an invalid object 832 * will cause a black frame to be displayed instead. Submissions with invalid 833 * objects mapped in the VM will be rejected. 834 */ 835 struct drm_xe_gem_create { 836 #define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0 837 #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0 838 /** @extensions: Pointer to the first extension struct, if any */ 839 __u64 extensions; 840 841 /** 842 * @size: Size of the object to be created, must match region 843 * (system or vram) minimum alignment (&min_page_size). 844 */ 845 __u64 size; 846 847 /** 848 * @placement: A mask of memory instances of where BO can be placed. 849 * Each index in this mask refers directly to the struct 850 * drm_xe_query_mem_regions' instance, no assumptions should 851 * be made about order. The type of each region is described 852 * by struct drm_xe_query_mem_regions' mem_class. 853 */ 854 __u32 placement; 855 856 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0) 857 #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1) 858 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2) 859 #define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION (1 << 3) 860 /** 861 * @flags: Flags, currently a mask of memory instances of where BO can 862 * be placed 863 */ 864 __u32 flags; 865 866 /** 867 * @vm_id: Attached VM, if any 868 * 869 * If a VM is specified, this BO must: 870 * 871 * 1. Only ever be bound to that VM. 872 * 2. Cannot be exported as a PRIME fd. 873 */ 874 __u32 vm_id; 875 876 /** 877 * @handle: Returned handle for the object. 878 * 879 * Object handles are nonzero. 880 */ 881 __u32 handle; 882 883 #define DRM_XE_GEM_CPU_CACHING_WB 1 884 #define DRM_XE_GEM_CPU_CACHING_WC 2 885 /** 886 * @cpu_caching: The CPU caching mode to select for this object. If 887 * mmaping the object the mode selected here will also be used. The 888 * exception is when mapping system memory (including data evicted 889 * to system) on discrete GPUs. The caching mode selected will 890 * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency 891 * between GPU- and CPU is guaranteed. The caching mode of 892 * existing CPU-mappings will be updated transparently to 893 * user-space clients. 894 */ 895 __u16 cpu_caching; 896 /** @pad: MBZ */ 897 __u16 pad[3]; 898 899 /** @reserved: Reserved */ 900 __u64 reserved[2]; 901 }; 902 903 /** 904 * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET 905 * 906 * The @flags can be: 907 * - %DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER - For user to query special offset 908 * for use in mmap ioctl. Writing to the returned mmap address will generate a 909 * PCI memory barrier with low overhead (avoiding IOCTL call as well as writing 910 * to VRAM which would also add overhead), acting like an MI_MEM_FENCE 911 * instruction. 912 * 913 * Note: The mmap size can be at most 4K, due to HW limitations. As a result 914 * this interface is only supported on CPU architectures that support 4K page 915 * size. The mmap_offset ioctl will detect this and gracefully return an 916 * error, where userspace is expected to have a different fallback method for 917 * triggering a barrier. 918 * 919 * Roughly the usage would be as follows: 920 * 921 * .. code-block:: C 922 * 923 * struct drm_xe_gem_mmap_offset mmo = { 924 * .handle = 0, // must be set to 0 925 * .flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER, 926 * }; 927 * 928 * err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo); 929 * map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset); 930 * map[i] = 0xdeadbeaf; // issue barrier 931 */ 932 struct drm_xe_gem_mmap_offset { 933 /** @extensions: Pointer to the first extension struct, if any */ 934 __u64 extensions; 935 936 /** @handle: Handle for the object being mapped. */ 937 __u32 handle; 938 939 #define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0) 940 /** @flags: Flags */ 941 __u32 flags; 942 943 /** @offset: The fake offset to use for subsequent mmap call */ 944 __u64 offset; 945 946 /** @reserved: Reserved */ 947 __u64 reserved[2]; 948 }; 949 950 /** 951 * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE 952 * 953 * The @flags can be: 954 * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE - Map the whole virtual address 955 * space of the VM to scratch page. A vm_bind would overwrite the scratch 956 * page mapping. This flag is mutually exclusive with the 957 * %DRM_XE_VM_CREATE_FLAG_FAULT_MODE flag, with an exception of on x2 and 958 * xe3 platform. 959 * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts 960 * exec submissions to its exec_queues that don't have an upper time 961 * limit on the job execution time. But exec submissions to these 962 * don't allow any of the sync types DRM_XE_SYNC_TYPE_SYNCOBJ, 963 * DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ, used as out-syncobjs, that is, 964 * together with sync flag DRM_XE_SYNC_FLAG_SIGNAL. 965 * LR VMs can be created in recoverable page-fault mode using 966 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. 967 * If that flag is omitted, the UMD can not rely on the slightly 968 * different per-VM overcommit semantics that are enabled by 969 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may 970 * still enable recoverable pagefaults if supported by the device. 971 * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also 972 * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on 973 * demand when accessed, and also allows per-VM overcommit of memory. 974 * The xe driver internally uses recoverable pagefaults to implement 975 * this. 976 * - %DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT - Requires also 977 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE. This disallows per-VM overcommit 978 * but only during a &DRM_IOCTL_XE_VM_BIND operation with the 979 * %DRM_XE_VM_BIND_FLAG_IMMEDIATE flag set. This may be useful for 980 * user-space naively probing the amount of available memory. 981 */ 982 struct drm_xe_vm_create { 983 /** @extensions: Pointer to the first extension struct, if any */ 984 __u64 extensions; 985 986 #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0) 987 #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1) 988 #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2) 989 #define DRM_XE_VM_CREATE_FLAG_NO_VM_OVERCOMMIT (1 << 3) 990 /** @flags: Flags */ 991 __u32 flags; 992 993 /** @vm_id: Returned VM ID */ 994 __u32 vm_id; 995 996 /** @reserved: Reserved */ 997 __u64 reserved[2]; 998 }; 999 1000 /** 1001 * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY 1002 */ 1003 struct drm_xe_vm_destroy { 1004 /** @vm_id: VM ID */ 1005 __u32 vm_id; 1006 1007 /** @pad: MBZ */ 1008 __u32 pad; 1009 1010 /** @reserved: Reserved */ 1011 __u64 reserved[2]; 1012 }; 1013 1014 /** 1015 * struct drm_xe_vm_bind_op - run bind operations 1016 * 1017 * The @op can be: 1018 * - %DRM_XE_VM_BIND_OP_MAP 1019 * - %DRM_XE_VM_BIND_OP_UNMAP 1020 * - %DRM_XE_VM_BIND_OP_MAP_USERPTR 1021 * - %DRM_XE_VM_BIND_OP_UNMAP_ALL 1022 * - %DRM_XE_VM_BIND_OP_PREFETCH 1023 * 1024 * and the @flags can be: 1025 * - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only 1026 * to ensure write protection 1027 * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the 1028 * MAP operation immediately rather than deferring the MAP to the page 1029 * fault handler. This is implied on a non-faulting VM as there is no 1030 * fault handler to defer to. 1031 * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page 1032 * tables are setup with a special bit which indicates writes are 1033 * dropped and all reads return zero. In the future, the NULL flags 1034 * will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO 1035 * handle MBZ, and the BO offset MBZ. This flag is intended to 1036 * implement VK sparse bindings. 1037 * - %DRM_XE_VM_BIND_FLAG_CHECK_PXP - If the object is encrypted via PXP, 1038 * reject the binding if the encryption key is no longer valid. This 1039 * flag has no effect on BOs that are not marked as using PXP. 1040 * - %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR - When the CPU address mirror flag is 1041 * set, no mappings are created rather the range is reserved for CPU address 1042 * mirroring which will be populated on GPU page faults or prefetches. Only 1043 * valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address 1044 * mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO 1045 * handle MBZ, and the BO offset MBZ. 1046 * - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with 1047 * %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying 1048 * CPU address space range is unmapped (typically with munmap(2) or brk(2)). 1049 * The madvise values set with &DRM_IOCTL_XE_MADVISE are reset to the values 1050 * that were present immediately after the &DRM_IOCTL_XE_VM_BIND. 1051 * The reset GPU virtual address range is the intersection of the range bound 1052 * using &DRM_IOCTL_XE_VM_BIND and the virtual CPU address space range 1053 * unmapped. 1054 * This functionality is present to mimic the behaviour of CPU address space 1055 * madvises set using madvise(2), which are typically reset on unmap. 1056 * Note: free(3) may or may not call munmap(2) and/or brk(2), and may thus 1057 * not invoke autoreset. Neither will stack variables going out of scope. 1058 * Therefore it's recommended to always explicitly reset the madvises when 1059 * freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call. 1060 * - DRM_XE_VM_BIND_FLAG_DECOMPRESS - Request on-device decompression for a MAP. 1061 * When set on a MAP bind operation, request the driver schedule an on-device 1062 * in-place decompression (via the migrate/resolve path) for the GPU mapping 1063 * created by this bind. Only valid for DRM_XE_VM_BIND_OP_MAP; usage on 1064 * other ops is rejected. The bind's pat_index must select the device's 1065 * "no-compression" PAT. Only meaningful for VRAM-backed BOs on devices that 1066 * support Flat CCS and the required HW generation XE2+. 1067 * 1068 * The @prefetch_mem_region_instance for %DRM_XE_VM_BIND_OP_PREFETCH can also be: 1069 * - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in 1070 * the memory region advised by madvise. 1071 */ 1072 struct drm_xe_vm_bind_op { 1073 /** @extensions: Pointer to the first extension struct, if any */ 1074 __u64 extensions; 1075 1076 /** 1077 * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP 1078 */ 1079 __u32 obj; 1080 1081 /** 1082 * @pat_index: The platform defined @pat_index to use for this mapping. 1083 * The index basically maps to some predefined memory attributes, 1084 * including things like caching, coherency, compression etc. The exact 1085 * meaning of the pat_index is platform specific and defined in the 1086 * Bspec and PRMs. When the KMD sets up the binding the index here is 1087 * encoded into the ppGTT PTE. 1088 * 1089 * For coherency the @pat_index needs to be at least 1way coherent when 1090 * drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD 1091 * will extract the coherency mode from the @pat_index and reject if 1092 * there is a mismatch (see note below for pre-MTL platforms). 1093 * 1094 * Note: On pre-MTL platforms there is only a caching mode and no 1095 * explicit coherency mode, but on such hardware there is always a 1096 * shared-LLC (or is dgpu) so all GT memory accesses are coherent with 1097 * CPU caches even with the caching mode set as uncached. It's only the 1098 * display engine that is incoherent (on dgpu it must be in VRAM which 1099 * is always mapped as WC on the CPU). However to keep the uapi somewhat 1100 * consistent with newer platforms the KMD groups the different cache 1101 * levels into the following coherency buckets on all pre-MTL platforms: 1102 * 1103 * ppGTT UC -> COH_NONE 1104 * ppGTT WC -> COH_NONE 1105 * ppGTT WT -> COH_NONE 1106 * ppGTT WB -> COH_AT_LEAST_1WAY 1107 * 1108 * In practice UC/WC/WT should only ever used for scanout surfaces on 1109 * such platforms (or perhaps in general for dma-buf if shared with 1110 * another device) since it is only the display engine that is actually 1111 * incoherent. Everything else should typically use WB given that we 1112 * have a shared-LLC. On MTL+ this completely changes and the HW 1113 * defines the coherency mode as part of the @pat_index, where 1114 * incoherent GT access is possible. 1115 * 1116 * Note: For userptr and externally imported dma-buf the kernel expects 1117 * either 1WAY or 2WAY for the @pat_index. 1118 * 1119 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions 1120 * on the @pat_index. For such mappings there is no actual memory being 1121 * mapped (the address in the PTE is invalid), so the various PAT memory 1122 * attributes likely do not apply. Simply leaving as zero is one 1123 * option (still a valid pat_index). Same applies to 1124 * DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping 1125 * there is no actual memory being mapped. 1126 */ 1127 __u16 pat_index; 1128 1129 /** @pad: MBZ */ 1130 __u16 pad; 1131 1132 union { 1133 /** 1134 * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE, 1135 * ignored for unbind 1136 */ 1137 __u64 obj_offset; 1138 1139 /** @userptr: user pointer to bind on */ 1140 __u64 userptr; 1141 1142 /** 1143 * @cpu_addr_mirror_offset: Offset from GPU @addr to create 1144 * CPU address mirror mappings. MBZ with current level of 1145 * support (e.g. 1 to 1 mapping between GPU and CPU mappings 1146 * only supported). 1147 */ 1148 __s64 cpu_addr_mirror_offset; 1149 }; 1150 1151 /** 1152 * @range: Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL 1153 */ 1154 __u64 range; 1155 1156 /** @addr: Address to operate on, MBZ for UNMAP_ALL */ 1157 __u64 addr; 1158 1159 #define DRM_XE_VM_BIND_OP_MAP 0x0 1160 #define DRM_XE_VM_BIND_OP_UNMAP 0x1 1161 #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2 1162 #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3 1163 #define DRM_XE_VM_BIND_OP_PREFETCH 0x4 1164 /** @op: Bind operation to perform */ 1165 __u32 op; 1166 1167 #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0) 1168 #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1) 1169 #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2) 1170 #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3) 1171 #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4) 1172 #define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5) 1173 #define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET (1 << 6) 1174 #define DRM_XE_VM_BIND_FLAG_DECOMPRESS (1 << 7) 1175 /** @flags: Bind flags */ 1176 __u32 flags; 1177 1178 #define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC -1 1179 /** 1180 * @prefetch_mem_region_instance: Memory region to prefetch VMA to. 1181 * It is a region instance, not a mask. 1182 * To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation. 1183 */ 1184 __u32 prefetch_mem_region_instance; 1185 1186 /** @pad2: MBZ */ 1187 __u32 pad2; 1188 1189 /** @reserved: Reserved */ 1190 __u64 reserved[3]; 1191 }; 1192 1193 /** 1194 * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND 1195 * 1196 * Below is an example of a minimal use of @drm_xe_vm_bind to 1197 * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to 1198 * illustrate `userptr`. It can be synchronized by using the example 1199 * provided for @drm_xe_sync. 1200 * 1201 * .. code-block:: C 1202 * 1203 * data = aligned_alloc(ALIGNMENT, BO_SIZE); 1204 * struct drm_xe_vm_bind bind = { 1205 * .vm_id = vm, 1206 * .num_binds = 1, 1207 * .bind.obj = 0, 1208 * .bind.obj_offset = to_user_pointer(data), 1209 * .bind.range = BO_SIZE, 1210 * .bind.addr = BIND_ADDRESS, 1211 * .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, 1212 * .bind.flags = 0, 1213 * .num_syncs = 1, 1214 * .syncs = &sync, 1215 * .exec_queue_id = 0, 1216 * }; 1217 * ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind); 1218 * 1219 */ 1220 struct drm_xe_vm_bind { 1221 /** @extensions: Pointer to the first extension struct, if any */ 1222 __u64 extensions; 1223 1224 /** @vm_id: The ID of the VM to bind to */ 1225 __u32 vm_id; 1226 1227 /** 1228 * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND 1229 * and exec queue must have same vm_id. If zero, the default VM bind engine 1230 * is used. 1231 */ 1232 __u32 exec_queue_id; 1233 1234 /** @pad: MBZ */ 1235 __u32 pad; 1236 1237 /** @num_binds: number of binds in this IOCTL */ 1238 __u32 num_binds; 1239 1240 union { 1241 /** @bind: used if num_binds == 1 */ 1242 struct drm_xe_vm_bind_op bind; 1243 1244 /** 1245 * @vector_of_binds: userptr to array of struct 1246 * drm_xe_vm_bind_op if num_binds > 1 1247 */ 1248 __u64 vector_of_binds; 1249 }; 1250 1251 /** @pad2: MBZ */ 1252 __u32 pad2; 1253 1254 /** @num_syncs: amount of syncs to wait on */ 1255 __u32 num_syncs; 1256 1257 /** @syncs: pointer to struct drm_xe_sync array */ 1258 __u64 syncs; 1259 1260 /** @reserved: Reserved */ 1261 __u64 reserved[2]; 1262 }; 1263 1264 /** 1265 * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE 1266 * 1267 * This ioctl supports setting the following properties via the 1268 * %DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY extension, which uses the 1269 * generic @drm_xe_ext_set_property struct: 1270 * 1271 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY - set the queue priority. 1272 * CAP_SYS_NICE is required to set a value above normal. 1273 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE - set the queue timeslice 1274 * duration in microseconds. 1275 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE - set the type of PXP session 1276 * this queue will be used with. Valid values are listed in enum 1277 * drm_xe_pxp_session_type. %DRM_XE_PXP_TYPE_NONE is the default behavior, so 1278 * there is no need to explicitly set that. When a queue of type 1279 * %DRM_XE_PXP_TYPE_HWDRM is created, the PXP default HWDRM session 1280 * (%XE_PXP_HWDRM_DEFAULT_SESSION) will be started, if isn't already running. 1281 * The user is expected to query the PXP status via the query ioctl (see 1282 * %DRM_XE_DEVICE_QUERY_PXP_STATUS) and to wait for PXP to be ready before 1283 * attempting to create a queue with this property. When a queue is created 1284 * before PXP is ready, the ioctl will return -EBUSY if init is still in 1285 * progress or -EIO if init failed. 1286 * Given that going into a power-saving state kills PXP HWDRM sessions, 1287 * runtime PM will be blocked while queues of this type are alive. 1288 * All PXP queues will be killed if a PXP invalidation event occurs. 1289 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP - Create a multi-queue group 1290 * or add secondary queues to a multi-queue group. 1291 * If the extension's 'value' field has %DRM_XE_MULTI_GROUP_CREATE flag set, 1292 * then a new multi-queue group is created with this queue as the primary queue 1293 * (Q0). Otherwise, the queue gets added to the multi-queue group whose primary 1294 * queue's exec_queue_id is specified in the lower 32 bits of the 'value' field. 1295 * All the other non-relevant bits of extension's 'value' field while adding the 1296 * primary or the secondary queues of the group must be set to 0. 1297 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY - Set the queue 1298 * priority within the multi-queue group. Current valid priority values are 0–2 1299 * (default is 1), with higher values indicating higher priority. 1300 * - %DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX - Set the queue to 1301 * enable render color cache keying on BTP+BTI instead of just BTI 1302 * (only valid for render queues). 1303 * 1304 * The example below shows how to use @drm_xe_exec_queue_create to create 1305 * a simple exec_queue (no parallel submission) of class 1306 * &DRM_XE_ENGINE_CLASS_RENDER. 1307 * 1308 * .. code-block:: C 1309 * 1310 * struct drm_xe_engine_class_instance instance = { 1311 * .engine_class = DRM_XE_ENGINE_CLASS_RENDER, 1312 * }; 1313 * struct drm_xe_exec_queue_create exec_queue_create = { 1314 * .extensions = 0, 1315 * .vm_id = vm, 1316 * .num_bb_per_exec = 1, 1317 * .num_eng_per_bb = 1, 1318 * .instances = to_user_pointer(&instance), 1319 * }; 1320 * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); 1321 * 1322 * Allow users to provide a hint to kernel for cases demanding low latency 1323 * profile. Please note it will have impact on power consumption. User can 1324 * indicate low latency hint with flag while creating exec queue as 1325 * mentioned below, 1326 * 1327 * struct drm_xe_exec_queue_create exec_queue_create = { 1328 * .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT, 1329 * .extensions = 0, 1330 * .vm_id = vm, 1331 * .num_bb_per_exec = 1, 1332 * .num_eng_per_bb = 1, 1333 * .instances = to_user_pointer(&instance), 1334 * }; 1335 * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); 1336 * 1337 */ 1338 struct drm_xe_exec_queue_create { 1339 #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 1340 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 1341 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 1342 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2 1343 #define DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE 3 1344 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_GROUP 4 1345 #define DRM_XE_MULTI_GROUP_CREATE (1ull << 63) 1346 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 5 1347 #define DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX 6 1348 /** @extensions: Pointer to the first extension struct, if any */ 1349 __u64 extensions; 1350 1351 /** @width: submission width (number BB per exec) for this exec queue */ 1352 __u16 width; 1353 1354 /** @num_placements: number of valid placements for this exec queue */ 1355 __u16 num_placements; 1356 1357 /** @vm_id: VM to use for this exec queue */ 1358 __u32 vm_id; 1359 1360 #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0) 1361 /** @flags: flags to use for this exec queue */ 1362 __u32 flags; 1363 1364 /** @exec_queue_id: Returned exec queue ID */ 1365 __u32 exec_queue_id; 1366 1367 /** 1368 * @instances: user pointer to a 2-d array of struct 1369 * drm_xe_engine_class_instance 1370 * 1371 * length = width (i) * num_placements (j) 1372 * index = j + i * width 1373 */ 1374 __u64 instances; 1375 1376 /** @reserved: Reserved */ 1377 __u64 reserved[2]; 1378 }; 1379 1380 /** 1381 * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY 1382 */ 1383 struct drm_xe_exec_queue_destroy { 1384 /** @exec_queue_id: Exec queue ID */ 1385 __u32 exec_queue_id; 1386 1387 /** @pad: MBZ */ 1388 __u32 pad; 1389 1390 /** @reserved: Reserved */ 1391 __u64 reserved[2]; 1392 }; 1393 1394 /** 1395 * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY 1396 * 1397 * The @property can be: 1398 * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 1399 */ 1400 struct drm_xe_exec_queue_get_property { 1401 /** @extensions: Pointer to the first extension struct, if any */ 1402 __u64 extensions; 1403 1404 /** @exec_queue_id: Exec queue ID */ 1405 __u32 exec_queue_id; 1406 1407 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 1408 /** @property: property to get */ 1409 __u32 property; 1410 1411 /** @value: property value */ 1412 __u64 value; 1413 1414 /** @reserved: Reserved */ 1415 __u64 reserved[2]; 1416 }; 1417 1418 /** 1419 * struct drm_xe_sync - sync object 1420 * 1421 * The @type can be: 1422 * - %DRM_XE_SYNC_TYPE_SYNCOBJ 1423 * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 1424 * - %DRM_XE_SYNC_TYPE_USER_FENCE 1425 * 1426 * and the @flags can be: 1427 * - %DRM_XE_SYNC_FLAG_SIGNAL 1428 * 1429 * A minimal use of @drm_xe_sync looks like this: 1430 * 1431 * .. code-block:: C 1432 * 1433 * struct drm_xe_sync sync = { 1434 * .flags = DRM_XE_SYNC_FLAG_SIGNAL, 1435 * .type = DRM_XE_SYNC_TYPE_SYNCOBJ, 1436 * }; 1437 * struct drm_syncobj_create syncobj_create = { 0 }; 1438 * ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); 1439 * sync.handle = syncobj_create.handle; 1440 * ... 1441 * use of &sync in drm_xe_exec or drm_xe_vm_bind 1442 * ... 1443 * struct drm_syncobj_wait wait = { 1444 * .handles = &sync.handle, 1445 * .timeout_nsec = INT64_MAX, 1446 * .count_handles = 1, 1447 * .flags = 0, 1448 * .first_signaled = 0, 1449 * .pad = 0, 1450 * }; 1451 * ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait); 1452 */ 1453 struct drm_xe_sync { 1454 /** @extensions: Pointer to the first extension struct, if any */ 1455 __u64 extensions; 1456 1457 #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0 1458 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1 1459 #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2 1460 /** @type: Type of the this sync object */ 1461 __u32 type; 1462 1463 #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0) 1464 /** @flags: Sync Flags */ 1465 __u32 flags; 1466 1467 union { 1468 /** @handle: Handle for the object */ 1469 __u32 handle; 1470 1471 /** 1472 * @addr: Address of user fence. When sync is passed in via exec 1473 * IOCTL this is a GPU address in the VM. When sync passed in via 1474 * VM bind IOCTL this is a user pointer. In either case, it is 1475 * the users responsibility that this address is present and 1476 * mapped when the user fence is signalled. Must be qword 1477 * aligned. 1478 */ 1479 __u64 addr; 1480 }; 1481 1482 /** 1483 * @timeline_value: Input for the timeline sync object. Needs to be 1484 * different than 0 when used with %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ. 1485 */ 1486 __u64 timeline_value; 1487 1488 /** @reserved: Reserved */ 1489 __u64 reserved[2]; 1490 }; 1491 1492 /** 1493 * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC 1494 * 1495 * This is an example to use @drm_xe_exec for execution of the object 1496 * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue 1497 * (see example in @drm_xe_exec_queue_create). It can be synchronized 1498 * by using the example provided for @drm_xe_sync. 1499 * 1500 * .. code-block:: C 1501 * 1502 * struct drm_xe_exec exec = { 1503 * .exec_queue_id = exec_queue, 1504 * .syncs = &sync, 1505 * .num_syncs = 1, 1506 * .address = BIND_ADDRESS, 1507 * .num_batch_buffer = 1, 1508 * }; 1509 * ioctl(fd, DRM_IOCTL_XE_EXEC, &exec); 1510 * 1511 */ 1512 struct drm_xe_exec { 1513 /** @extensions: Pointer to the first extension struct, if any */ 1514 __u64 extensions; 1515 1516 /** @exec_queue_id: Exec queue ID for the batch buffer */ 1517 __u32 exec_queue_id; 1518 1519 #define DRM_XE_MAX_SYNCS 1024 1520 /** @num_syncs: Amount of struct drm_xe_sync in array. */ 1521 __u32 num_syncs; 1522 1523 /** @syncs: Pointer to struct drm_xe_sync array. */ 1524 __u64 syncs; 1525 1526 /** 1527 * @address: address of batch buffer if num_batch_buffer == 1 or an 1528 * array of batch buffer addresses 1529 */ 1530 __u64 address; 1531 1532 /** 1533 * @num_batch_buffer: number of batch buffer in this exec, must match 1534 * the width of the engine 1535 */ 1536 __u16 num_batch_buffer; 1537 1538 /** @pad: MBZ */ 1539 __u16 pad[3]; 1540 1541 /** @reserved: Reserved */ 1542 __u64 reserved[2]; 1543 }; 1544 1545 /** 1546 * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE 1547 * 1548 * Wait on user fence, XE will wake-up on every HW engine interrupt in the 1549 * instances list and check if user fence is complete:: 1550 * 1551 * (*addr & MASK) OP (VALUE & MASK) 1552 * 1553 * Returns to user on user fence completion or timeout. 1554 * 1555 * The @op can be: 1556 * - %DRM_XE_UFENCE_WAIT_OP_EQ 1557 * - %DRM_XE_UFENCE_WAIT_OP_NEQ 1558 * - %DRM_XE_UFENCE_WAIT_OP_GT 1559 * - %DRM_XE_UFENCE_WAIT_OP_GTE 1560 * - %DRM_XE_UFENCE_WAIT_OP_LT 1561 * - %DRM_XE_UFENCE_WAIT_OP_LTE 1562 * 1563 * and the @flags can be: 1564 * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME 1565 * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP 1566 * 1567 * The @mask values can be for example: 1568 * - 0xffu for u8 1569 * - 0xffffu for u16 1570 * - 0xffffffffu for u32 1571 * - 0xffffffffffffffffu for u64 1572 */ 1573 struct drm_xe_wait_user_fence { 1574 /** @extensions: Pointer to the first extension struct, if any */ 1575 __u64 extensions; 1576 1577 /** 1578 * @addr: user pointer address to wait on, must qword aligned 1579 */ 1580 __u64 addr; 1581 1582 #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0 1583 #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1 1584 #define DRM_XE_UFENCE_WAIT_OP_GT 0x2 1585 #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3 1586 #define DRM_XE_UFENCE_WAIT_OP_LT 0x4 1587 #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5 1588 /** @op: wait operation (type of comparison) */ 1589 __u16 op; 1590 1591 #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) 1592 /** @flags: wait flags */ 1593 __u16 flags; 1594 1595 /** @pad: MBZ */ 1596 __u32 pad; 1597 1598 /** @value: compare value */ 1599 __u64 value; 1600 1601 /** @mask: comparison mask */ 1602 __u64 mask; 1603 1604 /** 1605 * @timeout: how long to wait before bailing, value in nanoseconds. 1606 * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) 1607 * it contains timeout expressed in nanoseconds to wait (fence will 1608 * expire at now() + timeout). 1609 * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait 1610 * will end at timeout (uses system MONOTONIC_CLOCK). 1611 * Passing negative timeout leads to neverending wait. 1612 * 1613 * On relative timeout this value is updated with timeout left 1614 * (for restarting the call in case of signal delivery). 1615 * On absolute timeout this value stays intact (restarted call still 1616 * expire at the same point of time). 1617 */ 1618 __s64 timeout; 1619 1620 /** @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl */ 1621 __u32 exec_queue_id; 1622 1623 /** @pad2: MBZ */ 1624 __u32 pad2; 1625 1626 /** @reserved: Reserved */ 1627 __u64 reserved[2]; 1628 }; 1629 1630 /** 1631 * enum drm_xe_observation_type - Observation stream types 1632 */ 1633 enum drm_xe_observation_type { 1634 /** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */ 1635 DRM_XE_OBSERVATION_TYPE_OA, 1636 /** @DRM_XE_OBSERVATION_TYPE_EU_STALL: EU stall sampling observation stream type */ 1637 DRM_XE_OBSERVATION_TYPE_EU_STALL, 1638 }; 1639 1640 /** 1641 * enum drm_xe_observation_op - Observation stream ops 1642 */ 1643 enum drm_xe_observation_op { 1644 /** @DRM_XE_OBSERVATION_OP_STREAM_OPEN: Open an observation stream */ 1645 DRM_XE_OBSERVATION_OP_STREAM_OPEN, 1646 1647 /** @DRM_XE_OBSERVATION_OP_ADD_CONFIG: Add observation stream config */ 1648 DRM_XE_OBSERVATION_OP_ADD_CONFIG, 1649 1650 /** @DRM_XE_OBSERVATION_OP_REMOVE_CONFIG: Remove observation stream config */ 1651 DRM_XE_OBSERVATION_OP_REMOVE_CONFIG, 1652 }; 1653 1654 /** 1655 * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION 1656 * 1657 * The observation layer enables multiplexing observation streams of 1658 * multiple types. The actual params for a particular stream operation are 1659 * supplied via the @param pointer (use __copy_from_user to get these 1660 * params). 1661 */ 1662 struct drm_xe_observation_param { 1663 /** @extensions: Pointer to the first extension struct, if any */ 1664 __u64 extensions; 1665 /** @observation_type: observation stream type, of enum @drm_xe_observation_type */ 1666 __u64 observation_type; 1667 /** @observation_op: observation stream op, of enum @drm_xe_observation_op */ 1668 __u64 observation_op; 1669 /** @param: Pointer to actual stream params */ 1670 __u64 param; 1671 }; 1672 1673 /** 1674 * enum drm_xe_observation_ioctls - Observation stream fd ioctl's 1675 * 1676 * Information exchanged between userspace and kernel for observation fd 1677 * ioctl's is stream type specific 1678 */ 1679 enum drm_xe_observation_ioctls { 1680 /** @DRM_XE_OBSERVATION_IOCTL_ENABLE: Enable data capture for an observation stream */ 1681 DRM_XE_OBSERVATION_IOCTL_ENABLE = _IO('i', 0x0), 1682 1683 /** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for a observation stream */ 1684 DRM_XE_OBSERVATION_IOCTL_DISABLE = _IO('i', 0x1), 1685 1686 /** @DRM_XE_OBSERVATION_IOCTL_CONFIG: Change observation stream configuration */ 1687 DRM_XE_OBSERVATION_IOCTL_CONFIG = _IO('i', 0x2), 1688 1689 /** @DRM_XE_OBSERVATION_IOCTL_STATUS: Return observation stream status */ 1690 DRM_XE_OBSERVATION_IOCTL_STATUS = _IO('i', 0x3), 1691 1692 /** @DRM_XE_OBSERVATION_IOCTL_INFO: Return observation stream info */ 1693 DRM_XE_OBSERVATION_IOCTL_INFO = _IO('i', 0x4), 1694 }; 1695 1696 /** 1697 * enum drm_xe_oa_unit_type - OA unit types 1698 */ 1699 enum drm_xe_oa_unit_type { 1700 /** 1701 * @DRM_XE_OA_UNIT_TYPE_OAG: OAG OA unit. OAR/OAC are considered 1702 * sub-types of OAG. For OAR/OAC, use OAG. 1703 */ 1704 DRM_XE_OA_UNIT_TYPE_OAG, 1705 1706 /** @DRM_XE_OA_UNIT_TYPE_OAM: OAM OA unit */ 1707 DRM_XE_OA_UNIT_TYPE_OAM, 1708 1709 /** @DRM_XE_OA_UNIT_TYPE_OAM_SAG: OAM_SAG OA unit */ 1710 DRM_XE_OA_UNIT_TYPE_OAM_SAG, 1711 1712 /** @DRM_XE_OA_UNIT_TYPE_MERT: MERT OA unit */ 1713 DRM_XE_OA_UNIT_TYPE_MERT, 1714 }; 1715 1716 /** 1717 * struct drm_xe_oa_unit - describe OA unit 1718 */ 1719 struct drm_xe_oa_unit { 1720 /** @extensions: Pointer to the first extension struct, if any */ 1721 __u64 extensions; 1722 1723 /** @oa_unit_id: OA unit ID */ 1724 __u32 oa_unit_id; 1725 1726 /** @oa_unit_type: OA unit type of @drm_xe_oa_unit_type */ 1727 __u32 oa_unit_type; 1728 1729 /** @capabilities: OA capabilities bit-mask */ 1730 __u64 capabilities; 1731 #define DRM_XE_OA_CAPS_BASE (1 << 0) 1732 #define DRM_XE_OA_CAPS_SYNCS (1 << 1) 1733 #define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2) 1734 #define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3) 1735 #define DRM_XE_OA_CAPS_OAM (1 << 4) 1736 #define DRM_XE_OA_CAPS_OA_UNIT_GT_ID (1 << 5) 1737 1738 /** @oa_timestamp_freq: OA timestamp freq */ 1739 __u64 oa_timestamp_freq; 1740 1741 /** @gt_id: gt id for this OA unit */ 1742 __u16 gt_id; 1743 1744 /** @reserved1: MBZ */ 1745 __u16 reserved1[3]; 1746 1747 /** @reserved: MBZ */ 1748 __u64 reserved[3]; 1749 1750 /** @num_engines: number of engines in @eci array */ 1751 __u64 num_engines; 1752 1753 /** @eci: engines attached to this OA unit */ 1754 struct drm_xe_engine_class_instance eci[]; 1755 }; 1756 1757 /** 1758 * struct drm_xe_query_oa_units - describe OA units 1759 * 1760 * If a query is made with a struct drm_xe_device_query where .query 1761 * is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct 1762 * drm_xe_query_oa_units in .data. 1763 * 1764 * OA unit properties for all OA units can be accessed using a code block 1765 * such as the one below: 1766 * 1767 * .. code-block:: C 1768 * 1769 * struct drm_xe_query_oa_units *qoa; 1770 * struct drm_xe_oa_unit *oau; 1771 * u8 *poau; 1772 * 1773 * // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then: 1774 * poau = (u8 *)&qoa->oa_units[0]; 1775 * for (int i = 0; i < qoa->num_oa_units; i++) { 1776 * oau = (struct drm_xe_oa_unit *)poau; 1777 * // Access 'struct drm_xe_oa_unit' fields here 1778 * poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]); 1779 * } 1780 */ 1781 struct drm_xe_query_oa_units { 1782 /** @extensions: Pointer to the first extension struct, if any */ 1783 __u64 extensions; 1784 /** @num_oa_units: number of OA units returned in oau[] */ 1785 __u32 num_oa_units; 1786 /** @pad: MBZ */ 1787 __u32 pad; 1788 /** 1789 * @oa_units: struct @drm_xe_oa_unit array returned for this device. 1790 * Written below as a u64 array to avoid problems with nested flexible 1791 * arrays with some compilers 1792 */ 1793 __u64 oa_units[]; 1794 }; 1795 1796 /** 1797 * enum drm_xe_oa_format_type - OA format types as specified in PRM/Bspec 1798 * 52198/60942 1799 */ 1800 enum drm_xe_oa_format_type { 1801 /** @DRM_XE_OA_FMT_TYPE_OAG: OAG report format */ 1802 DRM_XE_OA_FMT_TYPE_OAG, 1803 /** @DRM_XE_OA_FMT_TYPE_OAR: OAR report format */ 1804 DRM_XE_OA_FMT_TYPE_OAR, 1805 /** @DRM_XE_OA_FMT_TYPE_OAM: OAM report format */ 1806 DRM_XE_OA_FMT_TYPE_OAM, 1807 /** @DRM_XE_OA_FMT_TYPE_OAC: OAC report format */ 1808 DRM_XE_OA_FMT_TYPE_OAC, 1809 /** @DRM_XE_OA_FMT_TYPE_OAM_MPEC: OAM SAMEDIA or OAM MPEC report format */ 1810 DRM_XE_OA_FMT_TYPE_OAM_MPEC, 1811 /** @DRM_XE_OA_FMT_TYPE_PEC: PEC report format */ 1812 DRM_XE_OA_FMT_TYPE_PEC, 1813 }; 1814 1815 /** 1816 * enum drm_xe_oa_property_id - OA stream property id's 1817 * 1818 * Stream params are specified as a chain of @drm_xe_ext_set_property 1819 * struct's, with @property values from enum @drm_xe_oa_property_id and 1820 * @drm_xe_user_extension base.name set to @DRM_XE_OA_EXTENSION_SET_PROPERTY. 1821 * @param field in struct @drm_xe_observation_param points to the first 1822 * @drm_xe_ext_set_property struct. 1823 * 1824 * Exactly the same mechanism is also used for stream reconfiguration using the 1825 * @DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a 1826 * subset of properties below can be specified for stream reconfiguration. 1827 */ 1828 enum drm_xe_oa_property_id { 1829 #define DRM_XE_OA_EXTENSION_SET_PROPERTY 0 1830 /** 1831 * @DRM_XE_OA_PROPERTY_OA_UNIT_ID: ID of the OA unit on which to open 1832 * the OA stream, see @oa_unit_id in 'struct 1833 * drm_xe_query_oa_units'. Defaults to 0 if not provided. 1834 */ 1835 DRM_XE_OA_PROPERTY_OA_UNIT_ID = 1, 1836 1837 /** 1838 * @DRM_XE_OA_PROPERTY_SAMPLE_OA: A value of 1 requests inclusion of raw 1839 * OA unit reports or stream samples in a global buffer attached to an 1840 * OA unit. 1841 */ 1842 DRM_XE_OA_PROPERTY_SAMPLE_OA, 1843 1844 /** 1845 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET: OA metrics defining contents of OA 1846 * reports, previously added via @DRM_XE_OBSERVATION_OP_ADD_CONFIG. 1847 */ 1848 DRM_XE_OA_PROPERTY_OA_METRIC_SET, 1849 1850 /** @DRM_XE_OA_PROPERTY_OA_FORMAT: OA counter report format */ 1851 DRM_XE_OA_PROPERTY_OA_FORMAT, 1852 /* 1853 * OA_FORMAT's are specified the same way as in PRM/Bspec 52198/60942, 1854 * in terms of the following quantities: a. enum @drm_xe_oa_format_type 1855 * b. Counter select c. Counter size and d. BC report. Also refer to the 1856 * oa_formats array in drivers/gpu/drm/xe/xe_oa.c. 1857 */ 1858 #define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xffu << 0) 1859 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xffu << 8) 1860 #define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xffu << 16) 1861 #define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xffu << 24) 1862 1863 /** 1864 * @DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT: Requests periodic OA unit 1865 * sampling with sampling frequency proportional to 2^(period_exponent + 1) 1866 */ 1867 DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT, 1868 1869 /** 1870 * @DRM_XE_OA_PROPERTY_OA_DISABLED: A value of 1 will open the OA 1871 * stream in a DISABLED state (see @DRM_XE_OBSERVATION_IOCTL_ENABLE). 1872 */ 1873 DRM_XE_OA_PROPERTY_OA_DISABLED, 1874 1875 /** 1876 * @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID: Open the stream for a specific 1877 * @exec_queue_id. OA queries can be executed on this exec queue. 1878 */ 1879 DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID, 1880 1881 /** 1882 * @DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE: Optional engine instance to 1883 * pass along with @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0. 1884 */ 1885 DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE, 1886 1887 /** 1888 * @DRM_XE_OA_PROPERTY_NO_PREEMPT: Allow preemption and timeslicing 1889 * to be disabled for the stream exec queue. 1890 */ 1891 DRM_XE_OA_PROPERTY_NO_PREEMPT, 1892 1893 /** 1894 * @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array 1895 * specified in @DRM_XE_OA_PROPERTY_SYNCS 1896 */ 1897 DRM_XE_OA_PROPERTY_NUM_SYNCS, 1898 1899 /** 1900 * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to struct @drm_xe_sync array 1901 * with array size specified via @DRM_XE_OA_PROPERTY_NUM_SYNCS. OA 1902 * configuration will wait till input fences signal. Output fences 1903 * will signal after the new OA configuration takes effect. For 1904 * @DRM_XE_SYNC_TYPE_USER_FENCE, @addr is a user pointer, similar 1905 * to the VM bind case. 1906 */ 1907 DRM_XE_OA_PROPERTY_SYNCS, 1908 1909 /** 1910 * @DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE: Size of OA buffer to be 1911 * allocated by the driver in bytes. Supported sizes are powers of 1912 * 2 from 128 KiB to 128 MiB. When not specified, a 16 MiB OA 1913 * buffer is allocated by default. 1914 */ 1915 DRM_XE_OA_PROPERTY_OA_BUFFER_SIZE, 1916 1917 /** 1918 * @DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS: Number of reports to wait 1919 * for before unblocking poll or read 1920 */ 1921 DRM_XE_OA_PROPERTY_WAIT_NUM_REPORTS, 1922 }; 1923 1924 /** 1925 * struct drm_xe_oa_config - OA metric configuration 1926 * 1927 * Multiple OA configs can be added using @DRM_XE_OBSERVATION_OP_ADD_CONFIG. A 1928 * particular config can be specified when opening an OA stream using 1929 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET property. 1930 */ 1931 struct drm_xe_oa_config { 1932 /** @extensions: Pointer to the first extension struct, if any */ 1933 __u64 extensions; 1934 1935 /** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */ 1936 char uuid[36]; 1937 1938 /** @n_regs: Number of regs in @regs_ptr */ 1939 __u32 n_regs; 1940 1941 /** 1942 * @regs_ptr: Pointer to (register address, value) pairs for OA config 1943 * registers. Expected length of buffer is: (2 * sizeof(u32) * @n_regs). 1944 */ 1945 __u64 regs_ptr; 1946 }; 1947 1948 /** 1949 * struct drm_xe_oa_stream_status - OA stream status returned from 1950 * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can 1951 * call the ioctl to query stream status in response to EIO errno from 1952 * observation fd read(). 1953 */ 1954 struct drm_xe_oa_stream_status { 1955 /** @extensions: Pointer to the first extension struct, if any */ 1956 __u64 extensions; 1957 1958 /** @oa_status: OA stream status (see Bspec 46717/61226) */ 1959 __u64 oa_status; 1960 #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3) 1961 #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2) 1962 #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1) 1963 #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0) 1964 1965 /** @reserved: reserved for future use */ 1966 __u64 reserved[3]; 1967 }; 1968 1969 /** 1970 * struct drm_xe_oa_stream_info - OA stream info returned from 1971 * @DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl 1972 */ 1973 struct drm_xe_oa_stream_info { 1974 /** @extensions: Pointer to the first extension struct, if any */ 1975 __u64 extensions; 1976 1977 /** @oa_buf_size: OA buffer size */ 1978 __u64 oa_buf_size; 1979 1980 /** @reserved: reserved for future use */ 1981 __u64 reserved[3]; 1982 }; 1983 1984 /** 1985 * enum drm_xe_pxp_session_type - Supported PXP session types. 1986 * 1987 * We currently only support HWDRM sessions, which are used for protected 1988 * content that ends up being displayed, but the HW supports multiple types, so 1989 * we might extend support in the future. 1990 */ 1991 enum drm_xe_pxp_session_type { 1992 /** @DRM_XE_PXP_TYPE_NONE: PXP not used */ 1993 DRM_XE_PXP_TYPE_NONE = 0, 1994 /** 1995 * @DRM_XE_PXP_TYPE_HWDRM: HWDRM sessions are used for content that ends 1996 * up on the display. 1997 */ 1998 DRM_XE_PXP_TYPE_HWDRM = 1, 1999 }; 2000 2001 /* ID of the protected content session managed by Xe when PXP is active */ 2002 #define DRM_XE_PXP_HWDRM_DEFAULT_SESSION 0xf 2003 2004 /** 2005 * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids. 2006 * 2007 * These properties are passed to the driver at open as a chain of 2008 * @drm_xe_ext_set_property structures with @property set to these 2009 * properties' enums and @value set to the corresponding values of these 2010 * properties. @drm_xe_user_extension base.name should be set to 2011 * @DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY. 2012 * 2013 * With the file descriptor obtained from open, user space must enable 2014 * the EU stall stream fd with @DRM_XE_OBSERVATION_IOCTL_ENABLE before 2015 * calling read(). EIO errno from read() indicates HW dropped data 2016 * due to full buffer. 2017 */ 2018 enum drm_xe_eu_stall_property_id { 2019 #define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY 0 2020 /** 2021 * @DRM_XE_EU_STALL_PROP_GT_ID: @gt_id of the GT on which 2022 * EU stall data will be captured. 2023 */ 2024 DRM_XE_EU_STALL_PROP_GT_ID = 1, 2025 2026 /** 2027 * @DRM_XE_EU_STALL_PROP_SAMPLE_RATE: Sampling rate in 2028 * GPU cycles from @sampling_rates in struct @drm_xe_query_eu_stall 2029 */ 2030 DRM_XE_EU_STALL_PROP_SAMPLE_RATE, 2031 2032 /** 2033 * @DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS: Minimum number of 2034 * EU stall data reports to be present in the kernel buffer 2035 * before unblocking a blocked poll or read. 2036 */ 2037 DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS, 2038 }; 2039 2040 /** 2041 * struct drm_xe_query_eu_stall - Information about EU stall sampling. 2042 * 2043 * If a query is made with a struct @drm_xe_device_query where .query 2044 * is equal to @DRM_XE_DEVICE_QUERY_EU_STALL, then the reply uses 2045 * struct @drm_xe_query_eu_stall in .data. 2046 */ 2047 struct drm_xe_query_eu_stall { 2048 /** @extensions: Pointer to the first extension struct, if any */ 2049 __u64 extensions; 2050 2051 /** @capabilities: EU stall capabilities bit-mask */ 2052 __u64 capabilities; 2053 #define DRM_XE_EU_STALL_CAPS_BASE (1 << 0) 2054 2055 /** @record_size: size of each EU stall data record */ 2056 __u64 record_size; 2057 2058 /** @per_xecore_buf_size: internal per XeCore buffer size */ 2059 __u64 per_xecore_buf_size; 2060 2061 /** @reserved: Reserved */ 2062 __u64 reserved[5]; 2063 2064 /** @num_sampling_rates: Number of sampling rates in @sampling_rates array */ 2065 __u64 num_sampling_rates; 2066 2067 /** 2068 * @sampling_rates: Flexible array of sampling rates 2069 * sorted in the fastest to slowest order. 2070 * Sampling rates are specified in GPU clock cycles. 2071 */ 2072 __u64 sampling_rates[]; 2073 }; 2074 2075 /** 2076 * struct drm_xe_madvise - Input of &DRM_IOCTL_XE_MADVISE 2077 * 2078 * This structure is used to set memory attributes for a virtual address range 2079 * in a VM. The type of attribute is specified by @type, and the corresponding 2080 * union member is used to provide additional parameters for @type. 2081 * 2082 * Supported attribute types: 2083 * - DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC: Set preferred memory location. 2084 * - DRM_XE_MEM_RANGE_ATTR_ATOMIC: Set atomic access policy. 2085 * - DRM_XE_MEM_RANGE_ATTR_PAT: Set page attribute table index. 2086 * 2087 * Example: 2088 * 2089 * .. code-block:: C 2090 * 2091 * struct drm_xe_madvise madvise = { 2092 * .vm_id = vm_id, 2093 * .start = 0x100000, 2094 * .range = 0x2000, 2095 * .type = DRM_XE_MEM_RANGE_ATTR_ATOMIC, 2096 * .atomic_val = DRM_XE_ATOMIC_DEVICE, 2097 * }; 2098 * 2099 * ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise); 2100 * 2101 */ 2102 struct drm_xe_madvise { 2103 /** @extensions: Pointer to the first extension struct, if any */ 2104 __u64 extensions; 2105 2106 /** @start: start of the virtual address range */ 2107 __u64 start; 2108 2109 /** @range: size of the virtual address range */ 2110 __u64 range; 2111 2112 /** @vm_id: vm_id of the virtual range */ 2113 __u32 vm_id; 2114 2115 #define DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 0 2116 #define DRM_XE_MEM_RANGE_ATTR_ATOMIC 1 2117 #define DRM_XE_MEM_RANGE_ATTR_PAT 2 2118 /** @type: type of attribute */ 2119 __u32 type; 2120 2121 union { 2122 /** 2123 * @preferred_mem_loc: preferred memory location 2124 * 2125 * Used when @type == DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 2126 * 2127 * Supported values for @preferred_mem_loc.devmem_fd: 2128 * - DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE: set vram of fault tile as preferred loc 2129 * - DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM: set smem as preferred loc 2130 * 2131 * Supported values for @preferred_mem_loc.migration_policy: 2132 * - DRM_XE_MIGRATE_ALL_PAGES 2133 * - DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 2134 */ 2135 struct { 2136 #define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE 0 2137 #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM -1 2138 /** 2139 * @preferred_mem_loc.devmem_fd: 2140 * Device file-descriptor of the device where the 2141 * preferred memory is located, or one of the 2142 * above special values. Please also see 2143 * @preferred_mem_loc.region_instance below. 2144 */ 2145 __u32 devmem_fd; 2146 2147 #define DRM_XE_MIGRATE_ALL_PAGES 0 2148 #define DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 1 2149 /** @preferred_mem_loc.migration_policy: Page migration policy */ 2150 __u16 migration_policy; 2151 2152 /** 2153 * @preferred_mem_loc.region_instance : Region instance. 2154 * MBZ if @devmem_fd <= &DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE. 2155 * Otherwise should point to the desired device 2156 * VRAM instance of the device indicated by 2157 * @preferred_mem_loc.devmem_fd. 2158 */ 2159 __u16 region_instance; 2160 2161 /** @preferred_mem_loc.reserved : Reserved */ 2162 __u64 reserved; 2163 } preferred_mem_loc; 2164 2165 /** 2166 * @atomic: Atomic access policy 2167 * 2168 * Used when @type == DRM_XE_MEM_RANGE_ATTR_ATOMIC. 2169 * 2170 * Supported values for @atomic.val: 2171 * - DRM_XE_ATOMIC_UNDEFINED: Undefined or default behaviour. 2172 * Support both GPU and CPU atomic operations for system allocator. 2173 * Support GPU atomic operations for normal(bo) allocator. 2174 * - DRM_XE_ATOMIC_DEVICE: Support GPU atomic operations. 2175 * - DRM_XE_ATOMIC_GLOBAL: Support both GPU and CPU atomic operations. 2176 * - DRM_XE_ATOMIC_CPU: Support CPU atomic only, no GPU atomics supported. 2177 */ 2178 struct { 2179 #define DRM_XE_ATOMIC_UNDEFINED 0 2180 #define DRM_XE_ATOMIC_DEVICE 1 2181 #define DRM_XE_ATOMIC_GLOBAL 2 2182 #define DRM_XE_ATOMIC_CPU 3 2183 /** @atomic.val: value of atomic operation */ 2184 __u32 val; 2185 2186 /** @atomic.pad: MBZ */ 2187 __u32 pad; 2188 2189 /** @atomic.reserved: Reserved */ 2190 __u64 reserved; 2191 } atomic; 2192 2193 /** 2194 * @pat_index: Page attribute table index 2195 * 2196 * Used when @type == DRM_XE_MEM_RANGE_ATTR_PAT. 2197 */ 2198 struct { 2199 /** @pat_index.val: PAT index value */ 2200 __u32 val; 2201 2202 /** @pat_index.pad: MBZ */ 2203 __u32 pad; 2204 2205 /** @pat_index.reserved: Reserved */ 2206 __u64 reserved; 2207 } pat_index; 2208 }; 2209 2210 /** @reserved: Reserved */ 2211 __u64 reserved[2]; 2212 }; 2213 2214 /** 2215 * struct drm_xe_mem_range_attr - Output of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS 2216 * 2217 * This structure is provided by userspace and filled by KMD in response to the 2218 * DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS ioctl. It describes memory attributes of 2219 * a memory ranges within a user specified address range in a VM. 2220 * 2221 * The structure includes information such as atomic access policy, 2222 * page attribute table (PAT) index, and preferred memory location. 2223 * Userspace allocates an array of these structures and passes a pointer to the 2224 * ioctl to retrieve attributes for each memory ranges 2225 * 2226 * @extensions: Pointer to the first extension struct, if any 2227 * @start: Start address of the memory range 2228 * @end: End address of the virtual memory range 2229 * 2230 */ 2231 struct drm_xe_mem_range_attr { 2232 /** @extensions: Pointer to the first extension struct, if any */ 2233 __u64 extensions; 2234 2235 /** @start: start of the memory range */ 2236 __u64 start; 2237 2238 /** @end: end of the memory range */ 2239 __u64 end; 2240 2241 /** @preferred_mem_loc: preferred memory location */ 2242 struct { 2243 /** @preferred_mem_loc.devmem_fd: fd for preferred loc */ 2244 __u32 devmem_fd; 2245 2246 /** @preferred_mem_loc.migration_policy: Page migration policy */ 2247 __u32 migration_policy; 2248 } preferred_mem_loc; 2249 2250 /** @atomic: Atomic access policy */ 2251 struct { 2252 /** @atomic.val: atomic attribute */ 2253 __u32 val; 2254 2255 /** @atomic.reserved: Reserved */ 2256 __u32 reserved; 2257 } atomic; 2258 2259 /** @pat_index: Page attribute table index */ 2260 struct { 2261 /** @pat_index.val: PAT index */ 2262 __u32 val; 2263 2264 /** @pat_index.reserved: Reserved */ 2265 __u32 reserved; 2266 } pat_index; 2267 2268 /** @reserved: Reserved */ 2269 __u64 reserved[2]; 2270 }; 2271 2272 /** 2273 * struct drm_xe_vm_query_mem_range_attr - Input of &DRM_IOCTL_XE_VM_QUERY_MEM_ATTRIBUTES 2274 * 2275 * This structure is used to query memory attributes of memory regions 2276 * within a user specified address range in a VM. It provides detailed 2277 * information about each memory range, including atomic access policy, 2278 * page attribute table (PAT) index, and preferred memory location. 2279 * 2280 * Userspace first calls the ioctl with @num_mem_ranges = 0, 2281 * @sizeof_mem_ranges_attr = 0 and @vector_of_vma_mem_attr = NULL to retrieve 2282 * the number of memory regions and size of each memory range attribute. 2283 * Then, it allocates a buffer of that size and calls the ioctl again to fill 2284 * the buffer with memory range attributes. 2285 * 2286 * If second call fails with -ENOSPC, it means memory ranges changed between 2287 * first call and now, retry IOCTL again with @num_mem_ranges = 0, 2288 * @sizeof_mem_ranges_attr = 0 and @vector_of_vma_mem_attr = NULL followed by 2289 * Second ioctl call. 2290 * 2291 * Example: 2292 * 2293 * .. code-block:: C 2294 * 2295 * struct drm_xe_vm_query_mem_range_attr query = { 2296 * .vm_id = vm_id, 2297 * .start = 0x100000, 2298 * .range = 0x2000, 2299 * }; 2300 * 2301 * // First ioctl call to get num of mem regions and sizeof each attribute 2302 * ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query); 2303 * 2304 * // Allocate buffer for the memory region attributes 2305 * void *ptr = malloc(query.num_mem_ranges * query.sizeof_mem_range_attr); 2306 * void *ptr_start = ptr; 2307 * 2308 * query.vector_of_mem_attr = (uintptr_t)ptr; 2309 * 2310 * // Second ioctl call to actually fill the memory attributes 2311 * ioctl(fd, DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS, &query); 2312 * 2313 * // Iterate over the returned memory region attributes 2314 * for (unsigned int i = 0; i < query.num_mem_ranges; ++i) { 2315 * struct drm_xe_mem_range_attr *attr = (struct drm_xe_mem_range_attr *)ptr; 2316 * 2317 * // Do something with attr 2318 * 2319 * // Move pointer by one entry 2320 * ptr += query.sizeof_mem_range_attr; 2321 * } 2322 * 2323 * free(ptr_start); 2324 */ 2325 struct drm_xe_vm_query_mem_range_attr { 2326 /** @extensions: Pointer to the first extension struct, if any */ 2327 __u64 extensions; 2328 2329 /** @vm_id: vm_id of the virtual range */ 2330 __u32 vm_id; 2331 2332 /** @num_mem_ranges: number of mem_ranges in range */ 2333 __u32 num_mem_ranges; 2334 2335 /** @start: start of the virtual address range */ 2336 __u64 start; 2337 2338 /** @range: size of the virtual address range */ 2339 __u64 range; 2340 2341 /** @sizeof_mem_range_attr: size of struct drm_xe_mem_range_attr */ 2342 __u64 sizeof_mem_range_attr; 2343 2344 /** @vector_of_mem_attr: userptr to array of struct drm_xe_mem_range_attr */ 2345 __u64 vector_of_mem_attr; 2346 2347 /** @reserved: Reserved */ 2348 __u64 reserved[2]; 2349 2350 }; 2351 2352 /** 2353 * struct drm_xe_exec_queue_set_property - exec queue set property 2354 * 2355 * Sets execution queue properties dynamically. 2356 * Currently only %DRM_XE_EXEC_QUEUE_SET_PROPERTY_MULTI_QUEUE_PRIORITY 2357 * property can be dynamically set. 2358 */ 2359 struct drm_xe_exec_queue_set_property { 2360 /** @extensions: Pointer to the first extension struct, if any */ 2361 __u64 extensions; 2362 2363 /** @exec_queue_id: Exec queue ID */ 2364 __u32 exec_queue_id; 2365 2366 /** @property: property to set */ 2367 __u32 property; 2368 2369 /** @value: property value */ 2370 __u64 value; 2371 2372 /** @reserved: Reserved */ 2373 __u64 reserved[2]; 2374 }; 2375 2376 /** 2377 * DOC: Xe DRM RAS 2378 * 2379 * The enums and strings defined below map to the attributes of the DRM RAS Netlink Interface. 2380 * Refer to Documentation/netlink/specs/drm_ras.yaml for complete interface specification. 2381 * 2382 * Node Registration 2383 * ================= 2384 * 2385 * The driver registers DRM RAS nodes for each error severity level. 2386 * enum drm_xe_ras_error_severity defines the node-id, while DRM_XE_RAS_ERROR_SEVERITY_NAMES maps 2387 * node-id to node-name. 2388 * 2389 * Error Classification 2390 * ==================== 2391 * 2392 * Each node contains a list of error counters. Each error is identified by a error-id and 2393 * an error-name. enum drm_xe_ras_error_component defines the error-id, while 2394 * DRM_XE_RAS_ERROR_COMPONENT_NAMES maps error-id to error-name. 2395 * 2396 * User Interface 2397 * ============== 2398 * 2399 * To retrieve error values of a error counter, userspace applications should 2400 * follow the below steps: 2401 * 2402 * 1. Use command LIST_NODES to enumerate all available nodes 2403 * 2. Select node by node-id or node-name 2404 * 3. Use command GET_ERROR_COUNTERS to list errors of specific node 2405 * 4. Query specific error values using either error-id or error-name 2406 * 2407 * .. code-block:: C 2408 * 2409 * // Lookup tables for ID-to-name resolution 2410 * static const char *nodes[] = DRM_XE_RAS_ERROR_SEVERITY_NAMES; 2411 * static const char *errors[] = DRM_XE_RAS_ERROR_COMPONENT_NAMES; 2412 * 2413 */ 2414 2415 /** 2416 * enum drm_xe_ras_error_severity - DRM RAS error severity. 2417 */ 2418 enum drm_xe_ras_error_severity { 2419 /** @DRM_XE_RAS_ERR_SEV_CORRECTABLE: Correctable Error */ 2420 DRM_XE_RAS_ERR_SEV_CORRECTABLE = 0, 2421 /** @DRM_XE_RAS_ERR_SEV_UNCORRECTABLE: Uncorrectable Error */ 2422 DRM_XE_RAS_ERR_SEV_UNCORRECTABLE, 2423 /** @DRM_XE_RAS_ERR_SEV_MAX: Max severity */ 2424 DRM_XE_RAS_ERR_SEV_MAX /* non-ABI */ 2425 }; 2426 2427 /** 2428 * enum drm_xe_ras_error_component - DRM RAS error component. 2429 */ 2430 enum drm_xe_ras_error_component { 2431 /** @DRM_XE_RAS_ERR_COMP_CORE_COMPUTE: Core Compute Error */ 2432 DRM_XE_RAS_ERR_COMP_CORE_COMPUTE = 1, 2433 /** @DRM_XE_RAS_ERR_COMP_SOC_INTERNAL: SoC Internal Error */ 2434 DRM_XE_RAS_ERR_COMP_SOC_INTERNAL, 2435 /** @DRM_XE_RAS_ERR_COMP_MAX: Max Error */ 2436 DRM_XE_RAS_ERR_COMP_MAX /* non-ABI */ 2437 }; 2438 2439 /* 2440 * Error severity to name mapping. 2441 */ 2442 #define DRM_XE_RAS_ERROR_SEVERITY_NAMES { \ 2443 [DRM_XE_RAS_ERR_SEV_CORRECTABLE] = "correctable-errors", \ 2444 [DRM_XE_RAS_ERR_SEV_UNCORRECTABLE] = "uncorrectable-errors", \ 2445 } 2446 2447 /* 2448 * Error component to name mapping. 2449 */ 2450 #define DRM_XE_RAS_ERROR_COMPONENT_NAMES { \ 2451 [DRM_XE_RAS_ERR_COMP_CORE_COMPUTE] = "core-compute", \ 2452 [DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal" \ 2453 } 2454 2455 #if defined(__cplusplus) 2456 } 2457 #endif 2458 2459 #endif /* _UAPI_XE_DRM_H_ */ 2460