1 /************************************************************************** 2 * 3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #ifndef __VMWGFX_DRM_H__ 29 #define __VMWGFX_DRM_H__ 30 31 #define DRM_VMW_MAX_SURFACE_FACES 6 32 #define DRM_VMW_MAX_MIP_LEVELS 24 33 34 35 #define DRM_VMW_GET_PARAM 0 36 #define DRM_VMW_ALLOC_DMABUF 1 37 #define DRM_VMW_UNREF_DMABUF 2 38 #define DRM_VMW_CURSOR_BYPASS 3 39 /* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/ 40 #define DRM_VMW_CONTROL_STREAM 4 41 #define DRM_VMW_CLAIM_STREAM 5 42 #define DRM_VMW_UNREF_STREAM 6 43 /* guarded by DRM_VMW_PARAM_3D == 1 */ 44 #define DRM_VMW_CREATE_CONTEXT 7 45 #define DRM_VMW_UNREF_CONTEXT 8 46 #define DRM_VMW_CREATE_SURFACE 9 47 #define DRM_VMW_UNREF_SURFACE 10 48 #define DRM_VMW_REF_SURFACE 11 49 #define DRM_VMW_EXECBUF 12 50 #define DRM_VMW_GET_3D_CAP 13 51 #define DRM_VMW_FENCE_WAIT 14 52 #define DRM_VMW_FENCE_SIGNALED 15 53 #define DRM_VMW_FENCE_UNREF 16 54 #define DRM_VMW_FENCE_EVENT 17 55 #define DRM_VMW_PRESENT 18 56 #define DRM_VMW_PRESENT_READBACK 19 57 #define DRM_VMW_UPDATE_LAYOUT 20 58 59 /*************************************************************************/ 60 /** 61 * DRM_VMW_GET_PARAM - get device information. 62 * 63 * DRM_VMW_PARAM_FIFO_OFFSET: 64 * Offset to use to map the first page of the FIFO read-only. 65 * The fifo is mapped using the mmap() system call on the drm device. 66 * 67 * DRM_VMW_PARAM_OVERLAY_IOCTL: 68 * Does the driver support the overlay ioctl. 69 */ 70 71 #define DRM_VMW_PARAM_NUM_STREAMS 0 72 #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 73 #define DRM_VMW_PARAM_3D 2 74 #define DRM_VMW_PARAM_HW_CAPS 3 75 #define DRM_VMW_PARAM_FIFO_CAPS 4 76 #define DRM_VMW_PARAM_MAX_FB_SIZE 5 77 #define DRM_VMW_PARAM_FIFO_HW_VERSION 6 78 #define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 79 80 /** 81 * struct drm_vmw_getparam_arg 82 * 83 * @value: Returned value. //Out 84 * @param: Parameter to query. //In. 85 * 86 * Argument to the DRM_VMW_GET_PARAM Ioctl. 87 */ 88 89 struct drm_vmw_getparam_arg { 90 uint64_t value; 91 uint32_t param; 92 uint32_t pad64; 93 }; 94 95 /*************************************************************************/ 96 /** 97 * DRM_VMW_CREATE_CONTEXT - Create a host context. 98 * 99 * Allocates a device unique context id, and queues a create context command 100 * for the host. Does not wait for host completion. 101 */ 102 103 /** 104 * struct drm_vmw_context_arg 105 * 106 * @cid: Device unique context ID. 107 * 108 * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. 109 * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. 110 */ 111 112 struct drm_vmw_context_arg { 113 int32_t cid; 114 uint32_t pad64; 115 }; 116 117 /*************************************************************************/ 118 /** 119 * DRM_VMW_UNREF_CONTEXT - Create a host context. 120 * 121 * Frees a global context id, and queues a destroy host command for the host. 122 * Does not wait for host completion. The context ID can be used directly 123 * in the command stream and shows up as the same context ID on the host. 124 */ 125 126 /*************************************************************************/ 127 /** 128 * DRM_VMW_CREATE_SURFACE - Create a host suface. 129 * 130 * Allocates a device unique surface id, and queues a create surface command 131 * for the host. Does not wait for host completion. The surface ID can be 132 * used directly in the command stream and shows up as the same surface 133 * ID on the host. 134 */ 135 136 /** 137 * struct drm_wmv_surface_create_req 138 * 139 * @flags: Surface flags as understood by the host. 140 * @format: Surface format as understood by the host. 141 * @mip_levels: Number of mip levels for each face. 142 * An unused face should have 0 encoded. 143 * @size_addr: Address of a user-space array of sruct drm_vmw_size 144 * cast to an uint64_t for 32-64 bit compatibility. 145 * The size of the array should equal the total number of mipmap levels. 146 * @shareable: Boolean whether other clients (as identified by file descriptors) 147 * may reference this surface. 148 * @scanout: Boolean whether the surface is intended to be used as a 149 * scanout. 150 * 151 * Input data to the DRM_VMW_CREATE_SURFACE Ioctl. 152 * Output data from the DRM_VMW_REF_SURFACE Ioctl. 153 */ 154 155 struct drm_vmw_surface_create_req { 156 uint32_t flags; 157 uint32_t format; 158 uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES]; 159 uint64_t size_addr; 160 int32_t shareable; 161 int32_t scanout; 162 }; 163 164 /** 165 * struct drm_wmv_surface_arg 166 * 167 * @sid: Surface id of created surface or surface to destroy or reference. 168 * 169 * Output data from the DRM_VMW_CREATE_SURFACE Ioctl. 170 * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl. 171 * Input argument to the DRM_VMW_REF_SURFACE Ioctl. 172 */ 173 174 struct drm_vmw_surface_arg { 175 int32_t sid; 176 uint32_t pad64; 177 }; 178 179 /** 180 * struct drm_vmw_size ioctl. 181 * 182 * @width - mip level width 183 * @height - mip level height 184 * @depth - mip level depth 185 * 186 * Description of a mip level. 187 * Input data to the DRM_WMW_CREATE_SURFACE Ioctl. 188 */ 189 190 struct drm_vmw_size { 191 uint32_t width; 192 uint32_t height; 193 uint32_t depth; 194 uint32_t pad64; 195 }; 196 197 /** 198 * union drm_vmw_surface_create_arg 199 * 200 * @rep: Output data as described above. 201 * @req: Input data as described above. 202 * 203 * Argument to the DRM_VMW_CREATE_SURFACE Ioctl. 204 */ 205 206 union drm_vmw_surface_create_arg { 207 struct drm_vmw_surface_arg rep; 208 struct drm_vmw_surface_create_req req; 209 }; 210 211 /*************************************************************************/ 212 /** 213 * DRM_VMW_REF_SURFACE - Reference a host surface. 214 * 215 * Puts a reference on a host surface with a give sid, as previously 216 * returned by the DRM_VMW_CREATE_SURFACE ioctl. 217 * A reference will make sure the surface isn't destroyed while we hold 218 * it and will allow the calling client to use the surface ID in the command 219 * stream. 220 * 221 * On successful return, the Ioctl returns the surface information given 222 * in the DRM_VMW_CREATE_SURFACE ioctl. 223 */ 224 225 /** 226 * union drm_vmw_surface_reference_arg 227 * 228 * @rep: Output data as described above. 229 * @req: Input data as described above. 230 * 231 * Argument to the DRM_VMW_REF_SURFACE Ioctl. 232 */ 233 234 union drm_vmw_surface_reference_arg { 235 struct drm_vmw_surface_create_req rep; 236 struct drm_vmw_surface_arg req; 237 }; 238 239 /*************************************************************************/ 240 /** 241 * DRM_VMW_UNREF_SURFACE - Unreference a host surface. 242 * 243 * Clear a reference previously put on a host surface. 244 * When all references are gone, including the one implicitly placed 245 * on creation, 246 * a destroy surface command will be queued for the host. 247 * Does not wait for completion. 248 */ 249 250 /*************************************************************************/ 251 /** 252 * DRM_VMW_EXECBUF 253 * 254 * Submit a command buffer for execution on the host, and return a 255 * fence seqno that when signaled, indicates that the command buffer has 256 * executed. 257 */ 258 259 /** 260 * struct drm_vmw_execbuf_arg 261 * 262 * @commands: User-space address of a command buffer cast to an uint64_t. 263 * @command-size: Size in bytes of the command buffer. 264 * @throttle-us: Sleep until software is less than @throttle_us 265 * microseconds ahead of hardware. The driver may round this value 266 * to the nearest kernel tick. 267 * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an 268 * uint64_t. 269 * @version: Allows expanding the execbuf ioctl parameters without breaking 270 * backwards compatibility, since user-space will always tell the kernel 271 * which version it uses. 272 * @flags: Execbuf flags. None currently. 273 * 274 * Argument to the DRM_VMW_EXECBUF Ioctl. 275 */ 276 277 #define DRM_VMW_EXECBUF_VERSION 1 278 279 struct drm_vmw_execbuf_arg { 280 uint64_t commands; 281 uint32_t command_size; 282 uint32_t throttle_us; 283 uint64_t fence_rep; 284 uint32_t version; 285 uint32_t flags; 286 }; 287 288 /** 289 * struct drm_vmw_fence_rep 290 * 291 * @handle: Fence object handle for fence associated with a command submission. 292 * @mask: Fence flags relevant for this fence object. 293 * @seqno: Fence sequence number in fifo. A fence object with a lower 294 * seqno will signal the EXEC flag before a fence object with a higher 295 * seqno. This can be used by user-space to avoid kernel calls to determine 296 * whether a fence has signaled the EXEC flag. Note that @seqno will 297 * wrap at 32-bit. 298 * @passed_seqno: The highest seqno number processed by the hardware 299 * so far. This can be used to mark user-space fence objects as signaled, and 300 * to determine whether a fence seqno might be stale. 301 * @error: This member should've been set to -EFAULT on submission. 302 * The following actions should be take on completion: 303 * error == -EFAULT: Fence communication failed. The host is synchronized. 304 * Use the last fence id read from the FIFO fence register. 305 * error != 0 && error != -EFAULT: 306 * Fence submission failed. The host is synchronized. Use the fence_seq member. 307 * error == 0: All is OK, The host may not be synchronized. 308 * Use the fence_seq member. 309 * 310 * Input / Output data to the DRM_VMW_EXECBUF Ioctl. 311 */ 312 313 struct drm_vmw_fence_rep { 314 uint32_t handle; 315 uint32_t mask; 316 uint32_t seqno; 317 uint32_t passed_seqno; 318 uint32_t pad64; 319 int32_t error; 320 }; 321 322 /*************************************************************************/ 323 /** 324 * DRM_VMW_ALLOC_DMABUF 325 * 326 * Allocate a DMA buffer that is visible also to the host. 327 * NOTE: The buffer is 328 * identified by a handle and an offset, which are private to the guest, but 329 * useable in the command stream. The guest kernel may translate these 330 * and patch up the command stream accordingly. In the future, the offset may 331 * be zero at all times, or it may disappear from the interface before it is 332 * fixed. 333 * 334 * The DMA buffer may stay user-space mapped in the guest at all times, 335 * and is thus suitable for sub-allocation. 336 * 337 * DMA buffers are mapped using the mmap() syscall on the drm device. 338 */ 339 340 /** 341 * struct drm_vmw_alloc_dmabuf_req 342 * 343 * @size: Required minimum size of the buffer. 344 * 345 * Input data to the DRM_VMW_ALLOC_DMABUF Ioctl. 346 */ 347 348 struct drm_vmw_alloc_dmabuf_req { 349 uint32_t size; 350 uint32_t pad64; 351 }; 352 353 /** 354 * struct drm_vmw_dmabuf_rep 355 * 356 * @map_handle: Offset to use in the mmap() call used to map the buffer. 357 * @handle: Handle unique to this buffer. Used for unreferencing. 358 * @cur_gmr_id: GMR id to use in the command stream when this buffer is 359 * referenced. See not above. 360 * @cur_gmr_offset: Offset to use in the command stream when this buffer is 361 * referenced. See note above. 362 * 363 * Output data from the DRM_VMW_ALLOC_DMABUF Ioctl. 364 */ 365 366 struct drm_vmw_dmabuf_rep { 367 uint64_t map_handle; 368 uint32_t handle; 369 uint32_t cur_gmr_id; 370 uint32_t cur_gmr_offset; 371 uint32_t pad64; 372 }; 373 374 /** 375 * union drm_vmw_dmabuf_arg 376 * 377 * @req: Input data as described above. 378 * @rep: Output data as described above. 379 * 380 * Argument to the DRM_VMW_ALLOC_DMABUF Ioctl. 381 */ 382 383 union drm_vmw_alloc_dmabuf_arg { 384 struct drm_vmw_alloc_dmabuf_req req; 385 struct drm_vmw_dmabuf_rep rep; 386 }; 387 388 /*************************************************************************/ 389 /** 390 * DRM_VMW_UNREF_DMABUF - Free a DMA buffer. 391 * 392 */ 393 394 /** 395 * struct drm_vmw_unref_dmabuf_arg 396 * 397 * @handle: Handle indicating what buffer to free. Obtained from the 398 * DRM_VMW_ALLOC_DMABUF Ioctl. 399 * 400 * Argument to the DRM_VMW_UNREF_DMABUF Ioctl. 401 */ 402 403 struct drm_vmw_unref_dmabuf_arg { 404 uint32_t handle; 405 uint32_t pad64; 406 }; 407 408 /*************************************************************************/ 409 /** 410 * DRM_VMW_CONTROL_STREAM - Control overlays, aka streams. 411 * 412 * This IOCTL controls the overlay units of the svga device. 413 * The SVGA overlay units does not work like regular hardware units in 414 * that they do not automaticaly read back the contents of the given dma 415 * buffer. But instead only read back for each call to this ioctl, and 416 * at any point between this call being made and a following call that 417 * either changes the buffer or disables the stream. 418 */ 419 420 /** 421 * struct drm_vmw_rect 422 * 423 * Defines a rectangle. Used in the overlay ioctl to define 424 * source and destination rectangle. 425 */ 426 427 struct drm_vmw_rect { 428 int32_t x; 429 int32_t y; 430 uint32_t w; 431 uint32_t h; 432 }; 433 434 /** 435 * struct drm_vmw_control_stream_arg 436 * 437 * @stream_id: Stearm to control 438 * @enabled: If false all following arguments are ignored. 439 * @handle: Handle to buffer for getting data from. 440 * @format: Format of the overlay as understood by the host. 441 * @width: Width of the overlay. 442 * @height: Height of the overlay. 443 * @size: Size of the overlay in bytes. 444 * @pitch: Array of pitches, the two last are only used for YUV12 formats. 445 * @offset: Offset from start of dma buffer to overlay. 446 * @src: Source rect, must be within the defined area above. 447 * @dst: Destination rect, x and y may be negative. 448 * 449 * Argument to the DRM_VMW_CONTROL_STREAM Ioctl. 450 */ 451 452 struct drm_vmw_control_stream_arg { 453 uint32_t stream_id; 454 uint32_t enabled; 455 456 uint32_t flags; 457 uint32_t color_key; 458 459 uint32_t handle; 460 uint32_t offset; 461 int32_t format; 462 uint32_t size; 463 uint32_t width; 464 uint32_t height; 465 uint32_t pitch[3]; 466 467 uint32_t pad64; 468 struct drm_vmw_rect src; 469 struct drm_vmw_rect dst; 470 }; 471 472 /*************************************************************************/ 473 /** 474 * DRM_VMW_CURSOR_BYPASS - Give extra information about cursor bypass. 475 * 476 */ 477 478 #define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) 479 #define DRM_VMW_CURSOR_BYPASS_FLAGS (1) 480 481 /** 482 * struct drm_vmw_cursor_bypass_arg 483 * 484 * @flags: Flags. 485 * @crtc_id: Crtc id, only used if DMR_CURSOR_BYPASS_ALL isn't passed. 486 * @xpos: X position of cursor. 487 * @ypos: Y position of cursor. 488 * @xhot: X hotspot. 489 * @yhot: Y hotspot. 490 * 491 * Argument to the DRM_VMW_CURSOR_BYPASS Ioctl. 492 */ 493 494 struct drm_vmw_cursor_bypass_arg { 495 uint32_t flags; 496 uint32_t crtc_id; 497 int32_t xpos; 498 int32_t ypos; 499 int32_t xhot; 500 int32_t yhot; 501 }; 502 503 /*************************************************************************/ 504 /** 505 * DRM_VMW_CLAIM_STREAM - Claim a single stream. 506 */ 507 508 /** 509 * struct drm_vmw_context_arg 510 * 511 * @stream_id: Device unique context ID. 512 * 513 * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. 514 * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. 515 */ 516 517 struct drm_vmw_stream_arg { 518 uint32_t stream_id; 519 uint32_t pad64; 520 }; 521 522 /*************************************************************************/ 523 /** 524 * DRM_VMW_UNREF_STREAM - Unclaim a stream. 525 * 526 * Return a single stream that was claimed by this process. Also makes 527 * sure that the stream has been stopped. 528 */ 529 530 /*************************************************************************/ 531 /** 532 * DRM_VMW_GET_3D_CAP 533 * 534 * Read 3D capabilities from the FIFO 535 * 536 */ 537 538 /** 539 * struct drm_vmw_get_3d_cap_arg 540 * 541 * @buffer: Pointer to a buffer for capability data, cast to an uint64_t 542 * @size: Max size to copy 543 * 544 * Input argument to the DRM_VMW_GET_3D_CAP_IOCTL 545 * ioctls. 546 */ 547 548 struct drm_vmw_get_3d_cap_arg { 549 uint64_t buffer; 550 uint32_t max_size; 551 uint32_t pad64; 552 }; 553 554 /*************************************************************************/ 555 /** 556 * DRM_VMW_FENCE_WAIT 557 * 558 * Waits for a fence object to signal. The wait is interruptible, so that 559 * signals may be delivered during the interrupt. The wait may timeout, 560 * in which case the calls returns -EBUSY. If the wait is restarted, 561 * that is restarting without resetting @cookie_valid to zero, 562 * the timeout is computed from the first call. 563 * 564 * The flags argument to the DRM_VMW_FENCE_WAIT ioctl indicates what to wait 565 * on: 566 * DRM_VMW_FENCE_FLAG_EXEC: All commands ahead of the fence in the command 567 * stream 568 * have executed. 569 * DRM_VMW_FENCE_FLAG_QUERY: All query results resulting from query finish 570 * commands 571 * in the buffer given to the EXECBUF ioctl returning the fence object handle 572 * are available to user-space. 573 * 574 * DRM_VMW_WAIT_OPTION_UNREF: If this wait option is given, and the 575 * fenc wait ioctl returns 0, the fence object has been unreferenced after 576 * the wait. 577 */ 578 579 #define DRM_VMW_FENCE_FLAG_EXEC (1 << 0) 580 #define DRM_VMW_FENCE_FLAG_QUERY (1 << 1) 581 582 #define DRM_VMW_WAIT_OPTION_UNREF (1 << 0) 583 584 /** 585 * struct drm_vmw_fence_wait_arg 586 * 587 * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. 588 * @cookie_valid: Must be reset to 0 on first call. Left alone on restart. 589 * @kernel_cookie: Set to 0 on first call. Left alone on restart. 590 * @timeout_us: Wait timeout in microseconds. 0 for indefinite timeout. 591 * @lazy: Set to 1 if timing is not critical. Allow more than a kernel tick 592 * before returning. 593 * @flags: Fence flags to wait on. 594 * @wait_options: Options that control the behaviour of the wait ioctl. 595 * 596 * Input argument to the DRM_VMW_FENCE_WAIT ioctl. 597 */ 598 599 struct drm_vmw_fence_wait_arg { 600 uint32_t handle; 601 int32_t cookie_valid; 602 uint64_t kernel_cookie; 603 uint64_t timeout_us; 604 int32_t lazy; 605 int32_t flags; 606 int32_t wait_options; 607 int32_t pad64; 608 }; 609 610 /*************************************************************************/ 611 /** 612 * DRM_VMW_FENCE_SIGNALED 613 * 614 * Checks if a fence object is signaled.. 615 */ 616 617 /** 618 * struct drm_vmw_fence_signaled_arg 619 * 620 * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. 621 * @flags: Fence object flags input to DRM_VMW_FENCE_SIGNALED ioctl 622 * @signaled: Out: Flags signaled. 623 * @sequence: Out: Highest sequence passed so far. Can be used to signal the 624 * EXEC flag of user-space fence objects. 625 * 626 * Input/Output argument to the DRM_VMW_FENCE_SIGNALED and DRM_VMW_FENCE_UNREF 627 * ioctls. 628 */ 629 630 struct drm_vmw_fence_signaled_arg { 631 uint32_t handle; 632 uint32_t flags; 633 int32_t signaled; 634 uint32_t passed_seqno; 635 uint32_t signaled_flags; 636 uint32_t pad64; 637 }; 638 639 /*************************************************************************/ 640 /** 641 * DRM_VMW_FENCE_UNREF 642 * 643 * Unreferences a fence object, and causes it to be destroyed if there are no 644 * other references to it. 645 * 646 */ 647 648 /** 649 * struct drm_vmw_fence_arg 650 * 651 * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl. 652 * 653 * Input/Output argument to the DRM_VMW_FENCE_UNREF ioctl.. 654 */ 655 656 struct drm_vmw_fence_arg { 657 uint32_t handle; 658 uint32_t pad64; 659 }; 660 661 662 /*************************************************************************/ 663 /** 664 * DRM_VMW_FENCE_EVENT 665 * 666 * Queues an event on a fence to be delivered on the drm character device 667 * when the fence has signaled the DRM_VMW_FENCE_FLAG_EXEC flag. 668 * Optionally the approximate time when the fence signaled is 669 * given by the event. 670 */ 671 672 /* 673 * The event type 674 */ 675 #define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000 676 677 struct drm_vmw_event_fence { 678 struct drm_event base; 679 uint64_t user_data; 680 uint32_t tv_sec; 681 uint32_t tv_usec; 682 }; 683 684 /* 685 * Flags that may be given to the command. 686 */ 687 /* Request fence signaled time on the event. */ 688 #define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0) 689 690 /** 691 * struct drm_vmw_fence_event_arg 692 * 693 * @fence_rep: Pointer to fence_rep structure cast to uint64_t or 0 if 694 * the fence is not supposed to be referenced by user-space. 695 * @user_info: Info to be delivered with the event. 696 * @handle: Attach the event to this fence only. 697 * @flags: A set of flags as defined above. 698 */ 699 struct drm_vmw_fence_event_arg { 700 uint64_t fence_rep; 701 uint64_t user_data; 702 uint32_t handle; 703 uint32_t flags; 704 }; 705 706 707 /*************************************************************************/ 708 /** 709 * DRM_VMW_PRESENT 710 * 711 * Executes an SVGA present on a given fb for a given surface. The surface 712 * is placed on the framebuffer. Cliprects are given relative to the given 713 * point (the point disignated by dest_{x|y}). 714 * 715 */ 716 717 /** 718 * struct drm_vmw_present_arg 719 * @fb_id: framebuffer id to present / read back from. 720 * @sid: Surface id to present from. 721 * @dest_x: X placement coordinate for surface. 722 * @dest_y: Y placement coordinate for surface. 723 * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t. 724 * @num_clips: Number of cliprects given relative to the framebuffer origin, 725 * in the same coordinate space as the frame buffer. 726 * @pad64: Unused 64-bit padding. 727 * 728 * Input argument to the DRM_VMW_PRESENT ioctl. 729 */ 730 731 struct drm_vmw_present_arg { 732 uint32_t fb_id; 733 uint32_t sid; 734 int32_t dest_x; 735 int32_t dest_y; 736 uint64_t clips_ptr; 737 uint32_t num_clips; 738 uint32_t pad64; 739 }; 740 741 742 /*************************************************************************/ 743 /** 744 * DRM_VMW_PRESENT_READBACK 745 * 746 * Executes an SVGA present readback from a given fb to the dma buffer 747 * currently bound as the fb. If there is no dma buffer bound to the fb, 748 * an error will be returned. 749 * 750 */ 751 752 /** 753 * struct drm_vmw_present_arg 754 * @fb_id: fb_id to present / read back from. 755 * @num_clips: Number of cliprects. 756 * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t. 757 * @fence_rep: Pointer to a struct drm_vmw_fence_rep, cast to an uint64_t. 758 * If this member is NULL, then the ioctl should not return a fence. 759 */ 760 761 struct drm_vmw_present_readback_arg { 762 uint32_t fb_id; 763 uint32_t num_clips; 764 uint64_t clips_ptr; 765 uint64_t fence_rep; 766 }; 767 768 /*************************************************************************/ 769 /** 770 * DRM_VMW_UPDATE_LAYOUT - Update layout 771 * 772 * Updates the preferred modes and connection status for connectors. The 773 * command consists of one drm_vmw_update_layout_arg pointing to an array 774 * of num_outputs drm_vmw_rect's. 775 */ 776 777 /** 778 * struct drm_vmw_update_layout_arg 779 * 780 * @num_outputs: number of active connectors 781 * @rects: pointer to array of drm_vmw_rect cast to an uint64_t 782 * 783 * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl. 784 */ 785 struct drm_vmw_update_layout_arg { 786 uint32_t num_outputs; 787 uint32_t pad64; 788 uint64_t rects; 789 }; 790 791 #endif 792