1 /* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __NOUVEAU_DRM_H__ 26 #define __NOUVEAU_DRM_H__ 27 28 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000 29 30 #include "drm.h" 31 32 #if defined(__cplusplus) 33 extern "C" { 34 #endif 35 36 #define NOUVEAU_GETPARAM_PCI_VENDOR 3 37 #define NOUVEAU_GETPARAM_PCI_DEVICE 4 38 #define NOUVEAU_GETPARAM_BUS_TYPE 5 39 #define NOUVEAU_GETPARAM_FB_SIZE 8 40 #define NOUVEAU_GETPARAM_AGP_SIZE 9 41 #define NOUVEAU_GETPARAM_CHIPSET_ID 11 42 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 43 #define NOUVEAU_GETPARAM_GRAPH_UNITS 13 44 #define NOUVEAU_GETPARAM_PTIMER_TIME 14 45 #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 46 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 47 48 /* 49 * NOUVEAU_GETPARAM_EXEC_PUSH_MAX - query max pushes through getparam 50 * 51 * Query the maximum amount of IBs that can be pushed through a single 52 * &drm_nouveau_exec structure and hence a single &DRM_IOCTL_NOUVEAU_EXEC 53 * ioctl(). 54 */ 55 #define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17 56 57 /* 58 * NOUVEAU_GETPARAM_VRAM_BAR_SIZE - query bar size 59 * 60 * Query the VRAM BAR size. 61 */ 62 #define NOUVEAU_GETPARAM_VRAM_BAR_SIZE 18 63 64 /* 65 * NOUVEAU_GETPARAM_VRAM_USED 66 * 67 * Get remaining VRAM size. 68 */ 69 #define NOUVEAU_GETPARAM_VRAM_USED 19 70 71 struct drm_nouveau_getparam { 72 __u64 param; 73 __u64 value; 74 }; 75 76 /* 77 * Those are used to support selecting the main engine used on Kepler. 78 * This goes into drm_nouveau_channel_alloc::tt_ctxdma_handle 79 */ 80 #define NOUVEAU_FIFO_ENGINE_GR 0x01 81 #define NOUVEAU_FIFO_ENGINE_VP 0x02 82 #define NOUVEAU_FIFO_ENGINE_PPP 0x04 83 #define NOUVEAU_FIFO_ENGINE_BSP 0x08 84 #define NOUVEAU_FIFO_ENGINE_CE 0x30 85 86 struct drm_nouveau_channel_alloc { 87 __u32 fb_ctxdma_handle; 88 __u32 tt_ctxdma_handle; 89 90 __s32 channel; 91 __u32 pushbuf_domains; 92 93 /* Notifier memory */ 94 __u32 notifier_handle; 95 96 /* DRM-enforced subchannel assignments */ 97 struct { 98 __u32 handle; 99 __u32 grclass; 100 } subchan[8]; 101 __u32 nr_subchan; 102 }; 103 104 struct drm_nouveau_channel_free { 105 __s32 channel; 106 }; 107 108 struct drm_nouveau_notifierobj_alloc { 109 __u32 channel; 110 __u32 handle; 111 __u32 size; 112 __u32 offset; 113 }; 114 115 struct drm_nouveau_gpuobj_free { 116 __s32 channel; 117 __u32 handle; 118 }; 119 120 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 121 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 122 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 123 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) 124 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) 125 /* The BO will never be shared via import or export. */ 126 #define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5) 127 128 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ 129 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 130 #define NOUVEAU_GEM_TILE_16BPP 0x00000001 131 #define NOUVEAU_GEM_TILE_32BPP 0x00000002 132 #define NOUVEAU_GEM_TILE_ZETA 0x00000004 133 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 134 135 struct drm_nouveau_gem_info { 136 __u32 handle; 137 __u32 domain; 138 __u64 size; 139 __u64 offset; 140 __u64 map_handle; 141 __u32 tile_mode; 142 __u32 tile_flags; 143 }; 144 145 struct drm_nouveau_gem_new { 146 struct drm_nouveau_gem_info info; 147 __u32 channel_hint; 148 __u32 align; 149 }; 150 151 #define NOUVEAU_GEM_MAX_BUFFERS 1024 152 struct drm_nouveau_gem_pushbuf_bo_presumed { 153 __u32 valid; 154 __u32 domain; 155 __u64 offset; 156 }; 157 158 struct drm_nouveau_gem_pushbuf_bo { 159 __u64 user_priv; 160 __u32 handle; 161 __u32 read_domains; 162 __u32 write_domains; 163 __u32 valid_domains; 164 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 165 }; 166 167 #define NOUVEAU_GEM_RELOC_LOW (1 << 0) 168 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 169 #define NOUVEAU_GEM_RELOC_OR (1 << 2) 170 #define NOUVEAU_GEM_MAX_RELOCS 1024 171 struct drm_nouveau_gem_pushbuf_reloc { 172 __u32 reloc_bo_index; 173 __u32 reloc_bo_offset; 174 __u32 bo_index; 175 __u32 flags; 176 __u32 data; 177 __u32 vor; 178 __u32 tor; 179 }; 180 181 #define NOUVEAU_GEM_MAX_PUSH 512 182 struct drm_nouveau_gem_pushbuf_push { 183 __u32 bo_index; 184 __u32 pad; 185 __u64 offset; 186 __u64 length; 187 #define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23) 188 }; 189 190 struct drm_nouveau_gem_pushbuf { 191 __u32 channel; 192 __u32 nr_buffers; 193 __u64 buffers; 194 __u32 nr_relocs; 195 __u32 nr_push; 196 __u64 relocs; 197 __u64 push; 198 __u32 suffix0; 199 __u32 suffix1; 200 #define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0) 201 __u64 vram_available; 202 __u64 gart_available; 203 }; 204 205 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 206 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 207 struct drm_nouveau_gem_cpu_prep { 208 __u32 handle; 209 __u32 flags; 210 }; 211 212 struct drm_nouveau_gem_cpu_fini { 213 __u32 handle; 214 }; 215 216 /** 217 * struct drm_nouveau_sync - sync object 218 * 219 * This structure serves as synchronization mechanism for (potentially) 220 * asynchronous operations such as EXEC or VM_BIND. 221 */ 222 struct drm_nouveau_sync { 223 /** 224 * @flags: the flags for a sync object 225 * 226 * The first 8 bits are used to determine the type of the sync object. 227 */ 228 __u32 flags; 229 #define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0 230 #define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1 231 #define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf 232 /** 233 * @handle: the handle of the sync object 234 */ 235 __u32 handle; 236 /** 237 * @timeline_value: 238 * 239 * The timeline point of the sync object in case the syncobj is of 240 * type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ. 241 */ 242 __u64 timeline_value; 243 }; 244 245 /** 246 * struct drm_nouveau_vm_init - GPU VA space init structure 247 * 248 * Used to initialize the GPU's VA space for a user client, telling the kernel 249 * which portion of the VA space is managed by the UMD and kernel respectively. 250 * 251 * For the UMD to use the VM_BIND uAPI, this must be called before any BOs or 252 * channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails 253 * with -ENOSYS. 254 */ 255 struct drm_nouveau_vm_init { 256 /** 257 * @kernel_managed_addr: start address of the kernel managed VA space 258 * region 259 */ 260 __u64 kernel_managed_addr; 261 /** 262 * @kernel_managed_size: size of the kernel managed VA space region in 263 * bytes 264 */ 265 __u64 kernel_managed_size; 266 }; 267 268 /** 269 * struct drm_nouveau_vm_bind_op - VM_BIND operation 270 * 271 * This structure represents a single VM_BIND operation. UMDs should pass 272 * an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field. 273 */ 274 struct drm_nouveau_vm_bind_op { 275 /** 276 * @op: the operation type 277 * 278 * Supported values: 279 * 280 * %DRM_NOUVEAU_VM_BIND_OP_MAP - Map a GEM object to the GPU's VA 281 * space. Optionally, the &DRM_NOUVEAU_VM_BIND_SPARSE flag can be 282 * passed to instruct the kernel to create sparse mappings for the 283 * given range. 284 * 285 * %DRM_NOUVEAU_VM_BIND_OP_UNMAP - Unmap an existing mapping in the 286 * GPU's VA space. If the region the mapping is located in is a 287 * sparse region, new sparse mappings are created where the unmapped 288 * (memory backed) mapping was mapped previously. To remove a sparse 289 * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set. 290 */ 291 __u32 op; 292 #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0 293 #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1 294 /** 295 * @flags: the flags for a &drm_nouveau_vm_bind_op 296 * 297 * Supported values: 298 * 299 * %DRM_NOUVEAU_VM_BIND_SPARSE - Indicates that an allocated VA 300 * space region should be sparse. 301 */ 302 __u32 flags; 303 #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8) 304 /** 305 * @handle: the handle of the DRM GEM object to map 306 */ 307 __u32 handle; 308 /** 309 * @pad: 32 bit padding, should be 0 310 */ 311 __u32 pad; 312 /** 313 * @addr: 314 * 315 * the address the VA space region or (memory backed) mapping should be mapped to 316 */ 317 __u64 addr; 318 /** 319 * @bo_offset: the offset within the BO backing the mapping 320 */ 321 __u64 bo_offset; 322 /** 323 * @range: the size of the requested mapping in bytes 324 */ 325 __u64 range; 326 }; 327 328 /** 329 * struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND 330 */ 331 struct drm_nouveau_vm_bind { 332 /** 333 * @op_count: the number of &drm_nouveau_vm_bind_op 334 */ 335 __u32 op_count; 336 /** 337 * @flags: the flags for a &drm_nouveau_vm_bind ioctl 338 * 339 * Supported values: 340 * 341 * %DRM_NOUVEAU_VM_BIND_RUN_ASYNC - Indicates that the given VM_BIND 342 * operation should be executed asynchronously by the kernel. 343 * 344 * If this flag is not supplied the kernel executes the associated 345 * operations synchronously and doesn't accept any &drm_nouveau_sync 346 * objects. 347 */ 348 __u32 flags; 349 #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1 350 /** 351 * @wait_count: the number of wait &drm_nouveau_syncs 352 */ 353 __u32 wait_count; 354 /** 355 * @sig_count: the number of &drm_nouveau_syncs to signal when finished 356 */ 357 __u32 sig_count; 358 /** 359 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for 360 */ 361 __u64 wait_ptr; 362 /** 363 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished 364 */ 365 __u64 sig_ptr; 366 /** 367 * @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute 368 */ 369 __u64 op_ptr; 370 }; 371 372 /** 373 * struct drm_nouveau_exec_push - EXEC push operation 374 * 375 * This structure represents a single EXEC push operation. UMDs should pass an 376 * array of this structure via struct drm_nouveau_exec's &push_ptr field. 377 */ 378 struct drm_nouveau_exec_push { 379 /** 380 * @va: the virtual address of the push buffer mapping 381 */ 382 __u64 va; 383 /** 384 * @va_len: the length of the push buffer mapping 385 */ 386 __u32 va_len; 387 /** 388 * @flags: the flags for this push buffer mapping 389 */ 390 __u32 flags; 391 #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1 392 }; 393 394 /** 395 * struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC 396 */ 397 struct drm_nouveau_exec { 398 /** 399 * @channel: the channel to execute the push buffer in 400 */ 401 __u32 channel; 402 /** 403 * @push_count: the number of &drm_nouveau_exec_push ops 404 */ 405 __u32 push_count; 406 /** 407 * @wait_count: the number of wait &drm_nouveau_syncs 408 */ 409 __u32 wait_count; 410 /** 411 * @sig_count: the number of &drm_nouveau_syncs to signal when finished 412 */ 413 __u32 sig_count; 414 /** 415 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for 416 */ 417 __u64 wait_ptr; 418 /** 419 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished 420 */ 421 __u64 sig_ptr; 422 /** 423 * @push_ptr: pointer to &drm_nouveau_exec_push ops 424 */ 425 __u64 push_ptr; 426 }; 427 428 #define DRM_NOUVEAU_GETPARAM 0x00 429 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */ 430 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 431 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 432 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */ 433 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */ 434 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */ 435 #define DRM_NOUVEAU_NVIF 0x07 436 #define DRM_NOUVEAU_SVM_INIT 0x08 437 #define DRM_NOUVEAU_SVM_BIND 0x09 438 #define DRM_NOUVEAU_VM_INIT 0x10 439 #define DRM_NOUVEAU_VM_BIND 0x11 440 #define DRM_NOUVEAU_EXEC 0x12 441 #define DRM_NOUVEAU_GEM_NEW 0x40 442 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 443 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 444 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 445 #define DRM_NOUVEAU_GEM_INFO 0x44 446 447 struct drm_nouveau_svm_init { 448 __u64 unmanaged_addr; 449 __u64 unmanaged_size; 450 }; 451 452 struct drm_nouveau_svm_bind { 453 __u64 header; 454 __u64 va_start; 455 __u64 va_end; 456 __u64 npages; 457 __u64 stride; 458 __u64 result; 459 __u64 reserved0; 460 __u64 reserved1; 461 }; 462 463 #define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0 464 #define NOUVEAU_SVM_BIND_COMMAND_BITS 8 465 #define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1) 466 #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8 467 #define NOUVEAU_SVM_BIND_PRIORITY_BITS 8 468 #define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1) 469 #define NOUVEAU_SVM_BIND_TARGET_SHIFT 16 470 #define NOUVEAU_SVM_BIND_TARGET_BITS 32 471 #define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff 472 473 /* 474 * Below is use to validate ioctl argument, userspace can also use it to make 475 * sure that no bit are set beyond known fields for a given kernel version. 476 */ 477 #define NOUVEAU_SVM_BIND_VALID_BITS 48 478 #define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1) 479 480 481 /* 482 * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory. 483 * result: number of page successfuly migrate to the target memory. 484 */ 485 #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0 486 487 /* 488 * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory. 489 */ 490 #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31) 491 492 493 #define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam) 494 #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc) 495 #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free) 496 497 #define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init) 498 #define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind) 499 500 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 501 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) 502 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) 503 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) 504 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) 505 506 #define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init) 507 #define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind) 508 #define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec) 509 #if defined(__cplusplus) 510 } 511 #endif 512 513 #endif /* __NOUVEAU_DRM_H__ */ 514