1 /* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __NOUVEAU_DRM_H__ 26 #define __NOUVEAU_DRM_H__ 27 28 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000 29 30 #include "drm.h" 31 32 #if defined(__cplusplus) 33 extern "C" { 34 #endif 35 36 #define NOUVEAU_GETPARAM_PCI_VENDOR 3 37 #define NOUVEAU_GETPARAM_PCI_DEVICE 4 38 #define NOUVEAU_GETPARAM_BUS_TYPE 5 39 #define NOUVEAU_GETPARAM_FB_SIZE 8 40 #define NOUVEAU_GETPARAM_AGP_SIZE 9 41 #define NOUVEAU_GETPARAM_CHIPSET_ID 11 42 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 43 #define NOUVEAU_GETPARAM_GRAPH_UNITS 13 44 #define NOUVEAU_GETPARAM_PTIMER_TIME 14 45 #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 46 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 47 48 /* 49 * NOUVEAU_GETPARAM_EXEC_PUSH_MAX - query max pushes through getparam 50 * 51 * Query the maximum amount of IBs that can be pushed through a single 52 * &drm_nouveau_exec structure and hence a single &DRM_IOCTL_NOUVEAU_EXEC 53 * ioctl(). 54 */ 55 #define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17 56 57 /* 58 * NOUVEAU_GETPARAM_VRAM_BAR_SIZE - query bar size 59 * 60 * Query the VRAM BAR size. 61 */ 62 #define NOUVEAU_GETPARAM_VRAM_BAR_SIZE 18 63 64 /* 65 * NOUVEAU_GETPARAM_VRAM_USED 66 * 67 * Get remaining VRAM size. 68 */ 69 #define NOUVEAU_GETPARAM_VRAM_USED 19 70 71 /* 72 * NOUVEAU_GETPARAM_HAS_VMA_TILEMODE 73 * 74 * Query whether tile mode and PTE kind are accepted with VM allocs or not. 75 */ 76 #define NOUVEAU_GETPARAM_HAS_VMA_TILEMODE 20 77 78 struct drm_nouveau_getparam { 79 __u64 param; 80 __u64 value; 81 }; 82 83 /* 84 * Those are used to support selecting the main engine used on Kepler. 85 * This goes into drm_nouveau_channel_alloc::tt_ctxdma_handle 86 */ 87 #define NOUVEAU_FIFO_ENGINE_GR 0x01 88 #define NOUVEAU_FIFO_ENGINE_VP 0x02 89 #define NOUVEAU_FIFO_ENGINE_PPP 0x04 90 #define NOUVEAU_FIFO_ENGINE_BSP 0x08 91 #define NOUVEAU_FIFO_ENGINE_CE 0x30 92 #define NOUVEAU_FIFO_ENGINE_NVDEC 0x300 93 94 struct drm_nouveau_channel_alloc { 95 __u32 fb_ctxdma_handle; 96 __u32 tt_ctxdma_handle; 97 98 __s32 channel; 99 __u32 pushbuf_domains; 100 101 /* Notifier memory */ 102 __u32 notifier_handle; 103 104 /* DRM-enforced subchannel assignments */ 105 struct { 106 __u32 handle; 107 __u32 grclass; 108 } subchan[8]; 109 __u32 nr_subchan; 110 }; 111 112 struct drm_nouveau_channel_free { 113 __s32 channel; 114 }; 115 116 struct drm_nouveau_notifierobj_alloc { 117 __u32 channel; 118 __u32 handle; 119 __u32 size; 120 __u32 offset; 121 }; 122 123 struct drm_nouveau_gpuobj_free { 124 __s32 channel; 125 __u32 handle; 126 }; 127 128 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 129 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 130 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 131 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) 132 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) 133 /* The BO will never be shared via import or export. */ 134 #define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5) 135 136 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ 137 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 138 #define NOUVEAU_GEM_TILE_16BPP 0x00000001 139 #define NOUVEAU_GEM_TILE_32BPP 0x00000002 140 #define NOUVEAU_GEM_TILE_ZETA 0x00000004 141 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 142 143 struct drm_nouveau_gem_info { 144 __u32 handle; 145 __u32 domain; 146 __u64 size; 147 __u64 offset; 148 __u64 map_handle; 149 __u32 tile_mode; 150 __u32 tile_flags; 151 }; 152 153 struct drm_nouveau_gem_new { 154 struct drm_nouveau_gem_info info; 155 __u32 channel_hint; 156 __u32 align; 157 }; 158 159 #define NOUVEAU_GEM_MAX_BUFFERS 1024 160 struct drm_nouveau_gem_pushbuf_bo_presumed { 161 __u32 valid; 162 __u32 domain; 163 __u64 offset; 164 }; 165 166 struct drm_nouveau_gem_pushbuf_bo { 167 __u64 user_priv; 168 __u32 handle; 169 __u32 read_domains; 170 __u32 write_domains; 171 __u32 valid_domains; 172 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 173 }; 174 175 #define NOUVEAU_GEM_RELOC_LOW (1 << 0) 176 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 177 #define NOUVEAU_GEM_RELOC_OR (1 << 2) 178 #define NOUVEAU_GEM_MAX_RELOCS 1024 179 struct drm_nouveau_gem_pushbuf_reloc { 180 __u32 reloc_bo_index; 181 __u32 reloc_bo_offset; 182 __u32 bo_index; 183 __u32 flags; 184 __u32 data; 185 __u32 vor; 186 __u32 tor; 187 }; 188 189 #define NOUVEAU_GEM_MAX_PUSH 512 190 struct drm_nouveau_gem_pushbuf_push { 191 __u32 bo_index; 192 __u32 pad; 193 __u64 offset; 194 __u64 length; 195 #define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23) 196 }; 197 198 struct drm_nouveau_gem_pushbuf { 199 __u32 channel; 200 __u32 nr_buffers; 201 __u64 buffers; 202 __u32 nr_relocs; 203 __u32 nr_push; 204 __u64 relocs; 205 __u64 push; 206 __u32 suffix0; 207 __u32 suffix1; 208 #define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0) 209 __u64 vram_available; 210 __u64 gart_available; 211 }; 212 213 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 214 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 215 struct drm_nouveau_gem_cpu_prep { 216 __u32 handle; 217 __u32 flags; 218 }; 219 220 struct drm_nouveau_gem_cpu_fini { 221 __u32 handle; 222 }; 223 224 /** 225 * struct drm_nouveau_sync - sync object 226 * 227 * This structure serves as synchronization mechanism for (potentially) 228 * asynchronous operations such as EXEC or VM_BIND. 229 */ 230 struct drm_nouveau_sync { 231 /** 232 * @flags: the flags for a sync object 233 * 234 * The first 8 bits are used to determine the type of the sync object. 235 */ 236 __u32 flags; 237 #define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0 238 #define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1 239 #define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf 240 /** 241 * @handle: the handle of the sync object 242 */ 243 __u32 handle; 244 /** 245 * @timeline_value: 246 * 247 * The timeline point of the sync object in case the syncobj is of 248 * type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ. 249 */ 250 __u64 timeline_value; 251 }; 252 253 /** 254 * struct drm_nouveau_vm_init - GPU VA space init structure 255 * 256 * Used to initialize the GPU's VA space for a user client, telling the kernel 257 * which portion of the VA space is managed by the UMD and kernel respectively. 258 * 259 * For the UMD to use the VM_BIND uAPI, this must be called before any BOs or 260 * channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails 261 * with -ENOSYS. 262 */ 263 struct drm_nouveau_vm_init { 264 /** 265 * @kernel_managed_addr: start address of the kernel managed VA space 266 * region 267 */ 268 __u64 kernel_managed_addr; 269 /** 270 * @kernel_managed_size: size of the kernel managed VA space region in 271 * bytes 272 */ 273 __u64 kernel_managed_size; 274 }; 275 276 /** 277 * struct drm_nouveau_vm_bind_op - VM_BIND operation 278 * 279 * This structure represents a single VM_BIND operation. UMDs should pass 280 * an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field. 281 */ 282 struct drm_nouveau_vm_bind_op { 283 /** 284 * @op: the operation type 285 * 286 * Supported values: 287 * 288 * %DRM_NOUVEAU_VM_BIND_OP_MAP - Map a GEM object to the GPU's VA 289 * space. Optionally, the &DRM_NOUVEAU_VM_BIND_SPARSE flag can be 290 * passed to instruct the kernel to create sparse mappings for the 291 * given range. 292 * 293 * %DRM_NOUVEAU_VM_BIND_OP_UNMAP - Unmap an existing mapping in the 294 * GPU's VA space. If the region the mapping is located in is a 295 * sparse region, new sparse mappings are created where the unmapped 296 * (memory backed) mapping was mapped previously. To remove a sparse 297 * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set. 298 */ 299 __u32 op; 300 #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0 301 #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1 302 /** 303 * @flags: the flags for a &drm_nouveau_vm_bind_op 304 * 305 * Supported values: 306 * 307 * %DRM_NOUVEAU_VM_BIND_SPARSE - Indicates that an allocated VA 308 * space region should be sparse. 309 */ 310 __u32 flags; 311 #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8) 312 /** 313 * @handle: the handle of the DRM GEM object to map 314 */ 315 __u32 handle; 316 /** 317 * @pad: 32 bit padding, should be 0 318 */ 319 __u32 pad; 320 /** 321 * @addr: 322 * 323 * the address the VA space region or (memory backed) mapping should be mapped to 324 */ 325 __u64 addr; 326 /** 327 * @bo_offset: the offset within the BO backing the mapping 328 */ 329 __u64 bo_offset; 330 /** 331 * @range: the size of the requested mapping in bytes 332 */ 333 __u64 range; 334 }; 335 336 /** 337 * struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND 338 */ 339 struct drm_nouveau_vm_bind { 340 /** 341 * @op_count: the number of &drm_nouveau_vm_bind_op 342 */ 343 __u32 op_count; 344 /** 345 * @flags: the flags for a &drm_nouveau_vm_bind ioctl 346 * 347 * Supported values: 348 * 349 * %DRM_NOUVEAU_VM_BIND_RUN_ASYNC - Indicates that the given VM_BIND 350 * operation should be executed asynchronously by the kernel. 351 * 352 * If this flag is not supplied the kernel executes the associated 353 * operations synchronously and doesn't accept any &drm_nouveau_sync 354 * objects. 355 */ 356 __u32 flags; 357 #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1 358 /** 359 * @wait_count: the number of wait &drm_nouveau_syncs 360 */ 361 __u32 wait_count; 362 /** 363 * @sig_count: the number of &drm_nouveau_syncs to signal when finished 364 */ 365 __u32 sig_count; 366 /** 367 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for 368 */ 369 __u64 wait_ptr; 370 /** 371 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished 372 */ 373 __u64 sig_ptr; 374 /** 375 * @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute 376 */ 377 __u64 op_ptr; 378 }; 379 380 /** 381 * struct drm_nouveau_exec_push - EXEC push operation 382 * 383 * This structure represents a single EXEC push operation. UMDs should pass an 384 * array of this structure via struct drm_nouveau_exec's &push_ptr field. 385 */ 386 struct drm_nouveau_exec_push { 387 /** 388 * @va: the virtual address of the push buffer mapping 389 */ 390 __u64 va; 391 /** 392 * @va_len: the length of the push buffer mapping 393 */ 394 __u32 va_len; 395 /** 396 * @flags: the flags for this push buffer mapping 397 */ 398 __u32 flags; 399 #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1 400 }; 401 402 /** 403 * struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC 404 */ 405 struct drm_nouveau_exec { 406 /** 407 * @channel: the channel to execute the push buffer in 408 */ 409 __u32 channel; 410 /** 411 * @push_count: the number of &drm_nouveau_exec_push ops 412 */ 413 __u32 push_count; 414 /** 415 * @wait_count: the number of wait &drm_nouveau_syncs 416 */ 417 __u32 wait_count; 418 /** 419 * @sig_count: the number of &drm_nouveau_syncs to signal when finished 420 */ 421 __u32 sig_count; 422 /** 423 * @wait_ptr: pointer to &drm_nouveau_syncs to wait for 424 */ 425 __u64 wait_ptr; 426 /** 427 * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished 428 */ 429 __u64 sig_ptr; 430 /** 431 * @push_ptr: pointer to &drm_nouveau_exec_push ops 432 */ 433 __u64 push_ptr; 434 }; 435 436 struct drm_nouveau_get_zcull_info { 437 /** 438 * @width_align_pixels: required alignment for region widths, in pixels 439 * (typically #TPC's * 16). 440 */ 441 __u32 width_align_pixels; 442 /** 443 * @height_align_pixels: required alignment for region heights, in 444 * pixels (typically 32). 445 */ 446 __u32 height_align_pixels; 447 /** 448 * @pixel_squares_by_aliquots: the pixel area covered by an aliquot 449 * (typically #Zcull_banks * 16 * 16). 450 */ 451 __u32 pixel_squares_by_aliquots; 452 /** 453 * @aliquot_total: the total aliquot pool available in hardware 454 */ 455 __u32 aliquot_total; 456 /** 457 * @zcull_region_byte_multiplier: the size of an aliquot in bytes, which 458 * is used for save/restore operations on a region 459 */ 460 __u32 zcull_region_byte_multiplier; 461 /** 462 * @zcull_region_header_size: the region header size in bytes, which is 463 * used for save/restore operations on a region 464 */ 465 __u32 zcull_region_header_size; 466 /** 467 * @zcull_subregion_header_size: the subregion header size in bytes, 468 * which is used for save/restore operations on a region 469 */ 470 __u32 zcull_subregion_header_size; 471 /** 472 * @subregion_count: the total number of subregions the hardware 473 * supports 474 */ 475 __u32 subregion_count; 476 /** 477 * @subregion_width_align_pixels: required alignment for subregion 478 * widths, in pixels (typically #TPC's * 16). 479 */ 480 __u32 subregion_width_align_pixels; 481 /** 482 * @subregion_height_align_pixels: required alignment for subregion 483 * heights, in pixels 484 */ 485 __u32 subregion_height_align_pixels; 486 487 /** 488 * @ctxsw_size: the size, in bytes, of a zcull context switching region. 489 * Will be zero if the kernel does not support zcull context switching. 490 */ 491 __u32 ctxsw_size; 492 /** 493 * @ctxsw_align: the alignment, in bytes, of a zcull context switching 494 * region 495 */ 496 __u32 ctxsw_align; 497 }; 498 499 #define DRM_NOUVEAU_GETPARAM 0x00 500 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */ 501 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 502 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 503 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */ 504 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */ 505 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */ 506 #define DRM_NOUVEAU_NVIF 0x07 507 #define DRM_NOUVEAU_SVM_INIT 0x08 508 #define DRM_NOUVEAU_SVM_BIND 0x09 509 #define DRM_NOUVEAU_VM_INIT 0x10 510 #define DRM_NOUVEAU_VM_BIND 0x11 511 #define DRM_NOUVEAU_EXEC 0x12 512 #define DRM_NOUVEAU_GET_ZCULL_INFO 0x13 513 #define DRM_NOUVEAU_GEM_NEW 0x40 514 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 515 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 516 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 517 #define DRM_NOUVEAU_GEM_INFO 0x44 518 519 struct drm_nouveau_svm_init { 520 __u64 unmanaged_addr; 521 __u64 unmanaged_size; 522 }; 523 524 struct drm_nouveau_svm_bind { 525 __u64 header; 526 __u64 va_start; 527 __u64 va_end; 528 __u64 npages; 529 __u64 stride; 530 __u64 result; 531 __u64 reserved0; 532 __u64 reserved1; 533 }; 534 535 #define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0 536 #define NOUVEAU_SVM_BIND_COMMAND_BITS 8 537 #define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1) 538 #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8 539 #define NOUVEAU_SVM_BIND_PRIORITY_BITS 8 540 #define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1) 541 #define NOUVEAU_SVM_BIND_TARGET_SHIFT 16 542 #define NOUVEAU_SVM_BIND_TARGET_BITS 32 543 #define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff 544 545 /* 546 * Below is use to validate ioctl argument, userspace can also use it to make 547 * sure that no bit are set beyond known fields for a given kernel version. 548 */ 549 #define NOUVEAU_SVM_BIND_VALID_BITS 48 550 #define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1) 551 552 553 /* 554 * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory. 555 * result: number of page successfuly migrate to the target memory. 556 */ 557 #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0 558 559 /* 560 * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory. 561 */ 562 #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31) 563 564 565 #define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam) 566 #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc) 567 #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free) 568 569 #define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init) 570 #define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind) 571 572 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 573 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) 574 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) 575 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) 576 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) 577 578 #define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init) 579 #define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind) 580 #define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec) 581 582 #define DRM_IOCTL_NOUVEAU_GET_ZCULL_INFO DRM_IOR (DRM_COMMAND_BASE + DRM_NOUVEAU_GET_ZCULL_INFO, struct drm_nouveau_get_zcull_info) 583 #if defined(__cplusplus) 584 } 585 #endif 586 587 #endif /* __NOUVEAU_DRM_H__ */ 588