1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _UAPI_I915_DRM_H_ 28 #define _UAPI_I915_DRM_H_ 29 30 #include <drm/drm.h> 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 37 /* Each region is a minimum of 16k, and there are at most 255 of them. 38 */ 39 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 40 * of chars for next/prev indices */ 41 #define I915_LOG_MIN_TEX_REGION_SIZE 14 42 43 typedef struct _drm_i915_init { 44 enum { 45 I915_INIT_DMA = 0x01, 46 I915_CLEANUP_DMA = 0x02, 47 I915_RESUME_DMA = 0x03 48 } func; 49 unsigned int mmio_offset; 50 int sarea_priv_offset; 51 unsigned int ring_start; 52 unsigned int ring_end; 53 unsigned int ring_size; 54 unsigned int front_offset; 55 unsigned int back_offset; 56 unsigned int depth_offset; 57 unsigned int w; 58 unsigned int h; 59 unsigned int pitch; 60 unsigned int pitch_bits; 61 unsigned int back_pitch; 62 unsigned int depth_pitch; 63 unsigned int cpp; 64 unsigned int chipset; 65 } drm_i915_init_t; 66 67 typedef struct _drm_i915_sarea { 68 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 69 int last_upload; /* last time texture was uploaded */ 70 int last_enqueue; /* last time a buffer was enqueued */ 71 int last_dispatch; /* age of the most recently dispatched buffer */ 72 int ctxOwner; /* last context to upload state */ 73 int texAge; 74 int pf_enabled; /* is pageflipping allowed? */ 75 int pf_active; 76 int pf_current_page; /* which buffer is being displayed? */ 77 int perf_boxes; /* performance boxes to be displayed */ 78 int width, height; /* screen size in pixels */ 79 80 drm_handle_t front_handle; 81 int front_offset; 82 int front_size; 83 84 drm_handle_t back_handle; 85 int back_offset; 86 int back_size; 87 88 drm_handle_t depth_handle; 89 int depth_offset; 90 int depth_size; 91 92 drm_handle_t tex_handle; 93 int tex_offset; 94 int tex_size; 95 int log_tex_granularity; 96 int pitch; 97 int rotation; /* 0, 90, 180 or 270 */ 98 int rotated_offset; 99 int rotated_size; 100 int rotated_pitch; 101 int virtualX, virtualY; 102 103 unsigned int front_tiled; 104 unsigned int back_tiled; 105 unsigned int depth_tiled; 106 unsigned int rotated_tiled; 107 unsigned int rotated2_tiled; 108 109 int pipeA_x; 110 int pipeA_y; 111 int pipeA_w; 112 int pipeA_h; 113 int pipeB_x; 114 int pipeB_y; 115 int pipeB_w; 116 int pipeB_h; 117 118 /* fill out some space for old userspace triple buffer */ 119 drm_handle_t unused_handle; 120 __u32 unused1, unused2, unused3; 121 122 /* buffer object handles for static buffers. May change 123 * over the lifetime of the client. 124 */ 125 __u32 front_bo_handle; 126 __u32 back_bo_handle; 127 __u32 unused_bo_handle; 128 __u32 depth_bo_handle; 129 130 } drm_i915_sarea_t; 131 132 /* due to userspace building against these headers we need some compat here */ 133 #define planeA_x pipeA_x 134 #define planeA_y pipeA_y 135 #define planeA_w pipeA_w 136 #define planeA_h pipeA_h 137 #define planeB_x pipeB_x 138 #define planeB_y pipeB_y 139 #define planeB_w pipeB_w 140 #define planeB_h pipeB_h 141 142 /* Flags for perf_boxes 143 */ 144 #define I915_BOX_RING_EMPTY 0x1 145 #define I915_BOX_FLIP 0x2 146 #define I915_BOX_WAIT 0x4 147 #define I915_BOX_TEXTURE_LOAD 0x8 148 #define I915_BOX_LOST_CONTEXT 0x10 149 150 /* I915 specific ioctls 151 * The device specific ioctl range is 0x40 to 0x79. 152 */ 153 #define DRM_I915_INIT 0x00 154 #define DRM_I915_FLUSH 0x01 155 #define DRM_I915_FLIP 0x02 156 #define DRM_I915_BATCHBUFFER 0x03 157 #define DRM_I915_IRQ_EMIT 0x04 158 #define DRM_I915_IRQ_WAIT 0x05 159 #define DRM_I915_GETPARAM 0x06 160 #define DRM_I915_SETPARAM 0x07 161 #define DRM_I915_ALLOC 0x08 162 #define DRM_I915_FREE 0x09 163 #define DRM_I915_INIT_HEAP 0x0a 164 #define DRM_I915_CMDBUFFER 0x0b 165 #define DRM_I915_DESTROY_HEAP 0x0c 166 #define DRM_I915_SET_VBLANK_PIPE 0x0d 167 #define DRM_I915_GET_VBLANK_PIPE 0x0e 168 #define DRM_I915_VBLANK_SWAP 0x0f 169 #define DRM_I915_HWS_ADDR 0x11 170 #define DRM_I915_GEM_INIT 0x13 171 #define DRM_I915_GEM_EXECBUFFER 0x14 172 #define DRM_I915_GEM_PIN 0x15 173 #define DRM_I915_GEM_UNPIN 0x16 174 #define DRM_I915_GEM_BUSY 0x17 175 #define DRM_I915_GEM_THROTTLE 0x18 176 #define DRM_I915_GEM_ENTERVT 0x19 177 #define DRM_I915_GEM_LEAVEVT 0x1a 178 #define DRM_I915_GEM_CREATE 0x1b 179 #define DRM_I915_GEM_PREAD 0x1c 180 #define DRM_I915_GEM_PWRITE 0x1d 181 #define DRM_I915_GEM_MMAP 0x1e 182 #define DRM_I915_GEM_SET_DOMAIN 0x1f 183 #define DRM_I915_GEM_SW_FINISH 0x20 184 #define DRM_I915_GEM_SET_TILING 0x21 185 #define DRM_I915_GEM_GET_TILING 0x22 186 #define DRM_I915_GEM_GET_APERTURE 0x23 187 #define DRM_I915_GEM_MMAP_GTT 0x24 188 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 189 #define DRM_I915_GEM_MADVISE 0x26 190 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 191 #define DRM_I915_OVERLAY_ATTRS 0x28 192 #define DRM_I915_GEM_EXECBUFFER2 0x29 193 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 194 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 195 #define DRM_I915_GEM_WAIT 0x2c 196 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 197 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 198 #define DRM_I915_GEM_SET_CACHING 0x2f 199 #define DRM_I915_GEM_GET_CACHING 0x30 200 #define DRM_I915_REG_READ 0x31 201 202 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 203 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 204 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 205 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 206 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 207 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 208 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 209 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 210 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 211 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 212 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 213 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 214 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 215 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 216 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 217 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 218 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 219 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 220 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 221 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 222 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 223 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 224 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 225 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 226 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 227 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 228 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 229 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 230 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 231 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 232 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 233 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 234 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 235 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 236 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 237 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 238 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 239 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 240 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 241 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 242 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 243 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 244 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 245 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 246 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 247 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 248 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 249 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 250 251 /* Allow drivers to submit batchbuffers directly to hardware, relying 252 * on the security mechanisms provided by hardware. 253 */ 254 typedef struct drm_i915_batchbuffer { 255 int start; /* agp offset */ 256 int used; /* nr bytes in use */ 257 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 258 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 259 int num_cliprects; /* mulitpass with multiple cliprects? */ 260 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 261 } drm_i915_batchbuffer_t; 262 263 /* As above, but pass a pointer to userspace buffer which can be 264 * validated by the kernel prior to sending to hardware. 265 */ 266 typedef struct _drm_i915_cmdbuffer { 267 char __user *buf; /* pointer to userspace command buffer */ 268 int sz; /* nr bytes in buf */ 269 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 270 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 271 int num_cliprects; /* mulitpass with multiple cliprects? */ 272 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 273 } drm_i915_cmdbuffer_t; 274 275 /* Userspace can request & wait on irq's: 276 */ 277 typedef struct drm_i915_irq_emit { 278 int __user *irq_seq; 279 } drm_i915_irq_emit_t; 280 281 typedef struct drm_i915_irq_wait { 282 int irq_seq; 283 } drm_i915_irq_wait_t; 284 285 /* Ioctl to query kernel params: 286 */ 287 #define I915_PARAM_IRQ_ACTIVE 1 288 #define I915_PARAM_ALLOW_BATCHBUFFER 2 289 #define I915_PARAM_LAST_DISPATCH 3 290 #define I915_PARAM_CHIPSET_ID 4 291 #define I915_PARAM_HAS_GEM 5 292 #define I915_PARAM_NUM_FENCES_AVAIL 6 293 #define I915_PARAM_HAS_OVERLAY 7 294 #define I915_PARAM_HAS_PAGEFLIPPING 8 295 #define I915_PARAM_HAS_EXECBUF2 9 296 #define I915_PARAM_HAS_BSD 10 297 #define I915_PARAM_HAS_BLT 11 298 #define I915_PARAM_HAS_RELAXED_FENCING 12 299 #define I915_PARAM_HAS_COHERENT_RINGS 13 300 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 301 #define I915_PARAM_HAS_RELAXED_DELTA 15 302 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 303 #define I915_PARAM_HAS_LLC 17 304 #define I915_PARAM_HAS_ALIASING_PPGTT 18 305 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 306 #define I915_PARAM_HAS_SEMAPHORES 20 307 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 308 #define I915_PARAM_RSVD_FOR_FUTURE_USE 22 309 310 typedef struct drm_i915_getparam { 311 int param; 312 int __user *value; 313 } drm_i915_getparam_t; 314 315 /* Ioctl to set kernel params: 316 */ 317 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 318 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 319 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 320 #define I915_SETPARAM_NUM_USED_FENCES 4 321 322 typedef struct drm_i915_setparam { 323 int param; 324 int value; 325 } drm_i915_setparam_t; 326 327 /* A memory manager for regions of shared memory: 328 */ 329 #define I915_MEM_REGION_AGP 1 330 331 typedef struct drm_i915_mem_alloc { 332 int region; 333 int alignment; 334 int size; 335 int __user *region_offset; /* offset from start of fb or agp */ 336 } drm_i915_mem_alloc_t; 337 338 typedef struct drm_i915_mem_free { 339 int region; 340 int region_offset; 341 } drm_i915_mem_free_t; 342 343 typedef struct drm_i915_mem_init_heap { 344 int region; 345 int size; 346 int start; 347 } drm_i915_mem_init_heap_t; 348 349 /* Allow memory manager to be torn down and re-initialized (eg on 350 * rotate): 351 */ 352 typedef struct drm_i915_mem_destroy_heap { 353 int region; 354 } drm_i915_mem_destroy_heap_t; 355 356 /* Allow X server to configure which pipes to monitor for vblank signals 357 */ 358 #define DRM_I915_VBLANK_PIPE_A 1 359 #define DRM_I915_VBLANK_PIPE_B 2 360 361 typedef struct drm_i915_vblank_pipe { 362 int pipe; 363 } drm_i915_vblank_pipe_t; 364 365 /* Schedule buffer swap at given vertical blank: 366 */ 367 typedef struct drm_i915_vblank_swap { 368 drm_drawable_t drawable; 369 enum drm_vblank_seq_type seqtype; 370 unsigned int sequence; 371 } drm_i915_vblank_swap_t; 372 373 typedef struct drm_i915_hws_addr { 374 __u64 addr; 375 } drm_i915_hws_addr_t; 376 377 struct drm_i915_gem_init { 378 /** 379 * Beginning offset in the GTT to be managed by the DRM memory 380 * manager. 381 */ 382 __u64 gtt_start; 383 /** 384 * Ending offset in the GTT to be managed by the DRM memory 385 * manager. 386 */ 387 __u64 gtt_end; 388 }; 389 390 struct drm_i915_gem_create { 391 /** 392 * Requested size for the object. 393 * 394 * The (page-aligned) allocated size for the object will be returned. 395 */ 396 __u64 size; 397 /** 398 * Returned handle for the object. 399 * 400 * Object handles are nonzero. 401 */ 402 __u32 handle; 403 __u32 pad; 404 }; 405 406 struct drm_i915_gem_pread { 407 /** Handle for the object being read. */ 408 __u32 handle; 409 __u32 pad; 410 /** Offset into the object to read from */ 411 __u64 offset; 412 /** Length of data to read */ 413 __u64 size; 414 /** 415 * Pointer to write the data into. 416 * 417 * This is a fixed-size type for 32/64 compatibility. 418 */ 419 __u64 data_ptr; 420 }; 421 422 struct drm_i915_gem_pwrite { 423 /** Handle for the object being written to. */ 424 __u32 handle; 425 __u32 pad; 426 /** Offset into the object to write to */ 427 __u64 offset; 428 /** Length of data to write */ 429 __u64 size; 430 /** 431 * Pointer to read the data from. 432 * 433 * This is a fixed-size type for 32/64 compatibility. 434 */ 435 __u64 data_ptr; 436 }; 437 438 struct drm_i915_gem_mmap { 439 /** Handle for the object being mapped. */ 440 __u32 handle; 441 __u32 pad; 442 /** Offset in the object to map. */ 443 __u64 offset; 444 /** 445 * Length of data to map. 446 * 447 * The value will be page-aligned. 448 */ 449 __u64 size; 450 /** 451 * Returned pointer the data was mapped at. 452 * 453 * This is a fixed-size type for 32/64 compatibility. 454 */ 455 __u64 addr_ptr; 456 }; 457 458 struct drm_i915_gem_mmap_gtt { 459 /** Handle for the object being mapped. */ 460 __u32 handle; 461 __u32 pad; 462 /** 463 * Fake offset to use for subsequent mmap call 464 * 465 * This is a fixed-size type for 32/64 compatibility. 466 */ 467 __u64 offset; 468 }; 469 470 struct drm_i915_gem_set_domain { 471 /** Handle for the object */ 472 __u32 handle; 473 474 /** New read domains */ 475 __u32 read_domains; 476 477 /** New write domain */ 478 __u32 write_domain; 479 }; 480 481 struct drm_i915_gem_sw_finish { 482 /** Handle for the object */ 483 __u32 handle; 484 }; 485 486 struct drm_i915_gem_relocation_entry { 487 /** 488 * Handle of the buffer being pointed to by this relocation entry. 489 * 490 * It's appealing to make this be an index into the mm_validate_entry 491 * list to refer to the buffer, but this allows the driver to create 492 * a relocation list for state buffers and not re-write it per 493 * exec using the buffer. 494 */ 495 __u32 target_handle; 496 497 /** 498 * Value to be added to the offset of the target buffer to make up 499 * the relocation entry. 500 */ 501 __u32 delta; 502 503 /** Offset in the buffer the relocation entry will be written into */ 504 __u64 offset; 505 506 /** 507 * Offset value of the target buffer that the relocation entry was last 508 * written as. 509 * 510 * If the buffer has the same offset as last time, we can skip syncing 511 * and writing the relocation. This value is written back out by 512 * the execbuffer ioctl when the relocation is written. 513 */ 514 __u64 presumed_offset; 515 516 /** 517 * Target memory domains read by this operation. 518 */ 519 __u32 read_domains; 520 521 /** 522 * Target memory domains written by this operation. 523 * 524 * Note that only one domain may be written by the whole 525 * execbuffer operation, so that where there are conflicts, 526 * the application will get -EINVAL back. 527 */ 528 __u32 write_domain; 529 }; 530 531 /** @{ 532 * Intel memory domains 533 * 534 * Most of these just align with the various caches in 535 * the system and are used to flush and invalidate as 536 * objects end up cached in different domains. 537 */ 538 /** CPU cache */ 539 #define I915_GEM_DOMAIN_CPU 0x00000001 540 /** Render cache, used by 2D and 3D drawing */ 541 #define I915_GEM_DOMAIN_RENDER 0x00000002 542 /** Sampler cache, used by texture engine */ 543 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 544 /** Command queue, used to load batch buffers */ 545 #define I915_GEM_DOMAIN_COMMAND 0x00000008 546 /** Instruction cache, used by shader programs */ 547 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 548 /** Vertex address cache */ 549 #define I915_GEM_DOMAIN_VERTEX 0x00000020 550 /** GTT domain - aperture and scanout */ 551 #define I915_GEM_DOMAIN_GTT 0x00000040 552 /** @} */ 553 554 struct drm_i915_gem_exec_object { 555 /** 556 * User's handle for a buffer to be bound into the GTT for this 557 * operation. 558 */ 559 __u32 handle; 560 561 /** Number of relocations to be performed on this buffer */ 562 __u32 relocation_count; 563 /** 564 * Pointer to array of struct drm_i915_gem_relocation_entry containing 565 * the relocations to be performed in this buffer. 566 */ 567 __u64 relocs_ptr; 568 569 /** Required alignment in graphics aperture */ 570 __u64 alignment; 571 572 /** 573 * Returned value of the updated offset of the object, for future 574 * presumed_offset writes. 575 */ 576 __u64 offset; 577 }; 578 579 struct drm_i915_gem_execbuffer { 580 /** 581 * List of buffers to be validated with their relocations to be 582 * performend on them. 583 * 584 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 585 * 586 * These buffers must be listed in an order such that all relocations 587 * a buffer is performing refer to buffers that have already appeared 588 * in the validate list. 589 */ 590 __u64 buffers_ptr; 591 __u32 buffer_count; 592 593 /** Offset in the batchbuffer to start execution from. */ 594 __u32 batch_start_offset; 595 /** Bytes used in batchbuffer from batch_start_offset */ 596 __u32 batch_len; 597 __u32 DR1; 598 __u32 DR4; 599 __u32 num_cliprects; 600 /** This is a struct drm_clip_rect *cliprects */ 601 __u64 cliprects_ptr; 602 }; 603 604 struct drm_i915_gem_exec_object2 { 605 /** 606 * User's handle for a buffer to be bound into the GTT for this 607 * operation. 608 */ 609 __u32 handle; 610 611 /** Number of relocations to be performed on this buffer */ 612 __u32 relocation_count; 613 /** 614 * Pointer to array of struct drm_i915_gem_relocation_entry containing 615 * the relocations to be performed in this buffer. 616 */ 617 __u64 relocs_ptr; 618 619 /** Required alignment in graphics aperture */ 620 __u64 alignment; 621 622 /** 623 * Returned value of the updated offset of the object, for future 624 * presumed_offset writes. 625 */ 626 __u64 offset; 627 628 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 629 __u64 flags; 630 __u64 rsvd1; 631 __u64 rsvd2; 632 }; 633 634 struct drm_i915_gem_execbuffer2 { 635 /** 636 * List of gem_exec_object2 structs 637 */ 638 __u64 buffers_ptr; 639 __u32 buffer_count; 640 641 /** Offset in the batchbuffer to start execution from. */ 642 __u32 batch_start_offset; 643 /** Bytes used in batchbuffer from batch_start_offset */ 644 __u32 batch_len; 645 __u32 DR1; 646 __u32 DR4; 647 __u32 num_cliprects; 648 /** This is a struct drm_clip_rect *cliprects */ 649 __u64 cliprects_ptr; 650 #define I915_EXEC_RING_MASK (7<<0) 651 #define I915_EXEC_DEFAULT (0<<0) 652 #define I915_EXEC_RENDER (1<<0) 653 #define I915_EXEC_BSD (2<<0) 654 #define I915_EXEC_BLT (3<<0) 655 656 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 657 * Gen6+ only supports relative addressing to dynamic state (default) and 658 * absolute addressing. 659 * 660 * These flags are ignored for the BSD and BLT rings. 661 */ 662 #define I915_EXEC_CONSTANTS_MASK (3<<6) 663 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 664 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 665 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 666 __u64 flags; 667 __u64 rsvd1; /* now used for context info */ 668 __u64 rsvd2; 669 }; 670 671 /** Resets the SO write offset registers for transform feedback on gen7. */ 672 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 673 674 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 675 #define i915_execbuffer2_set_context_id(eb2, context) \ 676 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 677 #define i915_execbuffer2_get_context_id(eb2) \ 678 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 679 680 struct drm_i915_gem_pin { 681 /** Handle of the buffer to be pinned. */ 682 __u32 handle; 683 __u32 pad; 684 685 /** alignment required within the aperture */ 686 __u64 alignment; 687 688 /** Returned GTT offset of the buffer. */ 689 __u64 offset; 690 }; 691 692 struct drm_i915_gem_unpin { 693 /** Handle of the buffer to be unpinned. */ 694 __u32 handle; 695 __u32 pad; 696 }; 697 698 struct drm_i915_gem_busy { 699 /** Handle of the buffer to check for busy */ 700 __u32 handle; 701 702 /** Return busy status (1 if busy, 0 if idle). 703 * The high word is used to indicate on which rings the object 704 * currently resides: 705 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 706 */ 707 __u32 busy; 708 }; 709 710 #define I915_CACHING_NONE 0 711 #define I915_CACHING_CACHED 1 712 713 struct drm_i915_gem_caching { 714 /** 715 * Handle of the buffer to set/get the caching level of. */ 716 __u32 handle; 717 718 /** 719 * Cacheing level to apply or return value 720 * 721 * bits0-15 are for generic caching control (i.e. the above defined 722 * values). bits16-31 are reserved for platform-specific variations 723 * (e.g. l3$ caching on gen7). */ 724 __u32 caching; 725 }; 726 727 #define I915_TILING_NONE 0 728 #define I915_TILING_X 1 729 #define I915_TILING_Y 2 730 731 #define I915_BIT_6_SWIZZLE_NONE 0 732 #define I915_BIT_6_SWIZZLE_9 1 733 #define I915_BIT_6_SWIZZLE_9_10 2 734 #define I915_BIT_6_SWIZZLE_9_11 3 735 #define I915_BIT_6_SWIZZLE_9_10_11 4 736 /* Not seen by userland */ 737 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 738 /* Seen by userland. */ 739 #define I915_BIT_6_SWIZZLE_9_17 6 740 #define I915_BIT_6_SWIZZLE_9_10_17 7 741 742 struct drm_i915_gem_set_tiling { 743 /** Handle of the buffer to have its tiling state updated */ 744 __u32 handle; 745 746 /** 747 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 748 * I915_TILING_Y). 749 * 750 * This value is to be set on request, and will be updated by the 751 * kernel on successful return with the actual chosen tiling layout. 752 * 753 * The tiling mode may be demoted to I915_TILING_NONE when the system 754 * has bit 6 swizzling that can't be managed correctly by GEM. 755 * 756 * Buffer contents become undefined when changing tiling_mode. 757 */ 758 __u32 tiling_mode; 759 760 /** 761 * Stride in bytes for the object when in I915_TILING_X or 762 * I915_TILING_Y. 763 */ 764 __u32 stride; 765 766 /** 767 * Returned address bit 6 swizzling required for CPU access through 768 * mmap mapping. 769 */ 770 __u32 swizzle_mode; 771 }; 772 773 struct drm_i915_gem_get_tiling { 774 /** Handle of the buffer to get tiling state for. */ 775 __u32 handle; 776 777 /** 778 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 779 * I915_TILING_Y). 780 */ 781 __u32 tiling_mode; 782 783 /** 784 * Returned address bit 6 swizzling required for CPU access through 785 * mmap mapping. 786 */ 787 __u32 swizzle_mode; 788 }; 789 790 struct drm_i915_gem_get_aperture { 791 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 792 __u64 aper_size; 793 794 /** 795 * Available space in the aperture used by i915_gem_execbuffer, in 796 * bytes 797 */ 798 __u64 aper_available_size; 799 }; 800 801 struct drm_i915_get_pipe_from_crtc_id { 802 /** ID of CRTC being requested **/ 803 __u32 crtc_id; 804 805 /** pipe of requested CRTC **/ 806 __u32 pipe; 807 }; 808 809 #define I915_MADV_WILLNEED 0 810 #define I915_MADV_DONTNEED 1 811 #define __I915_MADV_PURGED 2 /* internal state */ 812 813 struct drm_i915_gem_madvise { 814 /** Handle of the buffer to change the backing store advice */ 815 __u32 handle; 816 817 /* Advice: either the buffer will be needed again in the near future, 818 * or wont be and could be discarded under memory pressure. 819 */ 820 __u32 madv; 821 822 /** Whether the backing store still exists. */ 823 __u32 retained; 824 }; 825 826 /* flags */ 827 #define I915_OVERLAY_TYPE_MASK 0xff 828 #define I915_OVERLAY_YUV_PLANAR 0x01 829 #define I915_OVERLAY_YUV_PACKED 0x02 830 #define I915_OVERLAY_RGB 0x03 831 832 #define I915_OVERLAY_DEPTH_MASK 0xff00 833 #define I915_OVERLAY_RGB24 0x1000 834 #define I915_OVERLAY_RGB16 0x2000 835 #define I915_OVERLAY_RGB15 0x3000 836 #define I915_OVERLAY_YUV422 0x0100 837 #define I915_OVERLAY_YUV411 0x0200 838 #define I915_OVERLAY_YUV420 0x0300 839 #define I915_OVERLAY_YUV410 0x0400 840 841 #define I915_OVERLAY_SWAP_MASK 0xff0000 842 #define I915_OVERLAY_NO_SWAP 0x000000 843 #define I915_OVERLAY_UV_SWAP 0x010000 844 #define I915_OVERLAY_Y_SWAP 0x020000 845 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 846 847 #define I915_OVERLAY_FLAGS_MASK 0xff000000 848 #define I915_OVERLAY_ENABLE 0x01000000 849 850 struct drm_intel_overlay_put_image { 851 /* various flags and src format description */ 852 __u32 flags; 853 /* source picture description */ 854 __u32 bo_handle; 855 /* stride values and offsets are in bytes, buffer relative */ 856 __u16 stride_Y; /* stride for packed formats */ 857 __u16 stride_UV; 858 __u32 offset_Y; /* offset for packet formats */ 859 __u32 offset_U; 860 __u32 offset_V; 861 /* in pixels */ 862 __u16 src_width; 863 __u16 src_height; 864 /* to compensate the scaling factors for partially covered surfaces */ 865 __u16 src_scan_width; 866 __u16 src_scan_height; 867 /* output crtc description */ 868 __u32 crtc_id; 869 __u16 dst_x; 870 __u16 dst_y; 871 __u16 dst_width; 872 __u16 dst_height; 873 }; 874 875 /* flags */ 876 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 877 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 878 struct drm_intel_overlay_attrs { 879 __u32 flags; 880 __u32 color_key; 881 __s32 brightness; 882 __u32 contrast; 883 __u32 saturation; 884 __u32 gamma0; 885 __u32 gamma1; 886 __u32 gamma2; 887 __u32 gamma3; 888 __u32 gamma4; 889 __u32 gamma5; 890 }; 891 892 /* 893 * Intel sprite handling 894 * 895 * Color keying works with a min/mask/max tuple. Both source and destination 896 * color keying is allowed. 897 * 898 * Source keying: 899 * Sprite pixels within the min & max values, masked against the color channels 900 * specified in the mask field, will be transparent. All other pixels will 901 * be displayed on top of the primary plane. For RGB surfaces, only the min 902 * and mask fields will be used; ranged compares are not allowed. 903 * 904 * Destination keying: 905 * Primary plane pixels that match the min value, masked against the color 906 * channels specified in the mask field, will be replaced by corresponding 907 * pixels from the sprite plane. 908 * 909 * Note that source & destination keying are exclusive; only one can be 910 * active on a given plane. 911 */ 912 913 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 914 #define I915_SET_COLORKEY_DESTINATION (1<<1) 915 #define I915_SET_COLORKEY_SOURCE (1<<2) 916 struct drm_intel_sprite_colorkey { 917 __u32 plane_id; 918 __u32 min_value; 919 __u32 channel_mask; 920 __u32 max_value; 921 __u32 flags; 922 }; 923 924 struct drm_i915_gem_wait { 925 /** Handle of BO we shall wait on */ 926 __u32 bo_handle; 927 __u32 flags; 928 /** Number of nanoseconds to wait, Returns time remaining. */ 929 __s64 timeout_ns; 930 }; 931 932 struct drm_i915_gem_context_create { 933 /* output: id of new context*/ 934 __u32 ctx_id; 935 __u32 pad; 936 }; 937 938 struct drm_i915_gem_context_destroy { 939 __u32 ctx_id; 940 __u32 pad; 941 }; 942 943 struct drm_i915_reg_read { 944 __u64 offset; 945 __u64 val; /* Return value */ 946 }; 947 #endif /* _UAPI_I915_DRM_H_ */ 948