1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _UAPI_I915_DRM_H_ 28 #define _UAPI_I915_DRM_H_ 29 30 #include <drm/drm.h> 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 /** 37 * DOC: uevents generated by i915 on it's device node 38 * 39 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch 40 * event from the gpu l3 cache. Additional information supplied is ROW, 41 * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep 42 * track of these events and if a specific cache-line seems to have a 43 * persistent error remap it with the l3 remapping tool supplied in 44 * intel-gpu-tools. The value supplied with the event is always 1. 45 * 46 * I915_ERROR_UEVENT - Generated upon error detection, currently only via 47 * hangcheck. The error detection event is a good indicator of when things 48 * began to go badly. The value supplied with the event is a 1 upon error 49 * detection, and a 0 upon reset completion, signifying no more error 50 * exists. NOTE: Disabling hangcheck or reset via module parameter will 51 * cause the related events to not be seen. 52 * 53 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the 54 * the GPU. The value supplied with the event is always 1. NOTE: Disable 55 * reset via module parameter will cause this event to not be seen. 56 */ 57 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 58 #define I915_ERROR_UEVENT "ERROR" 59 #define I915_RESET_UEVENT "RESET" 60 61 /* Each region is a minimum of 16k, and there are at most 255 of them. 62 */ 63 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 64 * of chars for next/prev indices */ 65 #define I915_LOG_MIN_TEX_REGION_SIZE 14 66 67 typedef struct _drm_i915_init { 68 enum { 69 I915_INIT_DMA = 0x01, 70 I915_CLEANUP_DMA = 0x02, 71 I915_RESUME_DMA = 0x03 72 } func; 73 unsigned int mmio_offset; 74 int sarea_priv_offset; 75 unsigned int ring_start; 76 unsigned int ring_end; 77 unsigned int ring_size; 78 unsigned int front_offset; 79 unsigned int back_offset; 80 unsigned int depth_offset; 81 unsigned int w; 82 unsigned int h; 83 unsigned int pitch; 84 unsigned int pitch_bits; 85 unsigned int back_pitch; 86 unsigned int depth_pitch; 87 unsigned int cpp; 88 unsigned int chipset; 89 } drm_i915_init_t; 90 91 typedef struct _drm_i915_sarea { 92 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 93 int last_upload; /* last time texture was uploaded */ 94 int last_enqueue; /* last time a buffer was enqueued */ 95 int last_dispatch; /* age of the most recently dispatched buffer */ 96 int ctxOwner; /* last context to upload state */ 97 int texAge; 98 int pf_enabled; /* is pageflipping allowed? */ 99 int pf_active; 100 int pf_current_page; /* which buffer is being displayed? */ 101 int perf_boxes; /* performance boxes to be displayed */ 102 int width, height; /* screen size in pixels */ 103 104 drm_handle_t front_handle; 105 int front_offset; 106 int front_size; 107 108 drm_handle_t back_handle; 109 int back_offset; 110 int back_size; 111 112 drm_handle_t depth_handle; 113 int depth_offset; 114 int depth_size; 115 116 drm_handle_t tex_handle; 117 int tex_offset; 118 int tex_size; 119 int log_tex_granularity; 120 int pitch; 121 int rotation; /* 0, 90, 180 or 270 */ 122 int rotated_offset; 123 int rotated_size; 124 int rotated_pitch; 125 int virtualX, virtualY; 126 127 unsigned int front_tiled; 128 unsigned int back_tiled; 129 unsigned int depth_tiled; 130 unsigned int rotated_tiled; 131 unsigned int rotated2_tiled; 132 133 int pipeA_x; 134 int pipeA_y; 135 int pipeA_w; 136 int pipeA_h; 137 int pipeB_x; 138 int pipeB_y; 139 int pipeB_w; 140 int pipeB_h; 141 142 /* fill out some space for old userspace triple buffer */ 143 drm_handle_t unused_handle; 144 __u32 unused1, unused2, unused3; 145 146 /* buffer object handles for static buffers. May change 147 * over the lifetime of the client. 148 */ 149 __u32 front_bo_handle; 150 __u32 back_bo_handle; 151 __u32 unused_bo_handle; 152 __u32 depth_bo_handle; 153 154 } drm_i915_sarea_t; 155 156 /* due to userspace building against these headers we need some compat here */ 157 #define planeA_x pipeA_x 158 #define planeA_y pipeA_y 159 #define planeA_w pipeA_w 160 #define planeA_h pipeA_h 161 #define planeB_x pipeB_x 162 #define planeB_y pipeB_y 163 #define planeB_w pipeB_w 164 #define planeB_h pipeB_h 165 166 /* Flags for perf_boxes 167 */ 168 #define I915_BOX_RING_EMPTY 0x1 169 #define I915_BOX_FLIP 0x2 170 #define I915_BOX_WAIT 0x4 171 #define I915_BOX_TEXTURE_LOAD 0x8 172 #define I915_BOX_LOST_CONTEXT 0x10 173 174 /* 175 * i915 specific ioctls. 176 * 177 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 178 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 179 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 180 */ 181 #define DRM_I915_INIT 0x00 182 #define DRM_I915_FLUSH 0x01 183 #define DRM_I915_FLIP 0x02 184 #define DRM_I915_BATCHBUFFER 0x03 185 #define DRM_I915_IRQ_EMIT 0x04 186 #define DRM_I915_IRQ_WAIT 0x05 187 #define DRM_I915_GETPARAM 0x06 188 #define DRM_I915_SETPARAM 0x07 189 #define DRM_I915_ALLOC 0x08 190 #define DRM_I915_FREE 0x09 191 #define DRM_I915_INIT_HEAP 0x0a 192 #define DRM_I915_CMDBUFFER 0x0b 193 #define DRM_I915_DESTROY_HEAP 0x0c 194 #define DRM_I915_SET_VBLANK_PIPE 0x0d 195 #define DRM_I915_GET_VBLANK_PIPE 0x0e 196 #define DRM_I915_VBLANK_SWAP 0x0f 197 #define DRM_I915_HWS_ADDR 0x11 198 #define DRM_I915_GEM_INIT 0x13 199 #define DRM_I915_GEM_EXECBUFFER 0x14 200 #define DRM_I915_GEM_PIN 0x15 201 #define DRM_I915_GEM_UNPIN 0x16 202 #define DRM_I915_GEM_BUSY 0x17 203 #define DRM_I915_GEM_THROTTLE 0x18 204 #define DRM_I915_GEM_ENTERVT 0x19 205 #define DRM_I915_GEM_LEAVEVT 0x1a 206 #define DRM_I915_GEM_CREATE 0x1b 207 #define DRM_I915_GEM_PREAD 0x1c 208 #define DRM_I915_GEM_PWRITE 0x1d 209 #define DRM_I915_GEM_MMAP 0x1e 210 #define DRM_I915_GEM_SET_DOMAIN 0x1f 211 #define DRM_I915_GEM_SW_FINISH 0x20 212 #define DRM_I915_GEM_SET_TILING 0x21 213 #define DRM_I915_GEM_GET_TILING 0x22 214 #define DRM_I915_GEM_GET_APERTURE 0x23 215 #define DRM_I915_GEM_MMAP_GTT 0x24 216 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 217 #define DRM_I915_GEM_MADVISE 0x26 218 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 219 #define DRM_I915_OVERLAY_ATTRS 0x28 220 #define DRM_I915_GEM_EXECBUFFER2 0x29 221 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 222 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 223 #define DRM_I915_GEM_WAIT 0x2c 224 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 225 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 226 #define DRM_I915_GEM_SET_CACHING 0x2f 227 #define DRM_I915_GEM_GET_CACHING 0x30 228 #define DRM_I915_REG_READ 0x31 229 #define DRM_I915_GET_RESET_STATS 0x32 230 #define DRM_I915_GEM_USERPTR 0x33 231 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 232 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 233 234 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 235 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 236 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 237 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 238 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 239 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 240 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 241 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 242 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 243 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 244 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 245 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 246 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 247 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 248 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 249 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 250 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 251 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 252 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 253 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 254 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 255 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 256 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 257 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 258 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 259 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 260 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 261 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 262 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 263 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 264 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 265 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 266 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 267 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 268 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 269 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 270 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 271 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 272 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 273 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 274 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 275 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 276 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 277 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 278 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 279 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 280 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 281 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 282 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 283 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 284 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 285 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 286 287 /* Allow drivers to submit batchbuffers directly to hardware, relying 288 * on the security mechanisms provided by hardware. 289 */ 290 typedef struct drm_i915_batchbuffer { 291 int start; /* agp offset */ 292 int used; /* nr bytes in use */ 293 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 294 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 295 int num_cliprects; /* mulitpass with multiple cliprects? */ 296 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 297 } drm_i915_batchbuffer_t; 298 299 /* As above, but pass a pointer to userspace buffer which can be 300 * validated by the kernel prior to sending to hardware. 301 */ 302 typedef struct _drm_i915_cmdbuffer { 303 char __user *buf; /* pointer to userspace command buffer */ 304 int sz; /* nr bytes in buf */ 305 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 306 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 307 int num_cliprects; /* mulitpass with multiple cliprects? */ 308 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 309 } drm_i915_cmdbuffer_t; 310 311 /* Userspace can request & wait on irq's: 312 */ 313 typedef struct drm_i915_irq_emit { 314 int __user *irq_seq; 315 } drm_i915_irq_emit_t; 316 317 typedef struct drm_i915_irq_wait { 318 int irq_seq; 319 } drm_i915_irq_wait_t; 320 321 /* Ioctl to query kernel params: 322 */ 323 #define I915_PARAM_IRQ_ACTIVE 1 324 #define I915_PARAM_ALLOW_BATCHBUFFER 2 325 #define I915_PARAM_LAST_DISPATCH 3 326 #define I915_PARAM_CHIPSET_ID 4 327 #define I915_PARAM_HAS_GEM 5 328 #define I915_PARAM_NUM_FENCES_AVAIL 6 329 #define I915_PARAM_HAS_OVERLAY 7 330 #define I915_PARAM_HAS_PAGEFLIPPING 8 331 #define I915_PARAM_HAS_EXECBUF2 9 332 #define I915_PARAM_HAS_BSD 10 333 #define I915_PARAM_HAS_BLT 11 334 #define I915_PARAM_HAS_RELAXED_FENCING 12 335 #define I915_PARAM_HAS_COHERENT_RINGS 13 336 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 337 #define I915_PARAM_HAS_RELAXED_DELTA 15 338 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 339 #define I915_PARAM_HAS_LLC 17 340 #define I915_PARAM_HAS_ALIASING_PPGTT 18 341 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 342 #define I915_PARAM_HAS_SEMAPHORES 20 343 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 344 #define I915_PARAM_HAS_VEBOX 22 345 #define I915_PARAM_HAS_SECURE_BATCHES 23 346 #define I915_PARAM_HAS_PINNED_BATCHES 24 347 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 348 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 349 #define I915_PARAM_HAS_WT 27 350 #define I915_PARAM_CMD_PARSER_VERSION 28 351 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 352 #define I915_PARAM_MMAP_VERSION 30 353 #define I915_PARAM_HAS_BSD2 31 354 #define I915_PARAM_REVISION 32 355 #define I915_PARAM_SUBSLICE_TOTAL 33 356 #define I915_PARAM_EU_TOTAL 34 357 358 typedef struct drm_i915_getparam { 359 int param; 360 int __user *value; 361 } drm_i915_getparam_t; 362 363 /* Ioctl to set kernel params: 364 */ 365 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 366 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 367 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 368 #define I915_SETPARAM_NUM_USED_FENCES 4 369 370 typedef struct drm_i915_setparam { 371 int param; 372 int value; 373 } drm_i915_setparam_t; 374 375 /* A memory manager for regions of shared memory: 376 */ 377 #define I915_MEM_REGION_AGP 1 378 379 typedef struct drm_i915_mem_alloc { 380 int region; 381 int alignment; 382 int size; 383 int __user *region_offset; /* offset from start of fb or agp */ 384 } drm_i915_mem_alloc_t; 385 386 typedef struct drm_i915_mem_free { 387 int region; 388 int region_offset; 389 } drm_i915_mem_free_t; 390 391 typedef struct drm_i915_mem_init_heap { 392 int region; 393 int size; 394 int start; 395 } drm_i915_mem_init_heap_t; 396 397 /* Allow memory manager to be torn down and re-initialized (eg on 398 * rotate): 399 */ 400 typedef struct drm_i915_mem_destroy_heap { 401 int region; 402 } drm_i915_mem_destroy_heap_t; 403 404 /* Allow X server to configure which pipes to monitor for vblank signals 405 */ 406 #define DRM_I915_VBLANK_PIPE_A 1 407 #define DRM_I915_VBLANK_PIPE_B 2 408 409 typedef struct drm_i915_vblank_pipe { 410 int pipe; 411 } drm_i915_vblank_pipe_t; 412 413 /* Schedule buffer swap at given vertical blank: 414 */ 415 typedef struct drm_i915_vblank_swap { 416 drm_drawable_t drawable; 417 enum drm_vblank_seq_type seqtype; 418 unsigned int sequence; 419 } drm_i915_vblank_swap_t; 420 421 typedef struct drm_i915_hws_addr { 422 __u64 addr; 423 } drm_i915_hws_addr_t; 424 425 struct drm_i915_gem_init { 426 /** 427 * Beginning offset in the GTT to be managed by the DRM memory 428 * manager. 429 */ 430 __u64 gtt_start; 431 /** 432 * Ending offset in the GTT to be managed by the DRM memory 433 * manager. 434 */ 435 __u64 gtt_end; 436 }; 437 438 struct drm_i915_gem_create { 439 /** 440 * Requested size for the object. 441 * 442 * The (page-aligned) allocated size for the object will be returned. 443 */ 444 __u64 size; 445 /** 446 * Returned handle for the object. 447 * 448 * Object handles are nonzero. 449 */ 450 __u32 handle; 451 __u32 pad; 452 }; 453 454 struct drm_i915_gem_pread { 455 /** Handle for the object being read. */ 456 __u32 handle; 457 __u32 pad; 458 /** Offset into the object to read from */ 459 __u64 offset; 460 /** Length of data to read */ 461 __u64 size; 462 /** 463 * Pointer to write the data into. 464 * 465 * This is a fixed-size type for 32/64 compatibility. 466 */ 467 __u64 data_ptr; 468 }; 469 470 struct drm_i915_gem_pwrite { 471 /** Handle for the object being written to. */ 472 __u32 handle; 473 __u32 pad; 474 /** Offset into the object to write to */ 475 __u64 offset; 476 /** Length of data to write */ 477 __u64 size; 478 /** 479 * Pointer to read the data from. 480 * 481 * This is a fixed-size type for 32/64 compatibility. 482 */ 483 __u64 data_ptr; 484 }; 485 486 struct drm_i915_gem_mmap { 487 /** Handle for the object being mapped. */ 488 __u32 handle; 489 __u32 pad; 490 /** Offset in the object to map. */ 491 __u64 offset; 492 /** 493 * Length of data to map. 494 * 495 * The value will be page-aligned. 496 */ 497 __u64 size; 498 /** 499 * Returned pointer the data was mapped at. 500 * 501 * This is a fixed-size type for 32/64 compatibility. 502 */ 503 __u64 addr_ptr; 504 505 /** 506 * Flags for extended behaviour. 507 * 508 * Added in version 2. 509 */ 510 __u64 flags; 511 #define I915_MMAP_WC 0x1 512 }; 513 514 struct drm_i915_gem_mmap_gtt { 515 /** Handle for the object being mapped. */ 516 __u32 handle; 517 __u32 pad; 518 /** 519 * Fake offset to use for subsequent mmap call 520 * 521 * This is a fixed-size type for 32/64 compatibility. 522 */ 523 __u64 offset; 524 }; 525 526 struct drm_i915_gem_set_domain { 527 /** Handle for the object */ 528 __u32 handle; 529 530 /** New read domains */ 531 __u32 read_domains; 532 533 /** New write domain */ 534 __u32 write_domain; 535 }; 536 537 struct drm_i915_gem_sw_finish { 538 /** Handle for the object */ 539 __u32 handle; 540 }; 541 542 struct drm_i915_gem_relocation_entry { 543 /** 544 * Handle of the buffer being pointed to by this relocation entry. 545 * 546 * It's appealing to make this be an index into the mm_validate_entry 547 * list to refer to the buffer, but this allows the driver to create 548 * a relocation list for state buffers and not re-write it per 549 * exec using the buffer. 550 */ 551 __u32 target_handle; 552 553 /** 554 * Value to be added to the offset of the target buffer to make up 555 * the relocation entry. 556 */ 557 __u32 delta; 558 559 /** Offset in the buffer the relocation entry will be written into */ 560 __u64 offset; 561 562 /** 563 * Offset value of the target buffer that the relocation entry was last 564 * written as. 565 * 566 * If the buffer has the same offset as last time, we can skip syncing 567 * and writing the relocation. This value is written back out by 568 * the execbuffer ioctl when the relocation is written. 569 */ 570 __u64 presumed_offset; 571 572 /** 573 * Target memory domains read by this operation. 574 */ 575 __u32 read_domains; 576 577 /** 578 * Target memory domains written by this operation. 579 * 580 * Note that only one domain may be written by the whole 581 * execbuffer operation, so that where there are conflicts, 582 * the application will get -EINVAL back. 583 */ 584 __u32 write_domain; 585 }; 586 587 /** @{ 588 * Intel memory domains 589 * 590 * Most of these just align with the various caches in 591 * the system and are used to flush and invalidate as 592 * objects end up cached in different domains. 593 */ 594 /** CPU cache */ 595 #define I915_GEM_DOMAIN_CPU 0x00000001 596 /** Render cache, used by 2D and 3D drawing */ 597 #define I915_GEM_DOMAIN_RENDER 0x00000002 598 /** Sampler cache, used by texture engine */ 599 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 600 /** Command queue, used to load batch buffers */ 601 #define I915_GEM_DOMAIN_COMMAND 0x00000008 602 /** Instruction cache, used by shader programs */ 603 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 604 /** Vertex address cache */ 605 #define I915_GEM_DOMAIN_VERTEX 0x00000020 606 /** GTT domain - aperture and scanout */ 607 #define I915_GEM_DOMAIN_GTT 0x00000040 608 /** @} */ 609 610 struct drm_i915_gem_exec_object { 611 /** 612 * User's handle for a buffer to be bound into the GTT for this 613 * operation. 614 */ 615 __u32 handle; 616 617 /** Number of relocations to be performed on this buffer */ 618 __u32 relocation_count; 619 /** 620 * Pointer to array of struct drm_i915_gem_relocation_entry containing 621 * the relocations to be performed in this buffer. 622 */ 623 __u64 relocs_ptr; 624 625 /** Required alignment in graphics aperture */ 626 __u64 alignment; 627 628 /** 629 * Returned value of the updated offset of the object, for future 630 * presumed_offset writes. 631 */ 632 __u64 offset; 633 }; 634 635 struct drm_i915_gem_execbuffer { 636 /** 637 * List of buffers to be validated with their relocations to be 638 * performend on them. 639 * 640 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 641 * 642 * These buffers must be listed in an order such that all relocations 643 * a buffer is performing refer to buffers that have already appeared 644 * in the validate list. 645 */ 646 __u64 buffers_ptr; 647 __u32 buffer_count; 648 649 /** Offset in the batchbuffer to start execution from. */ 650 __u32 batch_start_offset; 651 /** Bytes used in batchbuffer from batch_start_offset */ 652 __u32 batch_len; 653 __u32 DR1; 654 __u32 DR4; 655 __u32 num_cliprects; 656 /** This is a struct drm_clip_rect *cliprects */ 657 __u64 cliprects_ptr; 658 }; 659 660 struct drm_i915_gem_exec_object2 { 661 /** 662 * User's handle for a buffer to be bound into the GTT for this 663 * operation. 664 */ 665 __u32 handle; 666 667 /** Number of relocations to be performed on this buffer */ 668 __u32 relocation_count; 669 /** 670 * Pointer to array of struct drm_i915_gem_relocation_entry containing 671 * the relocations to be performed in this buffer. 672 */ 673 __u64 relocs_ptr; 674 675 /** Required alignment in graphics aperture */ 676 __u64 alignment; 677 678 /** 679 * Returned value of the updated offset of the object, for future 680 * presumed_offset writes. 681 */ 682 __u64 offset; 683 684 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 685 #define EXEC_OBJECT_NEEDS_GTT (1<<1) 686 #define EXEC_OBJECT_WRITE (1<<2) 687 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) 688 __u64 flags; 689 690 __u64 rsvd1; 691 __u64 rsvd2; 692 }; 693 694 struct drm_i915_gem_execbuffer2 { 695 /** 696 * List of gem_exec_object2 structs 697 */ 698 __u64 buffers_ptr; 699 __u32 buffer_count; 700 701 /** Offset in the batchbuffer to start execution from. */ 702 __u32 batch_start_offset; 703 /** Bytes used in batchbuffer from batch_start_offset */ 704 __u32 batch_len; 705 __u32 DR1; 706 __u32 DR4; 707 __u32 num_cliprects; 708 /** This is a struct drm_clip_rect *cliprects */ 709 __u64 cliprects_ptr; 710 #define I915_EXEC_RING_MASK (7<<0) 711 #define I915_EXEC_DEFAULT (0<<0) 712 #define I915_EXEC_RENDER (1<<0) 713 #define I915_EXEC_BSD (2<<0) 714 #define I915_EXEC_BLT (3<<0) 715 #define I915_EXEC_VEBOX (4<<0) 716 717 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 718 * Gen6+ only supports relative addressing to dynamic state (default) and 719 * absolute addressing. 720 * 721 * These flags are ignored for the BSD and BLT rings. 722 */ 723 #define I915_EXEC_CONSTANTS_MASK (3<<6) 724 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 725 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 726 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 727 __u64 flags; 728 __u64 rsvd1; /* now used for context info */ 729 __u64 rsvd2; 730 }; 731 732 /** Resets the SO write offset registers for transform feedback on gen7. */ 733 #define I915_EXEC_GEN7_SOL_RESET (1<<8) 734 735 /** Request a privileged ("secure") batch buffer. Note only available for 736 * DRM_ROOT_ONLY | DRM_MASTER processes. 737 */ 738 #define I915_EXEC_SECURE (1<<9) 739 740 /** Inform the kernel that the batch is and will always be pinned. This 741 * negates the requirement for a workaround to be performed to avoid 742 * an incoherent CS (such as can be found on 830/845). If this flag is 743 * not passed, the kernel will endeavour to make sure the batch is 744 * coherent with the CS before execution. If this flag is passed, 745 * userspace assumes the responsibility for ensuring the same. 746 */ 747 #define I915_EXEC_IS_PINNED (1<<10) 748 749 /** Provide a hint to the kernel that the command stream and auxiliary 750 * state buffers already holds the correct presumed addresses and so the 751 * relocation process may be skipped if no buffers need to be moved in 752 * preparation for the execbuffer. 753 */ 754 #define I915_EXEC_NO_RELOC (1<<11) 755 756 /** Use the reloc.handle as an index into the exec object array rather 757 * than as the per-file handle. 758 */ 759 #define I915_EXEC_HANDLE_LUT (1<<12) 760 761 /** Used for switching BSD rings on the platforms with two BSD rings */ 762 #define I915_EXEC_BSD_MASK (3<<13) 763 #define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */ 764 #define I915_EXEC_BSD_RING1 (1<<13) 765 #define I915_EXEC_BSD_RING2 (2<<13) 766 767 #define __I915_EXEC_UNKNOWN_FLAGS -(1<<15) 768 769 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 770 #define i915_execbuffer2_set_context_id(eb2, context) \ 771 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 772 #define i915_execbuffer2_get_context_id(eb2) \ 773 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 774 775 struct drm_i915_gem_pin { 776 /** Handle of the buffer to be pinned. */ 777 __u32 handle; 778 __u32 pad; 779 780 /** alignment required within the aperture */ 781 __u64 alignment; 782 783 /** Returned GTT offset of the buffer. */ 784 __u64 offset; 785 }; 786 787 struct drm_i915_gem_unpin { 788 /** Handle of the buffer to be unpinned. */ 789 __u32 handle; 790 __u32 pad; 791 }; 792 793 struct drm_i915_gem_busy { 794 /** Handle of the buffer to check for busy */ 795 __u32 handle; 796 797 /** Return busy status (1 if busy, 0 if idle). 798 * The high word is used to indicate on which rings the object 799 * currently resides: 800 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 801 */ 802 __u32 busy; 803 }; 804 805 /** 806 * I915_CACHING_NONE 807 * 808 * GPU access is not coherent with cpu caches. Default for machines without an 809 * LLC. 810 */ 811 #define I915_CACHING_NONE 0 812 /** 813 * I915_CACHING_CACHED 814 * 815 * GPU access is coherent with cpu caches and furthermore the data is cached in 816 * last-level caches shared between cpu cores and the gpu GT. Default on 817 * machines with HAS_LLC. 818 */ 819 #define I915_CACHING_CACHED 1 820 /** 821 * I915_CACHING_DISPLAY 822 * 823 * Special GPU caching mode which is coherent with the scanout engines. 824 * Transparently falls back to I915_CACHING_NONE on platforms where no special 825 * cache mode (like write-through or gfdt flushing) is available. The kernel 826 * automatically sets this mode when using a buffer as a scanout target. 827 * Userspace can manually set this mode to avoid a costly stall and clflush in 828 * the hotpath of drawing the first frame. 829 */ 830 #define I915_CACHING_DISPLAY 2 831 832 struct drm_i915_gem_caching { 833 /** 834 * Handle of the buffer to set/get the caching level of. */ 835 __u32 handle; 836 837 /** 838 * Cacheing level to apply or return value 839 * 840 * bits0-15 are for generic caching control (i.e. the above defined 841 * values). bits16-31 are reserved for platform-specific variations 842 * (e.g. l3$ caching on gen7). */ 843 __u32 caching; 844 }; 845 846 #define I915_TILING_NONE 0 847 #define I915_TILING_X 1 848 #define I915_TILING_Y 2 849 850 #define I915_BIT_6_SWIZZLE_NONE 0 851 #define I915_BIT_6_SWIZZLE_9 1 852 #define I915_BIT_6_SWIZZLE_9_10 2 853 #define I915_BIT_6_SWIZZLE_9_11 3 854 #define I915_BIT_6_SWIZZLE_9_10_11 4 855 /* Not seen by userland */ 856 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 857 /* Seen by userland. */ 858 #define I915_BIT_6_SWIZZLE_9_17 6 859 #define I915_BIT_6_SWIZZLE_9_10_17 7 860 861 struct drm_i915_gem_set_tiling { 862 /** Handle of the buffer to have its tiling state updated */ 863 __u32 handle; 864 865 /** 866 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 867 * I915_TILING_Y). 868 * 869 * This value is to be set on request, and will be updated by the 870 * kernel on successful return with the actual chosen tiling layout. 871 * 872 * The tiling mode may be demoted to I915_TILING_NONE when the system 873 * has bit 6 swizzling that can't be managed correctly by GEM. 874 * 875 * Buffer contents become undefined when changing tiling_mode. 876 */ 877 __u32 tiling_mode; 878 879 /** 880 * Stride in bytes for the object when in I915_TILING_X or 881 * I915_TILING_Y. 882 */ 883 __u32 stride; 884 885 /** 886 * Returned address bit 6 swizzling required for CPU access through 887 * mmap mapping. 888 */ 889 __u32 swizzle_mode; 890 }; 891 892 struct drm_i915_gem_get_tiling { 893 /** Handle of the buffer to get tiling state for. */ 894 __u32 handle; 895 896 /** 897 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 898 * I915_TILING_Y). 899 */ 900 __u32 tiling_mode; 901 902 /** 903 * Returned address bit 6 swizzling required for CPU access through 904 * mmap mapping. 905 */ 906 __u32 swizzle_mode; 907 908 /** 909 * Returned address bit 6 swizzling required for CPU access through 910 * mmap mapping whilst bound. 911 */ 912 __u32 phys_swizzle_mode; 913 }; 914 915 struct drm_i915_gem_get_aperture { 916 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 917 __u64 aper_size; 918 919 /** 920 * Available space in the aperture used by i915_gem_execbuffer, in 921 * bytes 922 */ 923 __u64 aper_available_size; 924 }; 925 926 struct drm_i915_get_pipe_from_crtc_id { 927 /** ID of CRTC being requested **/ 928 __u32 crtc_id; 929 930 /** pipe of requested CRTC **/ 931 __u32 pipe; 932 }; 933 934 #define I915_MADV_WILLNEED 0 935 #define I915_MADV_DONTNEED 1 936 #define __I915_MADV_PURGED 2 /* internal state */ 937 938 struct drm_i915_gem_madvise { 939 /** Handle of the buffer to change the backing store advice */ 940 __u32 handle; 941 942 /* Advice: either the buffer will be needed again in the near future, 943 * or wont be and could be discarded under memory pressure. 944 */ 945 __u32 madv; 946 947 /** Whether the backing store still exists. */ 948 __u32 retained; 949 }; 950 951 /* flags */ 952 #define I915_OVERLAY_TYPE_MASK 0xff 953 #define I915_OVERLAY_YUV_PLANAR 0x01 954 #define I915_OVERLAY_YUV_PACKED 0x02 955 #define I915_OVERLAY_RGB 0x03 956 957 #define I915_OVERLAY_DEPTH_MASK 0xff00 958 #define I915_OVERLAY_RGB24 0x1000 959 #define I915_OVERLAY_RGB16 0x2000 960 #define I915_OVERLAY_RGB15 0x3000 961 #define I915_OVERLAY_YUV422 0x0100 962 #define I915_OVERLAY_YUV411 0x0200 963 #define I915_OVERLAY_YUV420 0x0300 964 #define I915_OVERLAY_YUV410 0x0400 965 966 #define I915_OVERLAY_SWAP_MASK 0xff0000 967 #define I915_OVERLAY_NO_SWAP 0x000000 968 #define I915_OVERLAY_UV_SWAP 0x010000 969 #define I915_OVERLAY_Y_SWAP 0x020000 970 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 971 972 #define I915_OVERLAY_FLAGS_MASK 0xff000000 973 #define I915_OVERLAY_ENABLE 0x01000000 974 975 struct drm_intel_overlay_put_image { 976 /* various flags and src format description */ 977 __u32 flags; 978 /* source picture description */ 979 __u32 bo_handle; 980 /* stride values and offsets are in bytes, buffer relative */ 981 __u16 stride_Y; /* stride for packed formats */ 982 __u16 stride_UV; 983 __u32 offset_Y; /* offset for packet formats */ 984 __u32 offset_U; 985 __u32 offset_V; 986 /* in pixels */ 987 __u16 src_width; 988 __u16 src_height; 989 /* to compensate the scaling factors for partially covered surfaces */ 990 __u16 src_scan_width; 991 __u16 src_scan_height; 992 /* output crtc description */ 993 __u32 crtc_id; 994 __u16 dst_x; 995 __u16 dst_y; 996 __u16 dst_width; 997 __u16 dst_height; 998 }; 999 1000 /* flags */ 1001 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 1002 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 1003 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) 1004 struct drm_intel_overlay_attrs { 1005 __u32 flags; 1006 __u32 color_key; 1007 __s32 brightness; 1008 __u32 contrast; 1009 __u32 saturation; 1010 __u32 gamma0; 1011 __u32 gamma1; 1012 __u32 gamma2; 1013 __u32 gamma3; 1014 __u32 gamma4; 1015 __u32 gamma5; 1016 }; 1017 1018 /* 1019 * Intel sprite handling 1020 * 1021 * Color keying works with a min/mask/max tuple. Both source and destination 1022 * color keying is allowed. 1023 * 1024 * Source keying: 1025 * Sprite pixels within the min & max values, masked against the color channels 1026 * specified in the mask field, will be transparent. All other pixels will 1027 * be displayed on top of the primary plane. For RGB surfaces, only the min 1028 * and mask fields will be used; ranged compares are not allowed. 1029 * 1030 * Destination keying: 1031 * Primary plane pixels that match the min value, masked against the color 1032 * channels specified in the mask field, will be replaced by corresponding 1033 * pixels from the sprite plane. 1034 * 1035 * Note that source & destination keying are exclusive; only one can be 1036 * active on a given plane. 1037 */ 1038 1039 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 1040 #define I915_SET_COLORKEY_DESTINATION (1<<1) 1041 #define I915_SET_COLORKEY_SOURCE (1<<2) 1042 struct drm_intel_sprite_colorkey { 1043 __u32 plane_id; 1044 __u32 min_value; 1045 __u32 channel_mask; 1046 __u32 max_value; 1047 __u32 flags; 1048 }; 1049 1050 struct drm_i915_gem_wait { 1051 /** Handle of BO we shall wait on */ 1052 __u32 bo_handle; 1053 __u32 flags; 1054 /** Number of nanoseconds to wait, Returns time remaining. */ 1055 __s64 timeout_ns; 1056 }; 1057 1058 struct drm_i915_gem_context_create { 1059 /* output: id of new context*/ 1060 __u32 ctx_id; 1061 __u32 pad; 1062 }; 1063 1064 struct drm_i915_gem_context_destroy { 1065 __u32 ctx_id; 1066 __u32 pad; 1067 }; 1068 1069 struct drm_i915_reg_read { 1070 __u64 offset; 1071 __u64 val; /* Return value */ 1072 }; 1073 /* Known registers: 1074 * 1075 * Render engine timestamp - 0x2358 + 64bit - gen7+ 1076 * - Note this register returns an invalid value if using the default 1077 * single instruction 8byte read, in order to workaround that use 1078 * offset (0x2538 | 1) instead. 1079 * 1080 */ 1081 1082 struct drm_i915_reset_stats { 1083 __u32 ctx_id; 1084 __u32 flags; 1085 1086 /* All resets since boot/module reload, for all contexts */ 1087 __u32 reset_count; 1088 1089 /* Number of batches lost when active in GPU, for this context */ 1090 __u32 batch_active; 1091 1092 /* Number of batches lost pending for execution, for this context */ 1093 __u32 batch_pending; 1094 1095 __u32 pad; 1096 }; 1097 1098 struct drm_i915_gem_userptr { 1099 __u64 user_ptr; 1100 __u64 user_size; 1101 __u32 flags; 1102 #define I915_USERPTR_READ_ONLY 0x1 1103 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 1104 /** 1105 * Returned handle for the object. 1106 * 1107 * Object handles are nonzero. 1108 */ 1109 __u32 handle; 1110 }; 1111 1112 struct drm_i915_gem_context_param { 1113 __u32 ctx_id; 1114 __u32 size; 1115 __u64 param; 1116 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 1117 __u64 value; 1118 }; 1119 1120 #endif /* _UAPI_I915_DRM_H_ */ 1121