1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 /** 34 * DOC: overview 35 * 36 * In the DRM subsystem, framebuffer pixel formats are described using the 37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 38 * fourcc code, a Format Modifier may optionally be provided, in order to 39 * further describe the buffer's format - for example tiling or compression. 40 * 41 * Format Modifiers 42 * ---------------- 43 * 44 * Format modifiers are used in conjunction with a fourcc code, forming a 45 * unique fourcc:modifier pair. This format:modifier pair must fully define the 46 * format and data layout of the buffer, and should be the only way to describe 47 * that particular buffer. 48 * 49 * Having multiple fourcc:modifier pairs which describe the same layout should 50 * be avoided, as such aliases run the risk of different drivers exposing 51 * different names for the same data format, forcing userspace to understand 52 * that they are aliases. 53 * 54 * Format modifiers may change any property of the buffer, including the number 55 * of planes and/or the required allocation size. Format modifiers are 56 * vendor-namespaced, and as such the relationship between a fourcc code and a 57 * modifier is specific to the modifier being used. For example, some modifiers 58 * may preserve meaning - such as number of planes - from the fourcc code, 59 * whereas others may not. 60 * 61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 62 * match only a single modifier. A modifier must not be a subset of layouts of 63 * another modifier. For instance, it's incorrect to encode pitch alignment in 64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 65 * aligned modifier. That said, modifiers can have implicit minimal 66 * requirements. 67 * 68 * For modifiers where the combination of fourcc code and modifier can alias, 69 * a canonical pair needs to be defined and used by all drivers. Preferred 70 * combinations are also encouraged where all combinations might lead to 71 * confusion and unnecessarily reduced interoperability. An example for the 72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 73 * 74 * There are two kinds of modifier users: 75 * 76 * - Kernel and user-space drivers: for drivers it's important that modifiers 77 * don't alias, otherwise two drivers might support the same format but use 78 * different aliases, preventing them from sharing buffers in an efficient 79 * format. 80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 81 * see modifiers as opaque tokens they can check for equality and intersect. 82 * These users mustn't need to know to reason about the modifier value 83 * (i.e. they are not expected to extract information out of the modifier). 84 * 85 * Vendors should document their modifier usage in as much detail as 86 * possible, to ensure maximum compatibility across devices, drivers and 87 * applications. 88 * 89 * The authoritative list of format modifier codes is found in 90 * `include/uapi/drm/drm_fourcc.h` 91 * 92 * Open Source User Waiver 93 * ----------------------- 94 * 95 * Because this is the authoritative source for pixel formats and modifiers 96 * referenced by GL, Vulkan extensions and other standards and hence used both 97 * by open source and closed source driver stacks, the usual requirement for an 98 * upstream in-kernel or open source userspace user does not apply. 99 * 100 * To ensure, as much as feasible, compatibility across stacks and avoid 101 * confusion with incompatible enumerations stakeholders for all relevant driver 102 * stacks should approve additions. 103 */ 104 105 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ 106 ((__u32)(c) << 16) | ((__u32)(d) << 24)) 107 108 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 109 110 /* Reserve 0 for the invalid format specifier */ 111 #define DRM_FORMAT_INVALID 0 112 113 /* color index */ 114 #define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */ 115 #define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */ 116 #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */ 117 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 118 119 /* 1 bpp Darkness (inverse relationship between channel value and brightness) */ 120 #define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */ 121 122 /* 2 bpp Darkness (inverse relationship between channel value and brightness) */ 123 #define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */ 124 125 /* 4 bpp Darkness (inverse relationship between channel value and brightness) */ 126 #define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */ 127 128 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */ 129 #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */ 130 131 /* 1 bpp Red (direct relationship between channel value and brightness) */ 132 #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */ 133 134 /* 2 bpp Red (direct relationship between channel value and brightness) */ 135 #define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */ 136 137 /* 4 bpp Red (direct relationship between channel value and brightness) */ 138 #define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */ 139 140 /* 8 bpp Red (direct relationship between channel value and brightness) */ 141 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 142 143 /* 10 bpp Red (direct relationship between channel value and brightness) */ 144 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ 145 146 /* 12 bpp Red (direct relationship between channel value and brightness) */ 147 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ 148 149 /* 16 bpp Red (direct relationship between channel value and brightness) */ 150 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 151 152 /* 16 bpp RG */ 153 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 154 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 155 156 /* 32 bpp RG */ 157 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 158 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 159 160 /* 8 bpp RGB */ 161 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 162 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 163 164 /* 16 bpp RGB */ 165 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 166 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 167 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 168 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 169 170 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 171 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 172 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 173 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 174 175 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 176 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 177 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 178 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 179 180 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 181 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 182 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 183 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 184 185 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 186 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 187 188 /* 24 bpp RGB */ 189 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 190 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 191 192 /* 32 bpp RGB */ 193 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 194 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 195 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 196 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 197 198 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 199 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 200 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 201 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 202 203 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 204 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 205 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 206 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 207 208 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 209 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 210 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 211 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 212 213 /* 64 bpp RGB */ 214 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 215 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 216 217 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 218 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 219 220 /* 221 * Half-Floating point - 16b/component 222 * IEEE 754-2008 binary16 half-precision float 223 * [15:0] sign:exponent:mantissa 1:5:10 224 */ 225 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 226 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 227 228 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 229 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 230 231 #define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */ 232 #define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */ 233 #define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */ 234 235 /* 236 * Floating point - 32b/component 237 * IEEE 754-2008 binary32 float 238 * [31:0] sign:exponent:mantissa 1:8:23 239 */ 240 #define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */ 241 #define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */ 242 #define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian */ 243 #define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */ 244 245 /* 246 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 247 * of unused padding per component: 248 */ 249 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 250 251 /* packed YCbCr */ 252 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 253 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 254 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 255 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 256 257 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 258 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */ 259 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 260 #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */ 261 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 262 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 263 264 /* 265 * packed Y2xx indicate for each component, xx valid data occupy msb 266 * 16-xx padding occupy lsb 267 */ 268 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 269 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 270 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 271 272 /* 273 * packed Y4xx indicate for each component, xx valid data occupy msb 274 * 16-xx padding occupy lsb except Y410 275 */ 276 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 277 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 278 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 279 280 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 281 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 282 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 283 284 /* 285 * packed YCbCr420 2x2 tiled formats 286 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 287 */ 288 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 289 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 290 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 291 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 292 293 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 294 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 295 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 296 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 297 298 /* 299 * 1-plane YUV 4:2:0 300 * In these formats, the component ordering is specified (Y, followed by U 301 * then V), but the exact Linear layout is undefined. 302 * These formats can only be used with a non-Linear modifier. 303 */ 304 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 305 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 306 307 /* 308 * 2 plane RGB + A 309 * index 0 = RGB plane, same format as the corresponding non _A8 format has 310 * index 1 = A plane, [7:0] A 311 */ 312 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 313 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 314 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 315 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 316 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 317 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 318 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 319 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 320 321 /* 322 * 2 plane YCbCr 323 * index 0 = Y plane, [7:0] Y 324 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 325 * or 326 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 327 */ 328 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 329 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 330 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 331 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 332 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 333 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 334 /* 335 * 2 plane YCbCr 336 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 337 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 338 */ 339 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 340 #define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */ 341 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */ 342 343 /* 344 * 2 plane YCbCr MSB aligned 345 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 346 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 347 */ 348 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 349 350 /* 351 * 2 plane YCbCr MSB aligned 352 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 353 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 354 */ 355 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 356 357 /* 358 * 2 plane YCbCr MSB aligned 359 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 360 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 361 */ 362 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 363 364 /* 365 * 2 plane YCbCr MSB aligned 366 * index 0 = Y plane, [15:0] Y little endian 367 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 368 */ 369 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 370 371 /* 2 plane YCbCr420. 372 * 3 10 bit components and 2 padding bits packed into 4 bytes. 373 * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian 374 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian 375 */ 376 #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */ 377 378 /* 3 plane non-subsampled (444) YCbCr 379 * 16 bits per component, but only 10 bits are used and 6 bits are padded 380 * index 0: Y plane, [15:0] Y:x [10:6] little endian 381 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 382 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 383 */ 384 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 385 386 /* 3 plane non-subsampled (444) YCrCb 387 * 16 bits per component, but only 10 bits are used and 6 bits are padded 388 * index 0: Y plane, [15:0] Y:x [10:6] little endian 389 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 390 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 391 */ 392 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 393 394 /* 395 * 3 plane YCbCr LSB aligned 396 * In order to use these formats in a similar fashion to MSB aligned ones 397 * implementation can multiply the values by 2^6=64. For that reason the padding 398 * must only contain zeros. 399 * index 0 = Y plane, [15:0] z:Y [6:10] little endian 400 * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian 401 * index 2 = Cb plane, [15:0] z:Cb [6:10] little endian 402 */ 403 #define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ 404 #define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ 405 #define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */ 406 407 /* 408 * 3 plane YCbCr LSB aligned 409 * In order to use these formats in a similar fashion to MSB aligned ones 410 * implementation can multiply the values by 2^4=16. For that reason the padding 411 * must only contain zeros. 412 * index 0 = Y plane, [15:0] z:Y [4:12] little endian 413 * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian 414 * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian 415 */ 416 #define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ 417 #define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ 418 #define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */ 419 420 /* 421 * 3 plane YCbCr 422 * index 0 = Y plane, [15:0] Y little endian 423 * index 1 = Cr plane, [15:0] Cr little endian 424 * index 2 = Cb plane, [15:0] Cb little endian 425 */ 426 #define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ 427 #define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ 428 #define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */ 429 430 /* 431 * 3 plane YCbCr 432 * index 0: Y plane, [7:0] Y 433 * index 1: Cb plane, [7:0] Cb 434 * index 2: Cr plane, [7:0] Cr 435 * or 436 * index 1: Cr plane, [7:0] Cr 437 * index 2: Cb plane, [7:0] Cb 438 */ 439 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 440 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 441 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 442 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 443 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 444 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 445 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 446 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 447 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 448 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 449 450 451 /* 452 * Format Modifiers: 453 * 454 * Format modifiers describe, typically, a re-ordering or modification 455 * of the data in a plane of an FB. This can be used to express tiled/ 456 * swizzled formats, or compression, or a combination of the two. 457 * 458 * The upper 8 bits of the format modifier are a vendor-id as assigned 459 * below. The lower 56 bits are assigned as vendor sees fit. 460 */ 461 462 /* Vendor Ids: */ 463 #define DRM_FORMAT_MOD_VENDOR_NONE 0 464 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 465 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 466 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 467 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 468 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 469 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 470 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 471 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 472 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 473 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 474 #define DRM_FORMAT_MOD_VENDOR_MTK 0x0b 475 #define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c 476 477 /* add more to the end as needed */ 478 479 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 480 481 #define fourcc_mod_get_vendor(modifier) \ 482 (((modifier) >> 56) & 0xff) 483 484 #define fourcc_mod_is_vendor(modifier, vendor) \ 485 (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) 486 487 #define fourcc_mod_code(vendor, val) \ 488 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 489 490 /* 491 * Format Modifier tokens: 492 * 493 * When adding a new token please document the layout with a code comment, 494 * similar to the fourcc codes above. drm_fourcc.h is considered the 495 * authoritative source for all of these. 496 * 497 * Generic modifier names: 498 * 499 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 500 * for layouts which are common across multiple vendors. To preserve 501 * compatibility, in cases where a vendor-specific definition already exists and 502 * a generic name for it is desired, the common name is a purely symbolic alias 503 * and must use the same numerical value as the original definition. 504 * 505 * Note that generic names should only be used for modifiers which describe 506 * generic layouts (such as pixel re-ordering), which may have 507 * independently-developed support across multiple vendors. 508 * 509 * In future cases where a generic layout is identified before merging with a 510 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 511 * 'NONE' could be considered. This should only be for obvious, exceptional 512 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 513 * apply to a single vendor. 514 * 515 * Generic names should not be used for cases where multiple hardware vendors 516 * have implementations of the same standardised compression scheme (such as 517 * AFBC). In those cases, all implementations should use the same format 518 * modifier(s), reflecting the vendor of the standard. 519 */ 520 521 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 522 523 /* 524 * Invalid Modifier 525 * 526 * This modifier can be used as a sentinel to terminate the format modifiers 527 * list, or to initialize a variable with an invalid modifier. It might also be 528 * used to report an error back to userspace for certain APIs. 529 */ 530 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 531 532 /* 533 * Linear Layout 534 * 535 * Just plain linear layout. Note that this is different from no specifying any 536 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 537 * which tells the driver to also take driver-internal information into account 538 * and so might actually result in a tiled framebuffer. 539 */ 540 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 541 542 /* 543 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 544 * 545 * The "none" format modifier doesn't actually mean that the modifier is 546 * implicit, instead it means that the layout is linear. Whether modifiers are 547 * used is out-of-band information carried in an API-specific way (e.g. in a 548 * flag for drm_mode_fb_cmd2). 549 */ 550 #define DRM_FORMAT_MOD_NONE 0 551 552 /* Intel framebuffer modifiers */ 553 554 /* 555 * Intel X-tiling layout 556 * 557 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 558 * in row-major layout. Within the tile bytes are laid out row-major, with 559 * a platform-dependent stride. On top of that the memory can apply 560 * platform-depending swizzling of some higher address bits into bit6. 561 * 562 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 563 * On earlier platforms the is highly platforms specific and not useful for 564 * cross-driver sharing. It exists since on a given platform it does uniquely 565 * identify the layout in a simple way for i915-specific userspace, which 566 * facilitated conversion of userspace to modifiers. Additionally the exact 567 * format on some really old platforms is not known. 568 */ 569 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 570 571 /* 572 * Intel Y-tiling layout 573 * 574 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 575 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 576 * chunks column-major, with a platform-dependent height. On top of that the 577 * memory can apply platform-depending swizzling of some higher address bits 578 * into bit6. 579 * 580 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 581 * On earlier platforms the is highly platforms specific and not useful for 582 * cross-driver sharing. It exists since on a given platform it does uniquely 583 * identify the layout in a simple way for i915-specific userspace, which 584 * facilitated conversion of userspace to modifiers. Additionally the exact 585 * format on some really old platforms is not known. 586 */ 587 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 588 589 /* 590 * Intel Yf-tiling layout 591 * 592 * This is a tiled layout using 4Kb tiles in row-major layout. 593 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 594 * are arranged in four groups (two wide, two high) with column-major layout. 595 * Each group therefore consists out of four 256 byte units, which are also laid 596 * out as 2x2 column-major. 597 * 256 byte units are made out of four 64 byte blocks of pixels, producing 598 * either a square block or a 2:1 unit. 599 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 600 * in pixel depends on the pixel depth. 601 */ 602 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 603 604 /* 605 * Intel color control surface (CCS) for render compression 606 * 607 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 608 * The main surface will be plane index 0 and must be Y/Yf-tiled, 609 * the CCS will be plane index 1. 610 * 611 * Each CCS tile matches a 1024x512 pixel area of the main surface. 612 * To match certain aspects of the 3D hardware the CCS is 613 * considered to be made up of normal 128Bx32 Y tiles, Thus 614 * the CCS pitch must be specified in multiples of 128 bytes. 615 * 616 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 617 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 618 * But that fact is not relevant unless the memory is accessed 619 * directly. 620 */ 621 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 622 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 623 624 /* 625 * Intel color control surfaces (CCS) for Gen-12 render compression. 626 * 627 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 628 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 629 * main surface. In other words, 4 bits in CCS map to a main surface cache 630 * line pair. The main surface pitch is required to be a multiple of four 631 * Y-tile widths. 632 */ 633 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 634 635 /* 636 * Intel color control surfaces (CCS) for Gen-12 media compression 637 * 638 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 639 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 640 * main surface. In other words, 4 bits in CCS map to a main surface cache 641 * line pair. The main surface pitch is required to be a multiple of four 642 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 643 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 644 * planes 2 and 3 for the respective CCS. 645 */ 646 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 647 648 /* 649 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render 650 * compression. 651 * 652 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear 653 * and at index 1. The clear color is stored at index 2, and the pitch should 654 * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits 655 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 656 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 657 * the converted clear color of size 64 bits. The first 32 bits store the Lower 658 * Converted Clear Color value and the next 32 bits store the Higher Converted 659 * Clear Color value when applicable. The Converted Clear Color values are 660 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 661 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 662 * corresponds to an area of 4x1 tiles in the main surface. The main surface 663 * pitch is required to be a multiple of 4 tile widths. 664 */ 665 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) 666 667 /* 668 * Intel Tile 4 layout 669 * 670 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same 671 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It 672 * only differs from Tile Y at the 256B granularity in between. At this 673 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape 674 * of 64B x 8 rows. 675 */ 676 #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) 677 678 /* 679 * Intel color control surfaces (CCS) for DG2 render compression. 680 * 681 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 682 * outside of the GEM object in a reserved memory area dedicated for the 683 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 684 * main surface pitch is required to be a multiple of four Tile 4 widths. 685 */ 686 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10) 687 688 /* 689 * Intel color control surfaces (CCS) for DG2 media compression. 690 * 691 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 692 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 693 * 0 and 1, respectively. The CCS for all planes are stored outside of the 694 * GEM object in a reserved memory area dedicated for the storage of the 695 * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface 696 * pitch is required to be a multiple of four Tile 4 widths. 697 */ 698 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) 699 700 /* 701 * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. 702 * 703 * The main surface is Tile 4 and at plane index 0. The CCS data is stored 704 * outside of the GEM object in a reserved memory area dedicated for the 705 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The 706 * main surface pitch is required to be a multiple of four Tile 4 widths. The 707 * clear color is stored at plane index 1 and the pitch should be 64 bytes 708 * aligned. The format of the 256 bits of clear color data matches the one used 709 * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description 710 * for details. 711 */ 712 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) 713 714 /* 715 * Intel Color Control Surfaces (CCS) for display ver. 14 render compression. 716 * 717 * The main surface is tile4 and at plane index 0, the CCS is linear and 718 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 719 * main surface. In other words, 4 bits in CCS map to a main surface cache 720 * line pair. The main surface pitch is required to be a multiple of four 721 * tile4 widths. 722 */ 723 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13) 724 725 /* 726 * Intel Color Control Surfaces (CCS) for display ver. 14 media compression 727 * 728 * The main surface is tile4 and at plane index 0, the CCS is linear and 729 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 730 * main surface. In other words, 4 bits in CCS map to a main surface cache 731 * line pair. The main surface pitch is required to be a multiple of four 732 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the 733 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 734 * planes 2 and 3 for the respective CCS. 735 */ 736 #define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14) 737 738 /* 739 * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render 740 * compression. 741 * 742 * The main surface is tile4 and is at plane index 0 whereas CCS is linear 743 * and at index 1. The clear color is stored at index 2, and the pitch should 744 * be ignored. The clear color structure is 256 bits. The first 128 bits 745 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 746 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 747 * the converted clear color of size 64 bits. The first 32 bits store the Lower 748 * Converted Clear Color value and the next 32 bits store the Higher Converted 749 * Clear Color value when applicable. The Converted Clear Color values are 750 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 751 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 752 * corresponds to an area of 4x1 tiles in the main surface. The main surface 753 * pitch is required to be a multiple of 4 tile widths. 754 */ 755 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) 756 757 /* 758 * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression 759 * on integrated graphics 760 * 761 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 762 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 763 * 0 and 1, respectively. The CCS for all planes are stored outside of the 764 * GEM object in a reserved memory area dedicated for the storage of the 765 * CCS data for all compressible GEM objects. 766 */ 767 #define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16) 768 769 /* 770 * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression 771 * on discrete graphics 772 * 773 * The main surface is Tile 4 and at plane index 0. For semi-planar formats 774 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 775 * 0 and 1, respectively. The CCS for all planes are stored outside of the 776 * GEM object in a reserved memory area dedicated for the storage of the 777 * CCS data for all compressible GEM objects. The GEM object must be stored in 778 * contiguous memory with a size aligned to 64KB 779 */ 780 #define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17) 781 782 /* 783 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 784 * 785 * Macroblocks are laid in a Z-shape, and each pixel data is following the 786 * standard NV12 style. 787 * As for NV12, an image is the result of two frame buffers: one for Y, 788 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 789 * Alignment requirements are (for each buffer): 790 * - multiple of 128 pixels for the width 791 * - multiple of 32 pixels for the height 792 * 793 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 794 */ 795 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 796 797 /* 798 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 799 * 800 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 801 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 802 * they correspond to their 16x16 luma block. 803 */ 804 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 805 806 /* 807 * Qualcomm Compressed Format 808 * 809 * Refers to a compressed variant of the base format that is compressed. 810 * Implementation may be platform and base-format specific. 811 * 812 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 813 * Pixel data pitch/stride is aligned with macrotile width. 814 * Pixel data height is aligned with macrotile height. 815 * Entire pixel data buffer is aligned with 4k(bytes). 816 */ 817 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 818 819 /* 820 * Qualcomm Tiled Format 821 * 822 * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed. 823 * Implementation may be platform and base-format specific. 824 * 825 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 826 * Pixel data pitch/stride is aligned with macrotile width. 827 * Pixel data height is aligned with macrotile height. 828 * Entire pixel data buffer is aligned with 4k(bytes). 829 */ 830 #define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3) 831 832 /* 833 * Qualcomm Alternate Tiled Format 834 * 835 * Alternate tiled format typically only used within GMEM. 836 * Implementation may be platform and base-format specific. 837 */ 838 #define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2) 839 840 841 /* Vivante framebuffer modifiers */ 842 843 /* 844 * Vivante 4x4 tiling layout 845 * 846 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 847 * layout. 848 */ 849 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 850 851 /* 852 * Vivante 64x64 super-tiling layout 853 * 854 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 855 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 856 * major layout. 857 * 858 * For more information: see 859 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 860 */ 861 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 862 863 /* 864 * Vivante 4x4 tiling layout for dual-pipe 865 * 866 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 867 * different base address. Offsets from the base addresses are therefore halved 868 * compared to the non-split tiled layout. 869 */ 870 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 871 872 /* 873 * Vivante 64x64 super-tiling layout for dual-pipe 874 * 875 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 876 * starts at a different base address. Offsets from the base addresses are 877 * therefore halved compared to the non-split super-tiled layout. 878 */ 879 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 880 881 /* 882 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of 883 * the color buffer tiling modifiers defined above. When TS is present it's a 884 * separate buffer containing the clear/compression status of each tile. The 885 * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer 886 * tile size in bytes covered by one entry in the status buffer and s is the 887 * number of status bits per entry. 888 * We reserve the top 8 bits of the Vivante modifier space for tile status 889 * clear/compression modifiers, as future cores might add some more TS layout 890 * variations. 891 */ 892 #define VIVANTE_MOD_TS_64_4 (1ULL << 48) 893 #define VIVANTE_MOD_TS_64_2 (2ULL << 48) 894 #define VIVANTE_MOD_TS_128_4 (3ULL << 48) 895 #define VIVANTE_MOD_TS_256_4 (4ULL << 48) 896 #define VIVANTE_MOD_TS_MASK (0xfULL << 48) 897 898 /* 899 * Vivante compression modifiers. Those depend on a TS modifier being present 900 * as the TS bits get reinterpreted as compression tags instead of simple 901 * clear markers when compression is enabled. 902 */ 903 #define VIVANTE_MOD_COMP_DEC400 (1ULL << 52) 904 #define VIVANTE_MOD_COMP_MASK (0xfULL << 52) 905 906 /* Masking out the extension bits will yield the base modifier. */ 907 #define VIVANTE_MOD_EXT_MASK (VIVANTE_MOD_TS_MASK | \ 908 VIVANTE_MOD_COMP_MASK) 909 910 /* NVIDIA frame buffer modifiers */ 911 912 /* 913 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 914 * 915 * Pixels are arranged in simple tiles of 16 x 16 bytes. 916 */ 917 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 918 919 /* 920 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 921 * and Tegra GPUs starting with Tegra K1. 922 * 923 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 924 * based on the architecture generation. GOBs themselves are then arranged in 925 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 926 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 927 * a block depth or height of "4"). 928 * 929 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 930 * in full detail. 931 * 932 * Macro 933 * Bits Param Description 934 * ---- ----- ----------------------------------------------------------------- 935 * 936 * 3:0 h log2(height) of each block, in GOBs. Placed here for 937 * compatibility with the existing 938 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 939 * 940 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 941 * compatibility with the existing 942 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 943 * 944 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 945 * size). Must be zero. 946 * 947 * Note there is no log2(width) parameter. Some portions of the 948 * hardware support a block width of two gobs, but it is impractical 949 * to use due to lack of support elsewhere, and has no known 950 * benefits. 951 * 952 * 11:9 - Reserved (To support 2D-array textures with variable array stride 953 * in blocks, specified via log2(tile width in blocks)). Must be 954 * zero. 955 * 956 * 19:12 k Page Kind. This value directly maps to a field in the page 957 * tables of all GPUs >= NV50. It affects the exact layout of bits 958 * in memory and can be derived from the tuple 959 * 960 * (format, GPU model, compression type, samples per pixel) 961 * 962 * Where compression type is defined below. If GPU model were 963 * implied by the format modifier, format, or memory buffer, page 964 * kind would not need to be included in the modifier itself, but 965 * since the modifier should define the layout of the associated 966 * memory buffer independent from any device or other context, it 967 * must be included here. 968 * 969 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 970 * starting with Fermi GPUs. Additionally, the mapping between page 971 * kind and bit layout has changed at various points. 972 * 973 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 974 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 975 * 2 = Gob Height 8, Turing+ Page Kind mapping 976 * 3 = Reserved for future use. 977 * 978 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 979 * bit remapping step that occurs at an even lower level than the 980 * page kind and block linear swizzles. This causes the layout of 981 * surfaces mapped in those SOC's GPUs to be incompatible with the 982 * equivalent mapping on other GPUs in the same system. 983 * 984 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 985 * 1 = Desktop GPU and Tegra Xavier+ Layout 986 * 987 * 25:23 c Lossless Framebuffer Compression type. 988 * 989 * 0 = none 990 * 1 = ROP/3D, layout 1, exact compression format implied by Page 991 * Kind field 992 * 2 = ROP/3D, layout 2, exact compression format implied by Page 993 * Kind field 994 * 3 = CDE horizontal 995 * 4 = CDE vertical 996 * 5 = Reserved for future use 997 * 6 = Reserved for future use 998 * 7 = Reserved for future use 999 * 1000 * 55:25 - Reserved for future use. Must be zero. 1001 */ 1002 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 1003 fourcc_mod_code(NVIDIA, (0x10 | \ 1004 ((h) & 0xf) | \ 1005 (((k) & 0xff) << 12) | \ 1006 (((g) & 0x3) << 20) | \ 1007 (((s) & 0x1) << 22) | \ 1008 (((c) & 0x7) << 23))) 1009 1010 /* To grandfather in prior block linear format modifiers to the above layout, 1011 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 1012 * with block-linear layouts, is remapped within drivers to the value 0xfe, 1013 * which corresponds to the "generic" kind used for simple single-sample 1014 * uncompressed color formats on Fermi - Volta GPUs. 1015 */ 1016 static inline __u64 1017 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 1018 { 1019 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 1020 return modifier; 1021 else 1022 return modifier | (0xfe << 12); 1023 } 1024 1025 /* 1026 * 16Bx2 Block Linear layout, used by Tegra K1 and later 1027 * 1028 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 1029 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 1030 * 1031 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 1032 * 1033 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 1034 * Valid values are: 1035 * 1036 * 0 == ONE_GOB 1037 * 1 == TWO_GOBS 1038 * 2 == FOUR_GOBS 1039 * 3 == EIGHT_GOBS 1040 * 4 == SIXTEEN_GOBS 1041 * 5 == THIRTYTWO_GOBS 1042 * 1043 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 1044 * in full detail. 1045 */ 1046 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 1047 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 1048 1049 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 1050 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 1051 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 1052 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 1053 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 1054 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 1055 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 1056 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 1057 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 1058 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 1059 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 1060 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 1061 1062 /* 1063 * Some Broadcom modifiers take parameters, for example the number of 1064 * vertical lines in the image. Reserve the lower 32 bits for modifier 1065 * type, and the next 24 bits for parameters. Top 8 bits are the 1066 * vendor code. 1067 */ 1068 #define __fourcc_mod_broadcom_param_shift 8 1069 #define __fourcc_mod_broadcom_param_bits 48 1070 #define fourcc_mod_broadcom_code(val, params) \ 1071 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) 1072 #define fourcc_mod_broadcom_param(m) \ 1073 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 1074 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 1075 #define fourcc_mod_broadcom_mod(m) \ 1076 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 1077 __fourcc_mod_broadcom_param_shift)) 1078 1079 /* 1080 * Broadcom VC4 "T" format 1081 * 1082 * This is the primary layout that the V3D GPU can texture from (it 1083 * can't do linear). The T format has: 1084 * 1085 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 1086 * pixels at 32 bit depth. 1087 * 1088 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 1089 * 16x16 pixels). 1090 * 1091 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 1092 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 1093 * they're (TR, BR, BL, TL), where bottom left is start of memory. 1094 * 1095 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 1096 * tiles) or right-to-left (odd rows of 4k tiles). 1097 */ 1098 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 1099 1100 /* 1101 * Broadcom SAND format 1102 * 1103 * This is the native format that the H.264 codec block uses. For VC4 1104 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 1105 * 1106 * The image can be considered to be split into columns, and the 1107 * columns are placed consecutively into memory. The width of those 1108 * columns can be either 32, 64, 128, or 256 pixels, but in practice 1109 * only 128 pixel columns are used. 1110 * 1111 * The pitch between the start of each column is set to optimally 1112 * switch between SDRAM banks. This is passed as the number of lines 1113 * of column width in the modifier (we can't use the stride value due 1114 * to various core checks that look at it , so you should set the 1115 * stride to width*cpp). 1116 * 1117 * Note that the column height for this format modifier is the same 1118 * for all of the planes, assuming that each column contains both Y 1119 * and UV. Some SAND-using hardware stores UV in a separate tiled 1120 * image from Y to reduce the column height, which is not supported 1121 * with these modifiers. 1122 * 1123 * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also 1124 * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes 1125 * wide, but as this is a 10 bpp format that translates to 96 pixels. 1126 */ 1127 1128 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 1129 fourcc_mod_broadcom_code(2, v) 1130 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 1131 fourcc_mod_broadcom_code(3, v) 1132 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 1133 fourcc_mod_broadcom_code(4, v) 1134 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 1135 fourcc_mod_broadcom_code(5, v) 1136 1137 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 1138 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 1139 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 1140 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 1141 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 1142 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 1143 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 1144 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 1145 1146 /* Broadcom UIF format 1147 * 1148 * This is the common format for the current Broadcom multimedia 1149 * blocks, including V3D 3.x and newer, newer video codecs, and 1150 * displays. 1151 * 1152 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 1153 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 1154 * stored in columns, with padding between the columns to ensure that 1155 * moving from one column to the next doesn't hit the same SDRAM page 1156 * bank. 1157 * 1158 * To calculate the padding, it is assumed that each hardware block 1159 * and the software driving it knows the platform's SDRAM page size, 1160 * number of banks, and XOR address, and that it's identical between 1161 * all blocks using the format. This tiling modifier will use XOR as 1162 * necessary to reduce the padding. If a hardware block can't do XOR, 1163 * the assumption is that a no-XOR tiling modifier will be created. 1164 */ 1165 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 1166 1167 /* 1168 * Arm Framebuffer Compression (AFBC) modifiers 1169 * 1170 * AFBC is a proprietary lossless image compression protocol and format. 1171 * It provides fine-grained random access and minimizes the amount of data 1172 * transferred between IP blocks. 1173 * 1174 * AFBC has several features which may be supported and/or used, which are 1175 * represented using bits in the modifier. Not all combinations are valid, 1176 * and different devices or use-cases may support different combinations. 1177 * 1178 * Further information on the use of AFBC modifiers can be found in 1179 * Documentation/gpu/afbc.rst 1180 */ 1181 1182 /* 1183 * The top 4 bits (out of the 56 bits allotted for specifying vendor specific 1184 * modifiers) denote the category for modifiers. Currently we have three 1185 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of 1186 * sixteen different categories. 1187 */ 1188 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 1189 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 1190 1191 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 1192 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 1193 1194 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 1195 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 1196 1197 /* 1198 * AFBC superblock size 1199 * 1200 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 1201 * size (in pixels) must be aligned to a multiple of the superblock size. 1202 * Four lowest significant bits(LSBs) are reserved for block size. 1203 * 1204 * Where one superblock size is specified, it applies to all planes of the 1205 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 1206 * the first applies to the Luma plane and the second applies to the Chroma 1207 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 1208 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 1209 */ 1210 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 1211 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 1212 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 1213 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 1214 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 1215 1216 /* 1217 * AFBC lossless colorspace transform 1218 * 1219 * Indicates that the buffer makes use of the AFBC lossless colorspace 1220 * transform. 1221 */ 1222 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 1223 1224 /* 1225 * AFBC block-split 1226 * 1227 * Indicates that the payload of each superblock is split. The second 1228 * half of the payload is positioned at a predefined offset from the start 1229 * of the superblock payload. 1230 */ 1231 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 1232 1233 /* 1234 * AFBC sparse layout 1235 * 1236 * This flag indicates that the payload of each superblock must be stored at a 1237 * predefined position relative to the other superblocks in the same AFBC 1238 * buffer. This order is the same order used by the header buffer. In this mode 1239 * each superblock is given the same amount of space as an uncompressed 1240 * superblock of the particular format would require, rounding up to the next 1241 * multiple of 128 bytes in size. 1242 */ 1243 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 1244 1245 /* 1246 * AFBC copy-block restrict 1247 * 1248 * Buffers with this flag must obey the copy-block restriction. The restriction 1249 * is such that there are no copy-blocks referring across the border of 8x8 1250 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 1251 */ 1252 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 1253 1254 /* 1255 * AFBC tiled layout 1256 * 1257 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 1258 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 1259 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 1260 * larger bpp formats. The order between the tiles is scan line. 1261 * When the tiled layout is used, the buffer size (in pixels) must be aligned 1262 * to the tile size. 1263 */ 1264 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 1265 1266 /* 1267 * AFBC solid color blocks 1268 * 1269 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 1270 * can be reduced if a whole superblock is a single color. 1271 */ 1272 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 1273 1274 /* 1275 * AFBC double-buffer 1276 * 1277 * Indicates that the buffer is allocated in a layout safe for front-buffer 1278 * rendering. 1279 */ 1280 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 1281 1282 /* 1283 * AFBC buffer content hints 1284 * 1285 * Indicates that the buffer includes per-superblock content hints. 1286 */ 1287 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 1288 1289 /* AFBC uncompressed storage mode 1290 * 1291 * Indicates that the buffer is using AFBC uncompressed storage mode. 1292 * In this mode all superblock payloads in the buffer use the uncompressed 1293 * storage mode, which is usually only used for data which cannot be compressed. 1294 * The buffer layout is the same as for AFBC buffers without USM set, this only 1295 * affects the storage mode of the individual superblocks. Note that even a 1296 * buffer without USM set may use uncompressed storage mode for some or all 1297 * superblocks, USM just guarantees it for all. 1298 */ 1299 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 1300 1301 /* 1302 * Arm Fixed-Rate Compression (AFRC) modifiers 1303 * 1304 * AFRC is a proprietary fixed rate image compression protocol and format, 1305 * designed to provide guaranteed bandwidth and memory footprint 1306 * reductions in graphics and media use-cases. 1307 * 1308 * AFRC buffers consist of one or more planes, with the same components 1309 * and meaning as an uncompressed buffer using the same pixel format. 1310 * 1311 * Within each plane, the pixel/luma/chroma values are grouped into 1312 * "coding unit" blocks which are individually compressed to a 1313 * fixed size (in bytes). All coding units within a given plane of a buffer 1314 * store the same number of values, and have the same compressed size. 1315 * 1316 * The coding unit size is configurable, allowing different rates of compression. 1317 * 1318 * The start of each AFRC buffer plane must be aligned to an alignment granule which 1319 * depends on the coding unit size. 1320 * 1321 * Coding Unit Size Plane Alignment 1322 * ---------------- --------------- 1323 * 16 bytes 1024 bytes 1324 * 24 bytes 512 bytes 1325 * 32 bytes 2048 bytes 1326 * 1327 * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned 1328 * to a multiple of the paging tile dimensions. 1329 * The dimensions of each paging tile depend on whether the buffer is optimised for 1330 * scanline (SCAN layout) or rotated (ROT layout) access. 1331 * 1332 * Layout Paging Tile Width Paging Tile Height 1333 * ------ ----------------- ------------------ 1334 * SCAN 16 coding units 4 coding units 1335 * ROT 8 coding units 8 coding units 1336 * 1337 * The dimensions of each coding unit depend on the number of components 1338 * in the compressed plane and whether the buffer is optimised for 1339 * scanline (SCAN layout) or rotated (ROT layout) access. 1340 * 1341 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height 1342 * ----------------------------- --------- ----------------- ------------------ 1343 * 1 SCAN 16 samples 4 samples 1344 * Example: 16x4 luma samples in a 'Y' plane 1345 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1346 * ----------------------------- --------- ----------------- ------------------ 1347 * 1 ROT 8 samples 8 samples 1348 * Example: 8x8 luma samples in a 'Y' plane 1349 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer 1350 * ----------------------------- --------- ----------------- ------------------ 1351 * 2 DONT CARE 8 samples 4 samples 1352 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer 1353 * ----------------------------- --------- ----------------- ------------------ 1354 * 3 DONT CARE 4 samples 4 samples 1355 * Example: 4x4 pixels in an RGB buffer without alpha 1356 * ----------------------------- --------- ----------------- ------------------ 1357 * 4 DONT CARE 4 samples 4 samples 1358 * Example: 4x4 pixels in an RGB buffer with alpha 1359 */ 1360 1361 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 1362 1363 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ 1364 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) 1365 1366 /* 1367 * AFRC coding unit size modifier. 1368 * 1369 * Indicates the number of bytes used to store each compressed coding unit for 1370 * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance 1371 * is the same for both Cb and Cr, which may be stored in separate planes. 1372 * 1373 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store 1374 * each compressed coding unit in the first plane of the buffer. For RGBA buffers 1375 * this is the only plane, while for semi-planar and fully-planar YUV buffers, 1376 * this corresponds to the luma plane. 1377 * 1378 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store 1379 * each compressed coding unit in the second and third planes in the buffer. 1380 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). 1381 * 1382 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified 1383 * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. 1384 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and 1385 * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. 1386 */ 1387 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf 1388 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) 1389 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) 1390 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) 1391 1392 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) 1393 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) 1394 1395 /* 1396 * AFRC scanline memory layout. 1397 * 1398 * Indicates if the buffer uses the scanline-optimised layout 1399 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. 1400 * The memory layout is the same for all planes. 1401 */ 1402 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) 1403 1404 /* 1405 * Arm 16x16 Block U-Interleaved modifier 1406 * 1407 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 1408 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 1409 * in the block are reordered. 1410 */ 1411 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1412 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1413 1414 /* 1415 * Allwinner tiled modifier 1416 * 1417 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1418 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1419 * planes. 1420 * 1421 * With this tiling, the luminance samples are disposed in tiles representing 1422 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1423 * The pixel order in each tile is linear and the tiles are disposed linearly, 1424 * both in row-major order. 1425 */ 1426 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1427 1428 /* 1429 * Amlogic Video Framebuffer Compression modifiers 1430 * 1431 * Amlogic uses a proprietary lossless image compression protocol and format 1432 * for their hardware video codec accelerators, either video decoders or 1433 * video input encoders. 1434 * 1435 * It considerably reduces memory bandwidth while writing and reading 1436 * frames in memory. 1437 * 1438 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1439 * per component YCbCr 420, single plane : 1440 * - DRM_FORMAT_YUV420_8BIT 1441 * - DRM_FORMAT_YUV420_10BIT 1442 * 1443 * The first 8 bits of the mode defines the layout, then the following 8 bits 1444 * defines the options changing the layout. 1445 * 1446 * Not all combinations are valid, and different SoCs may support different 1447 * combinations of layout and options. 1448 */ 1449 #define __fourcc_mod_amlogic_layout_mask 0xff 1450 #define __fourcc_mod_amlogic_options_shift 8 1451 #define __fourcc_mod_amlogic_options_mask 0xff 1452 1453 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1454 fourcc_mod_code(AMLOGIC, \ 1455 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1456 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1457 << __fourcc_mod_amlogic_options_shift)) 1458 1459 /* Amlogic FBC Layouts */ 1460 1461 /* 1462 * Amlogic FBC Basic Layout 1463 * 1464 * The basic layout is composed of: 1465 * - a body content organized in 64x32 superblocks with 4096 bytes per 1466 * superblock in default mode. 1467 * - a 32 bytes per 128x64 header block 1468 * 1469 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1470 */ 1471 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1472 1473 /* 1474 * Amlogic FBC Scatter Memory layout 1475 * 1476 * Indicates the header contains IOMMU references to the compressed 1477 * frames content to optimize memory access and layout. 1478 * 1479 * In this mode, only the header memory address is needed, thus the 1480 * content memory organization is tied to the current producer 1481 * execution and cannot be saved/dumped neither transferrable between 1482 * Amlogic SoCs supporting this modifier. 1483 * 1484 * Due to the nature of the layout, these buffers are not expected to 1485 * be accessible by the user-space clients, but only accessible by the 1486 * hardware producers and consumers. 1487 * 1488 * The user-space clients should expect a failure while trying to mmap 1489 * the DMA-BUF handle returned by the producer. 1490 */ 1491 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1492 1493 /* Amlogic FBC Layout Options Bit Mask */ 1494 1495 /* 1496 * Amlogic FBC Memory Saving mode 1497 * 1498 * Indicates the storage is packed when pixel size is multiple of word 1499 * boundaries, i.e. 8bit should be stored in this mode to save allocation 1500 * memory. 1501 * 1502 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1503 * the basic layout and 3200 bytes per 64x32 superblock combined with 1504 * the scatter layout. 1505 */ 1506 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1507 1508 /* MediaTek modifiers 1509 * Bits Parameter Notes 1510 * ----- ------------------------ --------------------------------------------- 1511 * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_* 1512 * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_* 1513 * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_* 1514 * 1515 */ 1516 1517 #define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags) 1518 1519 /* 1520 * MediaTek Tiled Modifier 1521 * The lowest 8 bits of the modifier is used to specify the tiling 1522 * layout. Only the 16L_32S tiling is used for now, but we define an 1523 * "untiled" version and leave room for future expansion. 1524 */ 1525 #define MTK_FMT_MOD_TILE_MASK 0xf 1526 #define MTK_FMT_MOD_TILE_NONE 0x0 1527 #define MTK_FMT_MOD_TILE_16L32S 0x1 1528 1529 /* 1530 * Bits 8-15 specify compression options 1531 */ 1532 #define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8) 1533 #define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8) 1534 #define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8) 1535 1536 /* 1537 * Bits 16-23 specify how the bits of 10 bit formats are 1538 * stored out in memory 1539 */ 1540 #define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16) 1541 #define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16) 1542 #define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16) 1543 #define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16) 1544 1545 /* alias for the most common tiling format */ 1546 #define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S) 1547 1548 /* 1549 * Apple GPU-tiled layouts. 1550 * 1551 * Apple GPUs support nonlinear tilings with optional lossless compression. 1552 * 1553 * GPU-tiled images are divided into 16KiB tiles: 1554 * 1555 * Bytes per pixel Tile size 1556 * --------------- --------- 1557 * 1 128x128 1558 * 2 128x64 1559 * 4 64x64 1560 * 8 64x32 1561 * 16 32x32 1562 * 1563 * Tiles are raster-order. Pixels within a tile are interleaved (Morton order). 1564 * 1565 * Compressed images pad the body to 128-bytes and are immediately followed by a 1566 * metadata section. The metadata section rounds the image dimensions to 1567 * powers-of-two and contains 8 bytes for each 16x16 compression subtile. 1568 * Subtiles are interleaved (Morton order). 1569 * 1570 * All images are 128-byte aligned. 1571 * 1572 * These layouts fundamentally do not have meaningful strides. No matter how we 1573 * specify strides for these layouts, userspace unaware of Apple image layouts 1574 * will be unable to use correctly the specified stride for any purpose. 1575 * Userspace aware of the image layouts do not use strides. The most "correct" 1576 * convention would be setting the image stride to 0. Unfortunately, some 1577 * software assumes the stride is at least (width * bytes per pixel). We 1578 * therefore require that stride equals (width * bytes per pixel). Since the 1579 * stride is arbitrary here, we pick the simplest convention. 1580 * 1581 * Although containing two sections, compressed image layouts are treated in 1582 * software as a single plane. This is modelled after AFBC, a similar 1583 * scheme. Attempting to separate the sections to be "explicit" in DRM would 1584 * only generate more confusion, as software does not treat the image this way. 1585 * 1586 * For detailed information on the hardware image layouts, see 1587 * https://docs.mesa3d.org/drivers/asahi.html#image-layouts 1588 */ 1589 #define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1) 1590 #define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2) 1591 1592 /* 1593 * AMD modifiers 1594 * 1595 * Memory layout: 1596 * 1597 * without DCC: 1598 * - main surface 1599 * 1600 * with DCC & without DCC_RETILE: 1601 * - main surface in plane 0 1602 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1603 * 1604 * with DCC & DCC_RETILE: 1605 * - main surface in plane 0 1606 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1607 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1608 * 1609 * For multi-plane formats the above surfaces get merged into one plane for 1610 * each format plane, based on the required alignment only. 1611 * 1612 * Bits Parameter Notes 1613 * ----- ------------------------ --------------------------------------------- 1614 * 1615 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1616 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1617 * 13 DCC 1618 * 14 DCC_RETILE 1619 * 15 DCC_PIPE_ALIGN 1620 * 16 DCC_INDEPENDENT_64B 1621 * 17 DCC_INDEPENDENT_128B 1622 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1623 * 20 DCC_CONSTANT_ENCODE 1624 * 23:21 PIPE_XOR_BITS Only for some chips 1625 * 26:24 BANK_XOR_BITS Only for some chips 1626 * 29:27 PACKERS Only for some chips 1627 * 32:30 RB Only for some chips 1628 * 35:33 PIPE Only for some chips 1629 * 55:36 - Reserved for future use, must be zero 1630 */ 1631 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1632 1633 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1634 1635 /* Reserve 0 for GFX8 and older */ 1636 #define AMD_FMT_MOD_TILE_VER_GFX9 1 1637 #define AMD_FMT_MOD_TILE_VER_GFX10 2 1638 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1639 #define AMD_FMT_MOD_TILE_VER_GFX11 4 1640 #define AMD_FMT_MOD_TILE_VER_GFX12 5 1641 1642 /* 1643 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1644 * version. 1645 */ 1646 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1647 1648 /* 1649 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1650 * GFX9 as canonical version. 1651 * 1652 * 64K_D_2D on GFX12 is identical to 64K_D on GFX11. 1653 */ 1654 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1655 #define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22 1656 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1657 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1658 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1659 #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 1660 1661 /* Gfx12 swizzle modes: 1662 * 0 - LINEAR 1663 * 1 - 256B_2D - 2D block dimensions 1664 * 2 - 4KB_2D 1665 * 3 - 64KB_2D 1666 * 4 - 256KB_2D 1667 * 5 - 4KB_3D - 3D block dimensions 1668 * 6 - 64KB_3D 1669 * 7 - 256KB_3D 1670 */ 1671 #define AMD_FMT_MOD_TILE_GFX12_256B_2D 1 1672 #define AMD_FMT_MOD_TILE_GFX12_4K_2D 2 1673 #define AMD_FMT_MOD_TILE_GFX12_64K_2D 3 1674 #define AMD_FMT_MOD_TILE_GFX12_256K_2D 4 1675 1676 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 1677 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 1678 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 1679 1680 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1681 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1682 #define AMD_FMT_MOD_TILE_SHIFT 8 1683 #define AMD_FMT_MOD_TILE_MASK 0x1F 1684 1685 /* Whether DCC compression is enabled. */ 1686 #define AMD_FMT_MOD_DCC_SHIFT 13 1687 #define AMD_FMT_MOD_DCC_MASK 0x1 1688 1689 /* 1690 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1691 * one which is not-aligned. 1692 */ 1693 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1694 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1695 1696 /* Only set if DCC_RETILE = false */ 1697 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1698 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1699 1700 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1701 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1702 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1703 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1704 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1705 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1706 1707 /* 1708 * DCC supports embedding some clear colors directly in the DCC surface. 1709 * However, on older GPUs the rendering HW ignores the embedded clear color 1710 * and prefers the driver provided color. This necessitates doing a fastclear 1711 * eliminate operation before a process transfers control. 1712 * 1713 * If this bit is set that means the fastclear eliminate is not needed for these 1714 * embeddable colors. 1715 */ 1716 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1717 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1718 1719 /* 1720 * The below fields are for accounting for per GPU differences. These are only 1721 * relevant for GFX9 and later and if the tile field is *_X/_T. 1722 * 1723 * PIPE_XOR_BITS = always needed 1724 * BANK_XOR_BITS = only for TILE_VER_GFX9 1725 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1726 * RB = only for TILE_VER_GFX9 & DCC 1727 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1728 */ 1729 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1730 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1731 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1732 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1733 #define AMD_FMT_MOD_PACKERS_SHIFT 27 1734 #define AMD_FMT_MOD_PACKERS_MASK 0x7 1735 #define AMD_FMT_MOD_RB_SHIFT 30 1736 #define AMD_FMT_MOD_RB_MASK 0x7 1737 #define AMD_FMT_MOD_PIPE_SHIFT 33 1738 #define AMD_FMT_MOD_PIPE_MASK 0x7 1739 1740 #define AMD_FMT_MOD_SET(field, value) \ 1741 ((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT) 1742 #define AMD_FMT_MOD_GET(field, value) \ 1743 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1744 #define AMD_FMT_MOD_CLEAR(field) \ 1745 (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1746 1747 #if defined(__cplusplus) 1748 } 1749 #endif 1750 1751 #endif /* DRM_FOURCC_H */ 1752