1 /** 2 * \file drm.h 3 * Header for the Direct Rendering Manager 4 * 5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 6 * 7 * \par Acknowledgments: 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9 */ 10 11 /* 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14 * All rights reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a 17 * copy of this software and associated documentation files (the "Software"), 18 * to deal in the Software without restriction, including without limitation 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * and/or sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the next 24 * paragraph) shall be included in all copies or substantial portions of the 25 * Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 */ 35 36 #ifndef _DRM_H_ 37 #define _DRM_H_ 38 39 #if defined(__KERNEL__) 40 41 #include <linux/types.h> 42 #include <asm/ioctl.h> 43 typedef unsigned int drm_handle_t; 44 45 #elif defined(__linux__) 46 47 #include <linux/types.h> 48 #include <asm/ioctl.h> 49 typedef unsigned int drm_handle_t; 50 51 #else /* One of the BSDs */ 52 53 #include <sys/ioccom.h> 54 #include <sys/types.h> 55 typedef int8_t __s8; 56 typedef uint8_t __u8; 57 typedef int16_t __s16; 58 typedef uint16_t __u16; 59 typedef int32_t __s32; 60 typedef uint32_t __u32; 61 typedef int64_t __s64; 62 typedef uint64_t __u64; 63 typedef size_t __kernel_size_t; 64 typedef unsigned long drm_handle_t; 65 66 #endif 67 68 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 69 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 70 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 71 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 72 73 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 74 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 75 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 76 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 77 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 78 79 typedef unsigned int drm_context_t; 80 typedef unsigned int drm_drawable_t; 81 typedef unsigned int drm_magic_t; 82 83 /** 84 * Cliprect. 85 * 86 * \warning: If you change this structure, make sure you change 87 * XF86DRIClipRectRec in the server as well 88 * 89 * \note KW: Actually it's illegal to change either for 90 * backwards-compatibility reasons. 91 */ 92 struct drm_clip_rect { 93 unsigned short x1; 94 unsigned short y1; 95 unsigned short x2; 96 unsigned short y2; 97 }; 98 99 /** 100 * Drawable information. 101 */ 102 struct drm_drawable_info { 103 unsigned int num_rects; 104 struct drm_clip_rect *rects; 105 }; 106 107 /** 108 * Texture region, 109 */ 110 struct drm_tex_region { 111 unsigned char next; 112 unsigned char prev; 113 unsigned char in_use; 114 unsigned char padding; 115 unsigned int age; 116 }; 117 118 /** 119 * Hardware lock. 120 * 121 * The lock structure is a simple cache-line aligned integer. To avoid 122 * processor bus contention on a multiprocessor system, there should not be any 123 * other data stored in the same cache line. 124 */ 125 struct drm_hw_lock { 126 __volatile__ unsigned int lock; /**< lock variable */ 127 char padding[60]; /**< Pad to cache line */ 128 }; 129 130 /** 131 * DRM_IOCTL_VERSION ioctl argument type. 132 * 133 * \sa drmGetVersion(). 134 */ 135 struct drm_version { 136 int version_major; /**< Major version */ 137 int version_minor; /**< Minor version */ 138 int version_patchlevel; /**< Patch level */ 139 __kernel_size_t name_len; /**< Length of name buffer */ 140 char __user *name; /**< Name of driver */ 141 __kernel_size_t date_len; /**< Length of date buffer */ 142 char __user *date; /**< User-space buffer to hold date */ 143 __kernel_size_t desc_len; /**< Length of desc buffer */ 144 char __user *desc; /**< User-space buffer to hold desc */ 145 }; 146 147 /** 148 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 149 * 150 * \sa drmGetBusid() and drmSetBusId(). 151 */ 152 struct drm_unique { 153 __kernel_size_t unique_len; /**< Length of unique */ 154 char __user *unique; /**< Unique name for driver instantiation */ 155 }; 156 157 struct drm_list { 158 int count; /**< Length of user-space structures */ 159 struct drm_version __user *version; 160 }; 161 162 struct drm_block { 163 int unused; 164 }; 165 166 /** 167 * DRM_IOCTL_CONTROL ioctl argument type. 168 * 169 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 170 */ 171 struct drm_control { 172 enum { 173 DRM_ADD_COMMAND, 174 DRM_RM_COMMAND, 175 DRM_INST_HANDLER, 176 DRM_UNINST_HANDLER 177 } func; 178 int irq; 179 }; 180 181 /** 182 * Type of memory to map. 183 */ 184 enum drm_map_type { 185 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 186 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 187 _DRM_SHM = 2, /**< shared, cached */ 188 _DRM_AGP = 3, /**< AGP/GART */ 189 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 190 _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ 191 }; 192 193 /** 194 * Memory mapping flags. 195 */ 196 enum drm_map_flags { 197 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 198 _DRM_READ_ONLY = 0x02, 199 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 200 _DRM_KERNEL = 0x08, /**< kernel requires access */ 201 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 202 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 203 _DRM_REMOVABLE = 0x40, /**< Removable mapping */ 204 _DRM_DRIVER = 0x80 /**< Managed by driver */ 205 }; 206 207 struct drm_ctx_priv_map { 208 unsigned int ctx_id; /**< Context requesting private mapping */ 209 void *handle; /**< Handle of map */ 210 }; 211 212 /** 213 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 214 * argument type. 215 * 216 * \sa drmAddMap(). 217 */ 218 struct drm_map { 219 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 220 unsigned long size; /**< Requested physical size (bytes) */ 221 enum drm_map_type type; /**< Type of memory to map */ 222 enum drm_map_flags flags; /**< Flags */ 223 void *handle; /**< User-space: "Handle" to pass to mmap() */ 224 /**< Kernel-space: kernel-virtual address */ 225 int mtrr; /**< MTRR slot used */ 226 /* Private data */ 227 }; 228 229 /** 230 * DRM_IOCTL_GET_CLIENT ioctl argument type. 231 */ 232 struct drm_client { 233 int idx; /**< Which client desired? */ 234 int auth; /**< Is client authenticated? */ 235 unsigned long pid; /**< Process ID */ 236 unsigned long uid; /**< User ID */ 237 unsigned long magic; /**< Magic */ 238 unsigned long iocs; /**< Ioctl count */ 239 }; 240 241 enum drm_stat_type { 242 _DRM_STAT_LOCK, 243 _DRM_STAT_OPENS, 244 _DRM_STAT_CLOSES, 245 _DRM_STAT_IOCTLS, 246 _DRM_STAT_LOCKS, 247 _DRM_STAT_UNLOCKS, 248 _DRM_STAT_VALUE, /**< Generic value */ 249 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 250 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 251 252 _DRM_STAT_IRQ, /**< IRQ */ 253 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 254 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 255 _DRM_STAT_DMA, /**< DMA */ 256 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 257 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 258 /* Add to the *END* of the list */ 259 }; 260 261 /** 262 * DRM_IOCTL_GET_STATS ioctl argument type. 263 */ 264 struct drm_stats { 265 unsigned long count; 266 struct { 267 unsigned long value; 268 enum drm_stat_type type; 269 } data[15]; 270 }; 271 272 /** 273 * Hardware locking flags. 274 */ 275 enum drm_lock_flags { 276 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 277 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 278 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 279 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 280 /* These *HALT* flags aren't supported yet 281 -- they will be used to support the 282 full-screen DGA-like mode. */ 283 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 284 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 285 }; 286 287 /** 288 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 289 * 290 * \sa drmGetLock() and drmUnlock(). 291 */ 292 struct drm_lock { 293 int context; 294 enum drm_lock_flags flags; 295 }; 296 297 /** 298 * DMA flags 299 * 300 * \warning 301 * These values \e must match xf86drm.h. 302 * 303 * \sa drm_dma. 304 */ 305 enum drm_dma_flags { 306 /* Flags for DMA buffer dispatch */ 307 _DRM_DMA_BLOCK = 0x01, /**< 308 * Block until buffer dispatched. 309 * 310 * \note The buffer may not yet have 311 * been processed by the hardware -- 312 * getting a hardware lock with the 313 * hardware quiescent will ensure 314 * that the buffer has been 315 * processed. 316 */ 317 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 318 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 319 320 /* Flags for DMA buffer request */ 321 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 322 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 323 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 324 }; 325 326 /** 327 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 328 * 329 * \sa drmAddBufs(). 330 */ 331 struct drm_buf_desc { 332 int count; /**< Number of buffers of this size */ 333 int size; /**< Size in bytes */ 334 int low_mark; /**< Low water mark */ 335 int high_mark; /**< High water mark */ 336 enum { 337 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 338 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 339 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 340 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 341 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 342 } flags; 343 unsigned long agp_start; /**< 344 * Start address of where the AGP buffers are 345 * in the AGP aperture 346 */ 347 }; 348 349 /** 350 * DRM_IOCTL_INFO_BUFS ioctl argument type. 351 */ 352 struct drm_buf_info { 353 int count; /**< Entries in list */ 354 struct drm_buf_desc __user *list; 355 }; 356 357 /** 358 * DRM_IOCTL_FREE_BUFS ioctl argument type. 359 */ 360 struct drm_buf_free { 361 int count; 362 int __user *list; 363 }; 364 365 /** 366 * Buffer information 367 * 368 * \sa drm_buf_map. 369 */ 370 struct drm_buf_pub { 371 int idx; /**< Index into the master buffer list */ 372 int total; /**< Buffer size */ 373 int used; /**< Amount of buffer in use (for DMA) */ 374 void __user *address; /**< Address of buffer */ 375 }; 376 377 /** 378 * DRM_IOCTL_MAP_BUFS ioctl argument type. 379 */ 380 struct drm_buf_map { 381 int count; /**< Length of the buffer list */ 382 #ifdef __cplusplus 383 void __user *virt; 384 #else 385 void __user *virtual; /**< Mmap'd area in user-virtual */ 386 #endif 387 struct drm_buf_pub __user *list; /**< Buffer information */ 388 }; 389 390 /** 391 * DRM_IOCTL_DMA ioctl argument type. 392 * 393 * Indices here refer to the offset into the buffer list in drm_buf_get. 394 * 395 * \sa drmDMA(). 396 */ 397 struct drm_dma { 398 int context; /**< Context handle */ 399 int send_count; /**< Number of buffers to send */ 400 int __user *send_indices; /**< List of handles to buffers */ 401 int __user *send_sizes; /**< Lengths of data to send */ 402 enum drm_dma_flags flags; /**< Flags */ 403 int request_count; /**< Number of buffers requested */ 404 int request_size; /**< Desired size for buffers */ 405 int __user *request_indices; /**< Buffer information */ 406 int __user *request_sizes; 407 int granted_count; /**< Number of buffers granted */ 408 }; 409 410 enum drm_ctx_flags { 411 _DRM_CONTEXT_PRESERVED = 0x01, 412 _DRM_CONTEXT_2DONLY = 0x02 413 }; 414 415 /** 416 * DRM_IOCTL_ADD_CTX ioctl argument type. 417 * 418 * \sa drmCreateContext() and drmDestroyContext(). 419 */ 420 struct drm_ctx { 421 drm_context_t handle; 422 enum drm_ctx_flags flags; 423 }; 424 425 /** 426 * DRM_IOCTL_RES_CTX ioctl argument type. 427 */ 428 struct drm_ctx_res { 429 int count; 430 struct drm_ctx __user *contexts; 431 }; 432 433 /** 434 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 435 */ 436 struct drm_draw { 437 drm_drawable_t handle; 438 }; 439 440 /** 441 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 442 */ 443 typedef enum { 444 DRM_DRAWABLE_CLIPRECTS 445 } drm_drawable_info_type_t; 446 447 struct drm_update_draw { 448 drm_drawable_t handle; 449 unsigned int type; 450 unsigned int num; 451 unsigned long long data; 452 }; 453 454 /** 455 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 456 */ 457 struct drm_auth { 458 drm_magic_t magic; 459 }; 460 461 /** 462 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 463 * 464 * \sa drmGetInterruptFromBusID(). 465 */ 466 struct drm_irq_busid { 467 int irq; /**< IRQ number */ 468 int busnum; /**< bus number */ 469 int devnum; /**< device number */ 470 int funcnum; /**< function number */ 471 }; 472 473 enum drm_vblank_seq_type { 474 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 475 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 476 /* bits 1-6 are reserved for high crtcs */ 477 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, 478 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 479 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 480 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 481 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 482 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ 483 }; 484 #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 485 486 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 487 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ 488 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) 489 490 struct drm_wait_vblank_request { 491 enum drm_vblank_seq_type type; 492 unsigned int sequence; 493 unsigned long signal; 494 }; 495 496 struct drm_wait_vblank_reply { 497 enum drm_vblank_seq_type type; 498 unsigned int sequence; 499 long tval_sec; 500 long tval_usec; 501 }; 502 503 /** 504 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 505 * 506 * \sa drmWaitVBlank(). 507 */ 508 union drm_wait_vblank { 509 struct drm_wait_vblank_request request; 510 struct drm_wait_vblank_reply reply; 511 }; 512 513 #define _DRM_PRE_MODESET 1 514 #define _DRM_POST_MODESET 2 515 516 /** 517 * DRM_IOCTL_MODESET_CTL ioctl argument type 518 * 519 * \sa drmModesetCtl(). 520 */ 521 struct drm_modeset_ctl { 522 __u32 crtc; 523 __u32 cmd; 524 }; 525 526 /** 527 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 528 * 529 * \sa drmAgpEnable(). 530 */ 531 struct drm_agp_mode { 532 unsigned long mode; /**< AGP mode */ 533 }; 534 535 /** 536 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 537 * 538 * \sa drmAgpAlloc() and drmAgpFree(). 539 */ 540 struct drm_agp_buffer { 541 unsigned long size; /**< In bytes -- will round to page boundary */ 542 unsigned long handle; /**< Used for binding / unbinding */ 543 unsigned long type; /**< Type of memory to allocate */ 544 unsigned long physical; /**< Physical used by i810 */ 545 }; 546 547 /** 548 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 549 * 550 * \sa drmAgpBind() and drmAgpUnbind(). 551 */ 552 struct drm_agp_binding { 553 unsigned long handle; /**< From drm_agp_buffer */ 554 unsigned long offset; /**< In bytes -- will round to page boundary */ 555 }; 556 557 /** 558 * DRM_IOCTL_AGP_INFO ioctl argument type. 559 * 560 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 561 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 562 * drmAgpVendorId() and drmAgpDeviceId(). 563 */ 564 struct drm_agp_info { 565 int agp_version_major; 566 int agp_version_minor; 567 unsigned long mode; 568 unsigned long aperture_base; /* physical address */ 569 unsigned long aperture_size; /* bytes */ 570 unsigned long memory_allowed; /* bytes */ 571 unsigned long memory_used; 572 573 /* PCI information */ 574 unsigned short id_vendor; 575 unsigned short id_device; 576 }; 577 578 /** 579 * DRM_IOCTL_SG_ALLOC ioctl argument type. 580 */ 581 struct drm_scatter_gather { 582 unsigned long size; /**< In bytes -- will round to page boundary */ 583 unsigned long handle; /**< Used for mapping / unmapping */ 584 }; 585 586 /** 587 * DRM_IOCTL_SET_VERSION ioctl argument type. 588 */ 589 struct drm_set_version { 590 int drm_di_major; 591 int drm_di_minor; 592 int drm_dd_major; 593 int drm_dd_minor; 594 }; 595 596 /** DRM_IOCTL_GEM_CLOSE ioctl argument type */ 597 struct drm_gem_close { 598 /** Handle of the object to be closed. */ 599 __u32 handle; 600 __u32 pad; 601 }; 602 603 /** DRM_IOCTL_GEM_FLINK ioctl argument type */ 604 struct drm_gem_flink { 605 /** Handle for the object being named */ 606 __u32 handle; 607 608 /** Returned global name */ 609 __u32 name; 610 }; 611 612 /** DRM_IOCTL_GEM_OPEN ioctl argument type */ 613 struct drm_gem_open { 614 /** Name of object being opened */ 615 __u32 name; 616 617 /** Returned handle for the object */ 618 __u32 handle; 619 620 /** Returned size of the object */ 621 __u64 size; 622 }; 623 624 #define DRM_CAP_DUMB_BUFFER 0x1 625 #define DRM_CAP_VBLANK_HIGH_CRTC 0x2 626 #define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 627 #define DRM_CAP_DUMB_PREFER_SHADOW 0x4 628 #define DRM_CAP_PRIME 0x5 629 #define DRM_PRIME_CAP_IMPORT 0x1 630 #define DRM_PRIME_CAP_EXPORT 0x2 631 #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 632 #define DRM_CAP_ASYNC_PAGE_FLIP 0x7 633 /* 634 * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight 635 * combination for the hardware cursor. The intention is that a hardware 636 * agnostic userspace can query a cursor plane size to use. 637 * 638 * Note that the cross-driver contract is to merely return a valid size; 639 * drivers are free to attach another meaning on top, eg. i915 returns the 640 * maximum plane size. 641 */ 642 #define DRM_CAP_CURSOR_WIDTH 0x8 643 #define DRM_CAP_CURSOR_HEIGHT 0x9 644 #define DRM_CAP_ADDFB2_MODIFIERS 0x10 645 646 /** DRM_IOCTL_GET_CAP ioctl argument type */ 647 struct drm_get_cap { 648 __u64 capability; 649 __u64 value; 650 }; 651 652 /** 653 * DRM_CLIENT_CAP_STEREO_3D 654 * 655 * if set to 1, the DRM core will expose the stereo 3D capabilities of the 656 * monitor by advertising the supported 3D layouts in the flags of struct 657 * drm_mode_modeinfo. 658 */ 659 #define DRM_CLIENT_CAP_STEREO_3D 1 660 661 /** 662 * DRM_CLIENT_CAP_UNIVERSAL_PLANES 663 * 664 * If set to 1, the DRM core will expose all planes (overlay, primary, and 665 * cursor) to userspace. 666 */ 667 #define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 668 669 /** 670 * DRM_CLIENT_CAP_ATOMIC 671 * 672 * If set to 1, the DRM core will expose atomic properties to userspace 673 */ 674 #define DRM_CLIENT_CAP_ATOMIC 3 675 676 /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ 677 struct drm_set_client_cap { 678 __u64 capability; 679 __u64 value; 680 }; 681 682 #define DRM_RDWR O_RDWR 683 #define DRM_CLOEXEC O_CLOEXEC 684 struct drm_prime_handle { 685 __u32 handle; 686 687 /** Flags.. only applicable for handle->fd */ 688 __u32 flags; 689 690 /** Returned dmabuf file descriptor */ 691 __s32 fd; 692 }; 693 694 #include "drm_mode.h" 695 696 #define DRM_IOCTL_BASE 'd' 697 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 698 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 699 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 700 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 701 702 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 703 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) 704 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) 705 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) 706 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) 707 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 708 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 709 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 710 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 711 #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 712 #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 713 #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) 714 #define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) 715 #define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) 716 717 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 718 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 719 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) 720 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) 721 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) 722 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 723 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) 724 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) 725 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 726 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) 727 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) 728 729 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) 730 731 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) 732 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) 733 734 #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) 735 #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) 736 737 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) 738 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) 739 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) 740 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) 741 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) 742 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) 743 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) 744 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) 745 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) 746 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) 747 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) 748 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 749 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 750 751 #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) 752 #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) 753 754 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 755 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 756 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) 757 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) 758 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) 759 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) 760 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 761 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 762 763 #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 764 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 765 766 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 767 768 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) 769 770 #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) 771 #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) 772 #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) 773 #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) 774 #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) 775 #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 776 #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 777 #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 778 #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 779 #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 780 781 #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 782 #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 783 #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) 784 #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) 785 #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) 786 #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) 787 #define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) 788 #define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) 789 790 #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) 791 #define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) 792 #define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) 793 #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) 794 #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) 795 #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) 796 #define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) 797 #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) 798 #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) 799 #define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) 800 #define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) 801 #define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) 802 #define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) 803 804 /** 805 * Device specific ioctls should only be in their respective headers 806 * The device specific ioctl range is from 0x40 to 0x9f. 807 * Generic IOCTLS restart at 0xA0. 808 * 809 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 810 * drmCommandReadWrite(). 811 */ 812 #define DRM_COMMAND_BASE 0x40 813 #define DRM_COMMAND_END 0xA0 814 815 /** 816 * Header for events written back to userspace on the drm fd. The 817 * type defines the type of event, the length specifies the total 818 * length of the event (including the header), and user_data is 819 * typically a 64 bit value passed with the ioctl that triggered the 820 * event. A read on the drm fd will always only return complete 821 * events, that is, if for example the read buffer is 100 bytes, and 822 * there are two 64 byte events pending, only one will be returned. 823 * 824 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and 825 * up are chipset specific. 826 */ 827 struct drm_event { 828 __u32 type; 829 __u32 length; 830 }; 831 832 #define DRM_EVENT_VBLANK 0x01 833 #define DRM_EVENT_FLIP_COMPLETE 0x02 834 835 struct drm_event_vblank { 836 struct drm_event base; 837 __u64 user_data; 838 __u32 tv_sec; 839 __u32 tv_usec; 840 __u32 sequence; 841 __u32 reserved; 842 }; 843 844 /* typedef area */ 845 #ifndef __KERNEL__ 846 typedef struct drm_clip_rect drm_clip_rect_t; 847 typedef struct drm_drawable_info drm_drawable_info_t; 848 typedef struct drm_tex_region drm_tex_region_t; 849 typedef struct drm_hw_lock drm_hw_lock_t; 850 typedef struct drm_version drm_version_t; 851 typedef struct drm_unique drm_unique_t; 852 typedef struct drm_list drm_list_t; 853 typedef struct drm_block drm_block_t; 854 typedef struct drm_control drm_control_t; 855 typedef enum drm_map_type drm_map_type_t; 856 typedef enum drm_map_flags drm_map_flags_t; 857 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; 858 typedef struct drm_map drm_map_t; 859 typedef struct drm_client drm_client_t; 860 typedef enum drm_stat_type drm_stat_type_t; 861 typedef struct drm_stats drm_stats_t; 862 typedef enum drm_lock_flags drm_lock_flags_t; 863 typedef struct drm_lock drm_lock_t; 864 typedef enum drm_dma_flags drm_dma_flags_t; 865 typedef struct drm_buf_desc drm_buf_desc_t; 866 typedef struct drm_buf_info drm_buf_info_t; 867 typedef struct drm_buf_free drm_buf_free_t; 868 typedef struct drm_buf_pub drm_buf_pub_t; 869 typedef struct drm_buf_map drm_buf_map_t; 870 typedef struct drm_dma drm_dma_t; 871 typedef union drm_wait_vblank drm_wait_vblank_t; 872 typedef struct drm_agp_mode drm_agp_mode_t; 873 typedef enum drm_ctx_flags drm_ctx_flags_t; 874 typedef struct drm_ctx drm_ctx_t; 875 typedef struct drm_ctx_res drm_ctx_res_t; 876 typedef struct drm_draw drm_draw_t; 877 typedef struct drm_update_draw drm_update_draw_t; 878 typedef struct drm_auth drm_auth_t; 879 typedef struct drm_irq_busid drm_irq_busid_t; 880 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; 881 882 typedef struct drm_agp_buffer drm_agp_buffer_t; 883 typedef struct drm_agp_binding drm_agp_binding_t; 884 typedef struct drm_agp_info drm_agp_info_t; 885 typedef struct drm_scatter_gather drm_scatter_gather_t; 886 typedef struct drm_set_version drm_set_version_t; 887 #endif 888 889 #endif 890