1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef _UAPI_AMDXDNA_ACCEL_H_ 7 #define _UAPI_AMDXDNA_ACCEL_H_ 8 9 #include <linux/stddef.h> 10 #include "drm.h" 11 12 #if defined(__cplusplus) 13 extern "C" { 14 #endif 15 16 #define AMDXDNA_INVALID_CMD_HANDLE (~0UL) 17 #define AMDXDNA_INVALID_ADDR (~0UL) 18 #define AMDXDNA_INVALID_CTX_HANDLE 0 19 #define AMDXDNA_INVALID_BO_HANDLE 0 20 #define AMDXDNA_INVALID_FENCE_HANDLE 0 21 22 /* 23 * Define hardware context priority 24 */ 25 #define AMDXDNA_QOS_REALTIME_PRIORITY 0x100 26 #define AMDXDNA_QOS_HIGH_PRIORITY 0x180 27 #define AMDXDNA_QOS_NORMAL_PRIORITY 0x200 28 #define AMDXDNA_QOS_LOW_PRIORITY 0x280 29 30 enum amdxdna_device_type { 31 AMDXDNA_DEV_TYPE_UNKNOWN = -1, 32 AMDXDNA_DEV_TYPE_KMQ = 0, 33 AMDXDNA_DEV_TYPE_PF = 2, 34 }; 35 36 enum amdxdna_drm_ioctl_id { 37 DRM_AMDXDNA_CREATE_HWCTX, 38 DRM_AMDXDNA_DESTROY_HWCTX, 39 DRM_AMDXDNA_CONFIG_HWCTX, 40 DRM_AMDXDNA_CREATE_BO, 41 DRM_AMDXDNA_GET_BO_INFO, 42 DRM_AMDXDNA_SYNC_BO, 43 DRM_AMDXDNA_EXEC_CMD, 44 DRM_AMDXDNA_GET_INFO, 45 DRM_AMDXDNA_SET_STATE, 46 DRM_AMDXDNA_GET_ARRAY = 10, 47 }; 48 49 /** 50 * struct qos_info - QoS information for driver. 51 * @gops: Giga operations per second. 52 * @fps: Frames per second. 53 * @dma_bandwidth: DMA bandwidtha. 54 * @latency: Frame response latency. 55 * @frame_exec_time: Frame execution time. 56 * @priority: Request priority. 57 * 58 * User program can provide QoS hints to driver. 59 */ 60 struct amdxdna_qos_info { 61 __u32 gops; 62 __u32 fps; 63 __u32 dma_bandwidth; 64 __u32 latency; 65 __u32 frame_exec_time; 66 __u32 priority; 67 }; 68 69 /** 70 * struct amdxdna_drm_create_hwctx - Create hardware context. 71 * @ext: MBZ. 72 * @ext_flags: MBZ. 73 * @qos_p: Address of QoS info. 74 * @umq_bo: BO handle for user mode queue(UMQ). 75 * @log_buf_bo: BO handle for log buffer. 76 * @max_opc: Maximum operations per cycle. 77 * @num_tiles: Number of AIE tiles. 78 * @mem_size: Size of AIE tile memory. 79 * @umq_doorbell: Returned offset of doorbell associated with UMQ. 80 * @handle: Returned hardware context handle. 81 * @syncobj_handle: Returned syncobj handle for command completion. 82 */ 83 struct amdxdna_drm_create_hwctx { 84 __u64 ext; 85 __u64 ext_flags; 86 __u64 qos_p; 87 __u32 umq_bo; 88 __u32 log_buf_bo; 89 __u32 max_opc; 90 __u32 num_tiles; 91 __u32 mem_size; 92 __u32 umq_doorbell; 93 __u32 handle; 94 __u32 syncobj_handle; 95 }; 96 97 /** 98 * struct amdxdna_drm_destroy_hwctx - Destroy hardware context. 99 * @handle: Hardware context handle. 100 * @pad: MBZ. 101 */ 102 struct amdxdna_drm_destroy_hwctx { 103 __u32 handle; 104 __u32 pad; 105 }; 106 107 /** 108 * struct amdxdna_cu_config - configuration for one CU 109 * @cu_bo: CU configuration buffer bo handle. 110 * @cu_func: Function of a CU. 111 * @pad: MBZ. 112 */ 113 struct amdxdna_cu_config { 114 __u32 cu_bo; 115 __u8 cu_func; 116 __u8 pad[3]; 117 }; 118 119 /** 120 * struct amdxdna_hwctx_param_config_cu - configuration for CUs in hardware context 121 * @num_cus: Number of CUs to configure. 122 * @pad: MBZ. 123 * @cu_configs: Array of CU configurations of struct amdxdna_cu_config. 124 */ 125 struct amdxdna_hwctx_param_config_cu { 126 __u16 num_cus; 127 __u16 pad[3]; 128 struct amdxdna_cu_config cu_configs[] __counted_by(num_cus); 129 }; 130 131 enum amdxdna_drm_config_hwctx_param { 132 DRM_AMDXDNA_HWCTX_CONFIG_CU, 133 DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF, 134 DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF, 135 }; 136 137 /** 138 * struct amdxdna_drm_config_hwctx - Configure hardware context. 139 * @handle: hardware context handle. 140 * @param_type: Value in enum amdxdna_drm_config_hwctx_param. Specifies the 141 * structure passed in via param_val. 142 * @param_val: A structure specified by the param_type struct member. 143 * @param_val_size: Size of the parameter buffer pointed to by the param_val. 144 * If param_val is not a pointer, driver can ignore this. 145 * @pad: MBZ. 146 * 147 * Note: if the param_val is a pointer pointing to a buffer, the maximum size 148 * of the buffer is 4KiB(PAGE_SIZE). 149 */ 150 struct amdxdna_drm_config_hwctx { 151 __u32 handle; 152 __u32 param_type; 153 __u64 param_val; 154 __u32 param_val_size; 155 __u32 pad; 156 }; 157 158 enum amdxdna_bo_type { 159 AMDXDNA_BO_INVALID = 0, 160 AMDXDNA_BO_SHMEM = 1, /* Be compatible with legacy application code. */ 161 AMDXDNA_BO_SHARE = 1, 162 AMDXDNA_BO_DEV_HEAP = 2, 163 AMDXDNA_BO_DEV = 3, 164 AMDXDNA_BO_CMD = 4, 165 }; 166 167 /** 168 * struct amdxdna_drm_va_entry 169 * @vaddr: Virtual address. 170 * @len: Size of entry. 171 */ 172 struct amdxdna_drm_va_entry { 173 __u64 vaddr; 174 __u64 len; 175 }; 176 177 /** 178 * struct amdxdna_drm_va_tbl 179 * @dmabuf_fd: The fd of dmabuf. 180 * @num_entries: Number of va entries. 181 * @va_entries: Array of va entries. 182 * 183 * The input can be either a dmabuf fd or a virtual address entry table. 184 * When dmabuf_fd is used, num_entries must be zero. 185 */ 186 struct amdxdna_drm_va_tbl { 187 __s32 dmabuf_fd; 188 __u32 num_entries; 189 struct amdxdna_drm_va_entry va_entries[]; 190 }; 191 192 /** 193 * struct amdxdna_drm_create_bo - Create a buffer object. 194 * @flags: Buffer flags. MBZ. 195 * @vaddr: User VA of buffer if applied. MBZ. 196 * @size: Size in bytes. 197 * @type: Buffer type. 198 * @handle: Returned DRM buffer object handle. 199 */ 200 struct amdxdna_drm_create_bo { 201 __u64 flags; 202 __u64 vaddr; 203 __u64 size; 204 __u32 type; 205 __u32 handle; 206 }; 207 208 /** 209 * struct amdxdna_drm_get_bo_info - Get buffer object information. 210 * @ext: MBZ. 211 * @ext_flags: MBZ. 212 * @handle: DRM buffer object handle. 213 * @pad: MBZ. 214 * @map_offset: Returned DRM fake offset for mmap(). 215 * @vaddr: Returned user VA of buffer. 0 in case user needs mmap(). 216 * @xdna_addr: Returned XDNA device virtual address. 217 */ 218 struct amdxdna_drm_get_bo_info { 219 __u64 ext; 220 __u64 ext_flags; 221 __u32 handle; 222 __u32 pad; 223 __u64 map_offset; 224 __u64 vaddr; 225 __u64 xdna_addr; 226 }; 227 228 /** 229 * struct amdxdna_drm_sync_bo - Sync buffer object. 230 * @handle: Buffer object handle. 231 * @direction: Direction of sync, can be from device or to device. 232 * @offset: Offset in the buffer to sync. 233 * @size: Size in bytes. 234 */ 235 struct amdxdna_drm_sync_bo { 236 __u32 handle; 237 #define SYNC_DIRECT_TO_DEVICE 0U 238 #define SYNC_DIRECT_FROM_DEVICE 1U 239 __u32 direction; 240 __u64 offset; 241 __u64 size; 242 }; 243 244 enum amdxdna_cmd_type { 245 AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0, 246 AMDXDNA_CMD_SUBMIT_DEPENDENCY, 247 AMDXDNA_CMD_SUBMIT_SIGNAL, 248 }; 249 250 /** 251 * struct amdxdna_drm_exec_cmd - Execute command. 252 * @ext: MBZ. 253 * @ext_flags: MBZ. 254 * @hwctx: Hardware context handle. 255 * @type: One of command type in enum amdxdna_cmd_type. 256 * @cmd_handles: Array of command handles or the command handle itself 257 * in case of just one. 258 * @args: Array of arguments for all command handles. 259 * @cmd_count: Number of command handles in the cmd_handles array. 260 * @arg_count: Number of arguments in the args array. 261 * @seq: Returned sequence number for this command. 262 */ 263 struct amdxdna_drm_exec_cmd { 264 __u64 ext; 265 __u64 ext_flags; 266 __u32 hwctx; 267 __u32 type; 268 __u64 cmd_handles; 269 __u64 args; 270 __u32 cmd_count; 271 __u32 arg_count; 272 __u64 seq; 273 }; 274 275 /** 276 * struct amdxdna_drm_query_aie_status - Query the status of the AIE hardware 277 * @buffer: The user space buffer that will return the AIE status. 278 * @buffer_size: The size of the user space buffer. 279 * @cols_filled: A bitmap of AIE columns whose data has been returned in the buffer. 280 */ 281 struct amdxdna_drm_query_aie_status { 282 __u64 buffer; /* out */ 283 __u32 buffer_size; /* in */ 284 __u32 cols_filled; /* out */ 285 }; 286 287 /** 288 * struct amdxdna_drm_query_aie_version - Query the version of the AIE hardware 289 * @major: The major version number. 290 * @minor: The minor version number. 291 */ 292 struct amdxdna_drm_query_aie_version { 293 __u32 major; /* out */ 294 __u32 minor; /* out */ 295 }; 296 297 /** 298 * struct amdxdna_drm_query_aie_tile_metadata - Query the metadata of AIE tile (core, mem, shim) 299 * @row_count: The number of rows. 300 * @row_start: The starting row number. 301 * @dma_channel_count: The number of dma channels. 302 * @lock_count: The number of locks. 303 * @event_reg_count: The number of events. 304 * @pad: Structure padding. 305 */ 306 struct amdxdna_drm_query_aie_tile_metadata { 307 __u16 row_count; 308 __u16 row_start; 309 __u16 dma_channel_count; 310 __u16 lock_count; 311 __u16 event_reg_count; 312 __u16 pad[3]; 313 }; 314 315 /** 316 * struct amdxdna_drm_query_aie_metadata - Query the metadata of the AIE hardware 317 * @col_size: The size of a column in bytes. 318 * @cols: The total number of columns. 319 * @rows: The total number of rows. 320 * @version: The version of the AIE hardware. 321 * @core: The metadata for all core tiles. 322 * @mem: The metadata for all mem tiles. 323 * @shim: The metadata for all shim tiles. 324 */ 325 struct amdxdna_drm_query_aie_metadata { 326 __u32 col_size; 327 __u16 cols; 328 __u16 rows; 329 struct amdxdna_drm_query_aie_version version; 330 struct amdxdna_drm_query_aie_tile_metadata core; 331 struct amdxdna_drm_query_aie_tile_metadata mem; 332 struct amdxdna_drm_query_aie_tile_metadata shim; 333 }; 334 335 /** 336 * struct amdxdna_drm_query_clock - Metadata for a clock 337 * @name: The clock name. 338 * @freq_mhz: The clock frequency. 339 * @pad: Structure padding. 340 */ 341 struct amdxdna_drm_query_clock { 342 __u8 name[16]; 343 __u32 freq_mhz; 344 __u32 pad; 345 }; 346 347 /** 348 * struct amdxdna_drm_query_clock_metadata - Query metadata for clocks 349 * @mp_npu_clock: The metadata for MP-NPU clock. 350 * @h_clock: The metadata for H clock. 351 */ 352 struct amdxdna_drm_query_clock_metadata { 353 struct amdxdna_drm_query_clock mp_npu_clock; 354 struct amdxdna_drm_query_clock h_clock; 355 }; 356 357 enum amdxdna_sensor_type { 358 AMDXDNA_SENSOR_TYPE_POWER, 359 AMDXDNA_SENSOR_TYPE_COLUMN_UTILIZATION 360 }; 361 362 /** 363 * struct amdxdna_drm_query_sensor - The data for single sensor. 364 * @label: The name for a sensor. 365 * @input: The current value of the sensor. 366 * @max: The maximum value possible for the sensor. 367 * @average: The average value of the sensor. 368 * @highest: The highest recorded sensor value for this driver load for the sensor. 369 * @status: The sensor status. 370 * @units: The sensor units. 371 * @unitm: Translates value member variables into the correct unit via (pow(10, unitm) * value). 372 * @type: The sensor type from enum amdxdna_sensor_type. 373 * @pad: Structure padding. 374 */ 375 struct amdxdna_drm_query_sensor { 376 __u8 label[64]; 377 __u32 input; 378 __u32 max; 379 __u32 average; 380 __u32 highest; 381 __u8 status[64]; 382 __u8 units[16]; 383 __s8 unitm; 384 __u8 type; 385 __u8 pad[6]; 386 }; 387 388 /** 389 * struct amdxdna_drm_query_hwctx - The data for single context. 390 * @context_id: The ID for this context. 391 * @start_col: The starting column for the partition assigned to this context. 392 * @num_col: The number of columns in the partition assigned to this context. 393 * @pad: Structure padding. 394 * @pid: The Process ID of the process that created this context. 395 * @command_submissions: The number of commands submitted to this context. 396 * @command_completions: The number of commands completed by this context. 397 * @migrations: The number of times this context has been moved to a different partition. 398 * @preemptions: The number of times this context has been preempted by another context in the 399 * same partition. 400 * @errors: The errors for this context. 401 */ 402 struct amdxdna_drm_query_hwctx { 403 __u32 context_id; 404 __u32 start_col; 405 __u32 num_col; 406 __u32 pad; 407 __s64 pid; 408 __u64 command_submissions; 409 __u64 command_completions; 410 __u64 migrations; 411 __u64 preemptions; 412 __u64 errors; 413 }; 414 415 enum amdxdna_power_mode_type { 416 POWER_MODE_DEFAULT, /* Fallback to calculated DPM */ 417 POWER_MODE_LOW, /* Set frequency to lowest DPM */ 418 POWER_MODE_MEDIUM, /* Set frequency to medium DPM */ 419 POWER_MODE_HIGH, /* Set frequency to highest DPM */ 420 POWER_MODE_TURBO, /* Maximum power */ 421 }; 422 423 /** 424 * struct amdxdna_drm_get_power_mode - Get the configured power mode 425 * @power_mode: The mode type from enum amdxdna_power_mode_type 426 * @pad: Structure padding. 427 */ 428 struct amdxdna_drm_get_power_mode { 429 __u8 power_mode; 430 __u8 pad[7]; 431 }; 432 433 /** 434 * struct amdxdna_drm_query_firmware_version - Query the firmware version 435 * @major: The major version number 436 * @minor: The minor version number 437 * @patch: The patch level version number 438 * @build: The build ID 439 */ 440 struct amdxdna_drm_query_firmware_version { 441 __u32 major; /* out */ 442 __u32 minor; /* out */ 443 __u32 patch; /* out */ 444 __u32 build; /* out */ 445 }; 446 447 enum amdxdna_drm_get_param { 448 DRM_AMDXDNA_QUERY_AIE_STATUS, 449 DRM_AMDXDNA_QUERY_AIE_METADATA, 450 DRM_AMDXDNA_QUERY_AIE_VERSION, 451 DRM_AMDXDNA_QUERY_CLOCK_METADATA, 452 DRM_AMDXDNA_QUERY_SENSORS, 453 DRM_AMDXDNA_QUERY_HW_CONTEXTS, 454 DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8, 455 DRM_AMDXDNA_GET_POWER_MODE, 456 DRM_AMDXDNA_QUERY_TELEMETRY, 457 DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE, 458 DRM_AMDXDNA_QUERY_RESOURCE_INFO, 459 DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE, 460 }; 461 462 /** 463 * struct amdxdna_drm_get_resource_info - Get resource information 464 */ 465 struct amdxdna_drm_get_resource_info { 466 /** @npu_clk_max: max H-Clocks */ 467 __u64 npu_clk_max; 468 /** @npu_tops_max: max TOPs */ 469 __u64 npu_tops_max; 470 /** @npu_task_max: max number of tasks */ 471 __u64 npu_task_max; 472 /** @npu_tops_curr: current TOPs */ 473 __u64 npu_tops_curr; 474 /** @npu_task_curr: current number of tasks */ 475 __u64 npu_task_curr; 476 }; 477 478 /** 479 * struct amdxdna_drm_attribute_state - State of an attribute 480 */ 481 struct amdxdna_drm_attribute_state { 482 /** @state: enabled or disabled */ 483 __u8 state; 484 /** @pad: MBZ */ 485 __u8 pad[7]; 486 }; 487 488 /** 489 * struct amdxdna_drm_query_telemetry_header - Telemetry data header 490 */ 491 struct amdxdna_drm_query_telemetry_header { 492 /** @major: Firmware telemetry interface major version number */ 493 __u32 major; 494 /** @minor: Firmware telemetry interface minor version number */ 495 __u32 minor; 496 /** @type: Telemetry query type */ 497 __u32 type; 498 /** @map_num_elements: Total number of elements in the map table */ 499 __u32 map_num_elements; 500 /** @map: Element map */ 501 __u32 map[]; 502 }; 503 504 /** 505 * struct amdxdna_drm_get_info - Get some information from the AIE hardware. 506 * @param: Value in enum amdxdna_drm_get_param. Specifies the structure passed in the buffer. 507 * @buffer_size: Size of the input buffer. Size needed/written by the kernel. 508 * @buffer: A structure specified by the param struct member. 509 */ 510 struct amdxdna_drm_get_info { 511 __u32 param; /* in */ 512 __u32 buffer_size; /* in/out */ 513 __u64 buffer; /* in/out */ 514 }; 515 516 #define AMDXDNA_HWCTX_STATE_IDLE 0 517 #define AMDXDNA_HWCTX_STATE_ACTIVE 1 518 519 /** 520 * struct amdxdna_drm_hwctx_entry - The hardware context array entry 521 */ 522 struct amdxdna_drm_hwctx_entry { 523 /** @context_id: Context ID. */ 524 __u32 context_id; 525 /** @start_col: Start AIE array column assigned to context. */ 526 __u32 start_col; 527 /** @num_col: Number of AIE array columns assigned to context. */ 528 __u32 num_col; 529 /** @hwctx_id: The real hardware context id. */ 530 __u32 hwctx_id; 531 /** @pid: ID of process which created this context. */ 532 __s64 pid; 533 /** @command_submissions: Number of commands submitted. */ 534 __u64 command_submissions; 535 /** @command_completions: Number of commands completed. */ 536 __u64 command_completions; 537 /** @migrations: Number of times been migrated. */ 538 __u64 migrations; 539 /** @preemptions: Number of times been preempted. */ 540 __u64 preemptions; 541 /** @errors: Number of errors happened. */ 542 __u64 errors; 543 /** @priority: Context priority. */ 544 __u64 priority; 545 /** @heap_usage: Usage of device heap buffer. */ 546 __u64 heap_usage; 547 /** @suspensions: Number of times been suspended. */ 548 __u64 suspensions; 549 /** 550 * @state: Context state. 551 * %AMDXDNA_HWCTX_STATE_IDLE 552 * %AMDXDNA_HWCTX_STATE_ACTIVE 553 */ 554 __u32 state; 555 /** @pasid: PASID been bound. */ 556 __u32 pasid; 557 /** @gops: Giga operations per second. */ 558 __u32 gops; 559 /** @fps: Frames per second. */ 560 __u32 fps; 561 /** @dma_bandwidth: DMA bandwidth. */ 562 __u32 dma_bandwidth; 563 /** @latency: Frame response latency. */ 564 __u32 latency; 565 /** @frame_exec_time: Frame execution time. */ 566 __u32 frame_exec_time; 567 /** @txn_op_idx: Index of last control code executed. */ 568 __u32 txn_op_idx; 569 /** @ctx_pc: Program counter. */ 570 __u32 ctx_pc; 571 /** @fatal_error_type: Fatal error type if context crashes. */ 572 __u32 fatal_error_type; 573 /** @fatal_error_exception_type: Firmware exception type. */ 574 __u32 fatal_error_exception_type; 575 /** @fatal_error_exception_pc: Firmware exception program counter. */ 576 __u32 fatal_error_exception_pc; 577 /** @fatal_error_app_module: Exception module name. */ 578 __u32 fatal_error_app_module; 579 /** @pad: Structure pad. */ 580 __u32 pad; 581 }; 582 583 /** 584 * struct amdxdna_async_error - XDNA async error structure 585 */ 586 struct amdxdna_async_error { 587 /** @err_code: Error code. */ 588 __u64 err_code; 589 /** @ts_us: Timestamp. */ 590 __u64 ts_us; 591 /** @ex_err_code: Extra error code */ 592 __u64 ex_err_code; 593 }; 594 595 /** 596 * struct amdxdna_drm_bo_usage - all types of BO usage 597 * BOs managed by XRT/SHIM/driver is counted as internal. 598 * Others are counted as external which are managed by applications. 599 * 600 * Among all types of BOs: 601 * AMDXDNA_BO_DEV_HEAP - is counted for internal. 602 * AMDXDNA_BO_SHARE - is counted for external. 603 * AMDXDNA_BO_CMD - is counted for internal. 604 * AMDXDNA_BO_DEV - is counted by heap_usage only, not internal 605 * or external. It does not add to the total memory 606 * footprint since its mem comes from heap which is 607 * already counted as internal. 608 */ 609 struct amdxdna_drm_bo_usage { 610 /** @pid: The ID of the process to query from. */ 611 __s64 pid; 612 /** @total_usage: Total BO size used by process. */ 613 __u64 total_usage; 614 /** @internal_usage: Total internal BO size used by process. */ 615 __u64 internal_usage; 616 /** @heap_usage: Total device BO size used by process. */ 617 __u64 heap_usage; 618 }; 619 620 /* 621 * Supported params in struct amdxdna_drm_get_array 622 */ 623 #define DRM_AMDXDNA_HW_CONTEXT_ALL 0 624 #define DRM_AMDXDNA_HW_LAST_ASYNC_ERR 2 625 #define DRM_AMDXDNA_BO_USAGE 6 626 627 /** 628 * struct amdxdna_drm_get_array - Get information array. 629 */ 630 struct amdxdna_drm_get_array { 631 /** 632 * @param: 633 * 634 * Supported params: 635 * 636 * %DRM_AMDXDNA_HW_CONTEXT_ALL: 637 * Returns all created hardware contexts. 638 * 639 * %DRM_AMDXDNA_HW_LAST_ASYNC_ERR: 640 * Returns last async error. 641 * 642 * %DRM_AMDXDNA_BO_USAGE: 643 * Returns usage of heap/internal/external BOs. 644 */ 645 __u32 param; 646 /** 647 * @element_size: 648 * 649 * Specifies maximum element size and returns the actual element size. 650 */ 651 __u32 element_size; 652 /** 653 * @num_element: 654 * 655 * Specifies maximum number of elements and returns the actual number 656 * of elements. 657 */ 658 __u32 num_element; /* in/out */ 659 /** @pad: MBZ */ 660 __u32 pad; 661 /** 662 * @buffer: 663 * 664 * Specifies the match conditions and returns the matched information 665 * array. 666 */ 667 __u64 buffer; 668 }; 669 670 enum amdxdna_drm_set_param { 671 DRM_AMDXDNA_SET_POWER_MODE, 672 DRM_AMDXDNA_WRITE_AIE_MEM, 673 DRM_AMDXDNA_WRITE_AIE_REG, 674 DRM_AMDXDNA_SET_FORCE_PREEMPT, 675 DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT, 676 }; 677 678 /** 679 * struct amdxdna_drm_set_state - Set the state of the AIE hardware. 680 * @param: Value in enum amdxdna_drm_set_param. 681 * @buffer_size: Size of the input param. 682 * @buffer: Pointer to the input param. 683 */ 684 struct amdxdna_drm_set_state { 685 __u32 param; /* in */ 686 __u32 buffer_size; /* in */ 687 __u64 buffer; /* in */ 688 }; 689 690 /** 691 * struct amdxdna_drm_set_power_mode - Set the power mode of the AIE hardware 692 * @power_mode: The sensor type from enum amdxdna_power_mode_type 693 * @pad: MBZ. 694 */ 695 struct amdxdna_drm_set_power_mode { 696 __u8 power_mode; 697 __u8 pad[7]; 698 }; 699 700 #define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \ 701 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \ 702 struct amdxdna_drm_create_hwctx) 703 704 #define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \ 705 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \ 706 struct amdxdna_drm_destroy_hwctx) 707 708 #define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \ 709 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \ 710 struct amdxdna_drm_config_hwctx) 711 712 #define DRM_IOCTL_AMDXDNA_CREATE_BO \ 713 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \ 714 struct amdxdna_drm_create_bo) 715 716 #define DRM_IOCTL_AMDXDNA_GET_BO_INFO \ 717 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \ 718 struct amdxdna_drm_get_bo_info) 719 720 #define DRM_IOCTL_AMDXDNA_SYNC_BO \ 721 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \ 722 struct amdxdna_drm_sync_bo) 723 724 #define DRM_IOCTL_AMDXDNA_EXEC_CMD \ 725 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \ 726 struct amdxdna_drm_exec_cmd) 727 728 #define DRM_IOCTL_AMDXDNA_GET_INFO \ 729 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \ 730 struct amdxdna_drm_get_info) 731 732 #define DRM_IOCTL_AMDXDNA_SET_STATE \ 733 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \ 734 struct amdxdna_drm_set_state) 735 736 #define DRM_IOCTL_AMDXDNA_GET_ARRAY \ 737 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_ARRAY, \ 738 struct amdxdna_drm_get_array) 739 740 #if defined(__cplusplus) 741 } /* extern c end */ 742 #endif 743 744 #endif /* _UAPI_AMDXDNA_ACCEL_H_ */ 745