1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef _UAPI_AMDXDNA_ACCEL_H_ 7 #define _UAPI_AMDXDNA_ACCEL_H_ 8 9 #include <linux/stddef.h> 10 #include "drm.h" 11 12 #if defined(__cplusplus) 13 extern "C" { 14 #endif 15 16 #define AMDXDNA_INVALID_CMD_HANDLE (~0UL) 17 #define AMDXDNA_INVALID_ADDR (~0UL) 18 #define AMDXDNA_INVALID_CTX_HANDLE 0 19 #define AMDXDNA_INVALID_BO_HANDLE 0 20 #define AMDXDNA_INVALID_FENCE_HANDLE 0 21 #define AMDXDNA_INVALID_DOORBELL_OFFSET (~0U) 22 23 /* 24 * Define hardware context priority 25 */ 26 #define AMDXDNA_QOS_REALTIME_PRIORITY 0x100 27 #define AMDXDNA_QOS_HIGH_PRIORITY 0x180 28 #define AMDXDNA_QOS_NORMAL_PRIORITY 0x200 29 #define AMDXDNA_QOS_LOW_PRIORITY 0x280 30 31 enum amdxdna_device_type { 32 AMDXDNA_DEV_TYPE_UNKNOWN = -1, 33 AMDXDNA_DEV_TYPE_KMQ = 0, 34 AMDXDNA_DEV_TYPE_UMQ = 1, 35 AMDXDNA_DEV_TYPE_PF = 2, 36 }; 37 38 enum amdxdna_drm_ioctl_id { 39 DRM_AMDXDNA_CREATE_HWCTX, 40 DRM_AMDXDNA_DESTROY_HWCTX, 41 DRM_AMDXDNA_CONFIG_HWCTX, 42 DRM_AMDXDNA_CREATE_BO, 43 DRM_AMDXDNA_GET_BO_INFO, 44 DRM_AMDXDNA_SYNC_BO, 45 DRM_AMDXDNA_EXEC_CMD, 46 DRM_AMDXDNA_GET_INFO, 47 DRM_AMDXDNA_SET_STATE, 48 DRM_AMDXDNA_WAIT_CMD, 49 DRM_AMDXDNA_GET_ARRAY, 50 }; 51 52 /** 53 * struct qos_info - QoS information for driver. 54 * @gops: Giga operations per second. 55 * @fps: Frames per second. 56 * @dma_bandwidth: DMA bandwidtha. 57 * @latency: Frame response latency. 58 * @frame_exec_time: Frame execution time. 59 * @priority: Request priority. 60 * 61 * User program can provide QoS hints to driver. 62 */ 63 struct amdxdna_qos_info { 64 __u32 gops; 65 __u32 fps; 66 __u32 dma_bandwidth; 67 __u32 latency; 68 __u32 frame_exec_time; 69 __u32 priority; 70 }; 71 72 /** 73 * struct amdxdna_drm_create_hwctx - Create hardware context. 74 * @ext: MBZ. 75 * @ext_flags: MBZ. 76 * @qos_p: Address of QoS info. 77 * @umq_bo: BO handle for user mode queue(UMQ). 78 * @log_buf_bo: BO handle for log buffer. 79 * @max_opc: Maximum operations per cycle. 80 * @num_tiles: Number of AIE tiles. 81 * @mem_size: Size of AIE tile memory. 82 * @umq_doorbell: Returned offset of doorbell associated with UMQ. 83 * @handle: Returned hardware context handle. 84 * @syncobj_handle: Returned syncobj handle for command completion. 85 */ 86 struct amdxdna_drm_create_hwctx { 87 __u64 ext; 88 __u64 ext_flags; 89 __u64 qos_p; 90 __u32 umq_bo; 91 __u32 log_buf_bo; 92 __u32 max_opc; 93 __u32 num_tiles; 94 __u32 mem_size; 95 __u32 umq_doorbell; 96 __u32 handle; 97 __u32 syncobj_handle; 98 }; 99 100 /** 101 * struct amdxdna_drm_destroy_hwctx - Destroy hardware context. 102 * @handle: Hardware context handle. 103 * @pad: MBZ. 104 */ 105 struct amdxdna_drm_destroy_hwctx { 106 __u32 handle; 107 __u32 pad; 108 }; 109 110 /** 111 * struct amdxdna_cu_config - configuration for one CU 112 * @cu_bo: CU configuration buffer bo handle. 113 * @cu_func: Function of a CU. 114 * @pad: MBZ. 115 */ 116 struct amdxdna_cu_config { 117 __u32 cu_bo; 118 __u8 cu_func; 119 __u8 pad[3]; 120 }; 121 122 /** 123 * struct amdxdna_hwctx_param_config_cu - configuration for CUs in hardware context 124 * @num_cus: Number of CUs to configure. 125 * @pad: MBZ. 126 * @cu_configs: Array of CU configurations of struct amdxdna_cu_config. 127 */ 128 struct amdxdna_hwctx_param_config_cu { 129 __u16 num_cus; 130 __u16 pad[3]; 131 struct amdxdna_cu_config cu_configs[] __counted_by(num_cus); 132 }; 133 134 enum amdxdna_drm_config_hwctx_param { 135 DRM_AMDXDNA_HWCTX_CONFIG_CU, 136 DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF, 137 DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF, 138 }; 139 140 /** 141 * struct amdxdna_drm_config_hwctx - Configure hardware context. 142 * @handle: hardware context handle. 143 * @param_type: Value in enum amdxdna_drm_config_hwctx_param. Specifies the 144 * structure passed in via param_val. 145 * @param_val: A structure specified by the param_type struct member. 146 * @param_val_size: Size of the parameter buffer pointed to by the param_val. 147 * If param_val is not a pointer, driver can ignore this. 148 * @pad: MBZ. 149 * 150 * Note: if the param_val is a pointer pointing to a buffer, the maximum size 151 * of the buffer is 4KiB(PAGE_SIZE). 152 */ 153 struct amdxdna_drm_config_hwctx { 154 __u32 handle; 155 __u32 param_type; 156 __u64 param_val; 157 __u32 param_val_size; 158 __u32 pad; 159 }; 160 161 enum amdxdna_bo_type { 162 AMDXDNA_BO_INVALID = 0, 163 AMDXDNA_BO_SHMEM = 1, /* Be compatible with legacy application code. */ 164 AMDXDNA_BO_SHARE = 1, 165 AMDXDNA_BO_DEV_HEAP = 2, 166 AMDXDNA_BO_DEV = 3, 167 AMDXDNA_BO_CMD = 4, 168 }; 169 170 /** 171 * struct amdxdna_drm_va_entry 172 * @vaddr: Virtual address. 173 * @len: Size of entry. 174 */ 175 struct amdxdna_drm_va_entry { 176 __u64 vaddr; 177 __u64 len; 178 }; 179 180 /** 181 * struct amdxdna_drm_va_tbl 182 * @dmabuf_fd: The fd of dmabuf. 183 * @num_entries: Number of va entries. 184 * @va_entries: Array of va entries. 185 * 186 * The input can be either a dmabuf fd or a virtual address entry table. 187 * When dmabuf_fd is used, num_entries must be zero. 188 */ 189 struct amdxdna_drm_va_tbl { 190 __s32 dmabuf_fd; 191 __u32 num_entries; 192 struct amdxdna_drm_va_entry va_entries[]; 193 }; 194 195 /** 196 * struct amdxdna_drm_create_bo - Create a buffer object. 197 * @flags: Buffer flags. MBZ. 198 * @vaddr: User VA of buffer if applied. MBZ. 199 * @size: Size in bytes. 200 * @type: Buffer type. 201 * @handle: Returned DRM buffer object handle. 202 */ 203 struct amdxdna_drm_create_bo { 204 __u64 flags; 205 __u64 vaddr; 206 __u64 size; 207 __u32 type; 208 __u32 handle; 209 }; 210 211 /** 212 * struct amdxdna_drm_get_bo_info - Get buffer object information. 213 * @ext: MBZ. 214 * @ext_flags: MBZ. 215 * @handle: DRM buffer object handle. 216 * @pad: MBZ. 217 * @map_offset: Returned DRM fake offset for mmap(). 218 * @vaddr: Returned user VA of buffer. 0 in case user needs mmap(). 219 * @xdna_addr: Returned XDNA device virtual address. 220 */ 221 struct amdxdna_drm_get_bo_info { 222 __u64 ext; 223 __u64 ext_flags; 224 __u32 handle; 225 __u32 pad; 226 __u64 map_offset; 227 __u64 vaddr; 228 __u64 xdna_addr; 229 }; 230 231 /** 232 * struct amdxdna_drm_sync_bo - Sync buffer object. 233 * @handle: Buffer object handle. 234 * @direction: Direction of sync, can be from device or to device. 235 * @offset: Offset in the buffer to sync. 236 * @size: Size in bytes. 237 */ 238 struct amdxdna_drm_sync_bo { 239 __u32 handle; 240 #define SYNC_DIRECT_TO_DEVICE 0U 241 #define SYNC_DIRECT_FROM_DEVICE 1U 242 __u32 direction; 243 __u64 offset; 244 __u64 size; 245 }; 246 247 enum amdxdna_cmd_type { 248 AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0, 249 AMDXDNA_CMD_SUBMIT_DEPENDENCY, 250 AMDXDNA_CMD_SUBMIT_SIGNAL, 251 }; 252 253 /** 254 * struct amdxdna_drm_exec_cmd - Execute command. 255 * @ext: MBZ. 256 * @ext_flags: MBZ. 257 * @hwctx: Hardware context handle. 258 * @type: One of command type in enum amdxdna_cmd_type. 259 * @cmd_handles: Array of command handles or the command handle itself 260 * in case of just one. 261 * @args: Array of arguments for all command handles. 262 * @cmd_count: Number of command handles in the cmd_handles array. 263 * @arg_count: Number of arguments in the args array. 264 * @seq: Returned sequence number for this command. 265 */ 266 struct amdxdna_drm_exec_cmd { 267 __u64 ext; 268 __u64 ext_flags; 269 __u32 hwctx; 270 __u32 type; 271 __u64 cmd_handles; 272 __u64 args; 273 __u32 cmd_count; 274 __u32 arg_count; 275 __u64 seq; 276 }; 277 278 /** 279 * struct amdxdna_drm_wait_cmd - Wait execution command. 280 * 281 * @hwctx: Context handle. 282 * @timeout: timeout in ms, 0 implies infinite wait. 283 * @seq: sequence number of the command returned by execute command. 284 * 285 * Wait a command specified by seq to be completed. 286 */ 287 struct amdxdna_drm_wait_cmd { 288 __u32 hwctx; 289 __u32 timeout; 290 __u64 seq; 291 }; 292 293 /** 294 * struct amdxdna_drm_query_aie_status - Query the status of the AIE hardware 295 * @buffer: The user space buffer that will return the AIE status. 296 * @buffer_size: The size of the user space buffer. 297 * @cols_filled: A bitmap of AIE columns whose data has been returned in the buffer. 298 */ 299 struct amdxdna_drm_query_aie_status { 300 __u64 buffer; /* out */ 301 __u32 buffer_size; /* in */ 302 __u32 cols_filled; /* out */ 303 }; 304 305 /** 306 * struct amdxdna_drm_query_aie_version - Query the version of the AIE hardware 307 * @major: The major version number. 308 * @minor: The minor version number. 309 */ 310 struct amdxdna_drm_query_aie_version { 311 __u32 major; /* out */ 312 __u32 minor; /* out */ 313 }; 314 315 /** 316 * struct amdxdna_drm_query_aie_tile_metadata - Query the metadata of AIE tile (core, mem, shim) 317 * @row_count: The number of rows. 318 * @row_start: The starting row number. 319 * @dma_channel_count: The number of dma channels. 320 * @lock_count: The number of locks. 321 * @event_reg_count: The number of events. 322 * @pad: Structure padding. 323 */ 324 struct amdxdna_drm_query_aie_tile_metadata { 325 __u16 row_count; 326 __u16 row_start; 327 __u16 dma_channel_count; 328 __u16 lock_count; 329 __u16 event_reg_count; 330 __u16 pad[3]; 331 }; 332 333 /** 334 * struct amdxdna_drm_query_aie_metadata - Query the metadata of the AIE hardware 335 * @col_size: The size of a column in bytes. 336 * @cols: The total number of columns. 337 * @rows: The total number of rows. 338 * @version: The version of the AIE hardware. 339 * @core: The metadata for all core tiles. 340 * @mem: The metadata for all mem tiles. 341 * @shim: The metadata for all shim tiles. 342 */ 343 struct amdxdna_drm_query_aie_metadata { 344 __u32 col_size; 345 __u16 cols; 346 __u16 rows; 347 struct amdxdna_drm_query_aie_version version; 348 struct amdxdna_drm_query_aie_tile_metadata core; 349 struct amdxdna_drm_query_aie_tile_metadata mem; 350 struct amdxdna_drm_query_aie_tile_metadata shim; 351 }; 352 353 /** 354 * struct amdxdna_drm_query_clock - Metadata for a clock 355 * @name: The clock name. 356 * @freq_mhz: The clock frequency. 357 * @pad: Structure padding. 358 */ 359 struct amdxdna_drm_query_clock { 360 __u8 name[16]; 361 __u32 freq_mhz; 362 __u32 pad; 363 }; 364 365 /** 366 * struct amdxdna_drm_query_clock_metadata - Query metadata for clocks 367 * @mp_npu_clock: The metadata for MP-NPU clock. 368 * @h_clock: The metadata for H clock. 369 */ 370 struct amdxdna_drm_query_clock_metadata { 371 struct amdxdna_drm_query_clock mp_npu_clock; 372 struct amdxdna_drm_query_clock h_clock; 373 }; 374 375 enum amdxdna_sensor_type { 376 AMDXDNA_SENSOR_TYPE_POWER, 377 AMDXDNA_SENSOR_TYPE_COLUMN_UTILIZATION 378 }; 379 380 /** 381 * struct amdxdna_drm_query_sensor - The data for single sensor. 382 * @label: The name for a sensor. 383 * @input: The current value of the sensor. 384 * @max: The maximum value possible for the sensor. 385 * @average: The average value of the sensor. 386 * @highest: The highest recorded sensor value for this driver load for the sensor. 387 * @status: The sensor status. 388 * @units: The sensor units. 389 * @unitm: Translates value member variables into the correct unit via (pow(10, unitm) * value). 390 * @type: The sensor type from enum amdxdna_sensor_type. 391 * @pad: Structure padding. 392 */ 393 struct amdxdna_drm_query_sensor { 394 __u8 label[64]; 395 __u32 input; 396 __u32 max; 397 __u32 average; 398 __u32 highest; 399 __u8 status[64]; 400 __u8 units[16]; 401 __s8 unitm; 402 __u8 type; 403 __u8 pad[6]; 404 }; 405 406 /** 407 * struct amdxdna_drm_query_hwctx - The data for single context. 408 * @context_id: The ID for this context. 409 * @start_col: The starting column for the partition assigned to this context. 410 * @num_col: The number of columns in the partition assigned to this context. 411 * @pad: Structure padding. 412 * @pid: The Process ID of the process that created this context. 413 * @command_submissions: The number of commands submitted to this context. 414 * @command_completions: The number of commands completed by this context. 415 * @migrations: The number of times this context has been moved to a different partition. 416 * @preemptions: The number of times this context has been preempted by another context in the 417 * same partition. 418 * @errors: The errors for this context. 419 */ 420 struct amdxdna_drm_query_hwctx { 421 __u32 context_id; 422 __u32 start_col; 423 __u32 num_col; 424 __u32 pad; 425 __s64 pid; 426 __u64 command_submissions; 427 __u64 command_completions; 428 __u64 migrations; 429 __u64 preemptions; 430 __u64 errors; 431 }; 432 433 enum amdxdna_power_mode_type { 434 POWER_MODE_DEFAULT, /* Fallback to calculated DPM */ 435 POWER_MODE_LOW, /* Set frequency to lowest DPM */ 436 POWER_MODE_MEDIUM, /* Set frequency to medium DPM */ 437 POWER_MODE_HIGH, /* Set frequency to highest DPM */ 438 POWER_MODE_TURBO, /* Maximum power */ 439 }; 440 441 /** 442 * struct amdxdna_drm_get_power_mode - Get the configured power mode 443 * @power_mode: The mode type from enum amdxdna_power_mode_type 444 * @pad: Structure padding. 445 */ 446 struct amdxdna_drm_get_power_mode { 447 __u8 power_mode; 448 __u8 pad[7]; 449 }; 450 451 /** 452 * struct amdxdna_drm_query_firmware_version - Query the firmware version 453 * @major: The major version number 454 * @minor: The minor version number 455 * @patch: The patch level version number 456 * @build: The build ID 457 */ 458 struct amdxdna_drm_query_firmware_version { 459 __u32 major; /* out */ 460 __u32 minor; /* out */ 461 __u32 patch; /* out */ 462 __u32 build; /* out */ 463 }; 464 465 enum amdxdna_drm_get_param { 466 DRM_AMDXDNA_QUERY_AIE_STATUS, 467 DRM_AMDXDNA_QUERY_AIE_METADATA, 468 DRM_AMDXDNA_QUERY_AIE_VERSION, 469 DRM_AMDXDNA_QUERY_CLOCK_METADATA, 470 DRM_AMDXDNA_QUERY_SENSORS, 471 DRM_AMDXDNA_QUERY_HW_CONTEXTS, 472 DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8, 473 DRM_AMDXDNA_GET_POWER_MODE, 474 DRM_AMDXDNA_QUERY_TELEMETRY, 475 DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE, 476 DRM_AMDXDNA_QUERY_RESOURCE_INFO, 477 DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE, 478 }; 479 480 /** 481 * struct amdxdna_drm_get_resource_info - Get resource information 482 */ 483 struct amdxdna_drm_get_resource_info { 484 /** @npu_clk_max: max H-Clocks */ 485 __u64 npu_clk_max; 486 /** @npu_tops_max: max TOPs */ 487 __u64 npu_tops_max; 488 /** @npu_task_max: max number of tasks */ 489 __u64 npu_task_max; 490 /** @npu_tops_curr: current TOPs */ 491 __u64 npu_tops_curr; 492 /** @npu_task_curr: current number of tasks */ 493 __u64 npu_task_curr; 494 }; 495 496 /** 497 * struct amdxdna_drm_attribute_state - State of an attribute 498 */ 499 struct amdxdna_drm_attribute_state { 500 /** @state: enabled or disabled */ 501 __u8 state; 502 /** @pad: MBZ */ 503 __u8 pad[7]; 504 }; 505 506 /** 507 * struct amdxdna_drm_query_telemetry_header - Telemetry data header 508 */ 509 struct amdxdna_drm_query_telemetry_header { 510 /** @major: Firmware telemetry interface major version number */ 511 __u32 major; 512 /** @minor: Firmware telemetry interface minor version number */ 513 __u32 minor; 514 /** @type: Telemetry query type */ 515 __u32 type; 516 /** @map_num_elements: Total number of elements in the map table */ 517 __u32 map_num_elements; 518 /** @map: Element map */ 519 __u32 map[]; 520 }; 521 522 /** 523 * struct amdxdna_drm_get_info - Get some information from the AIE hardware. 524 * @param: Value in enum amdxdna_drm_get_param. Specifies the structure passed in the buffer. 525 * @buffer_size: Size of the input buffer. Size needed/written by the kernel. 526 * @buffer: A structure specified by the param struct member. 527 */ 528 struct amdxdna_drm_get_info { 529 __u32 param; /* in */ 530 __u32 buffer_size; /* in/out */ 531 __u64 buffer; /* in/out */ 532 }; 533 534 #define AMDXDNA_HWCTX_STATE_IDLE 0 535 #define AMDXDNA_HWCTX_STATE_ACTIVE 1 536 537 /** 538 * struct amdxdna_drm_hwctx_entry - The hardware context array entry 539 */ 540 struct amdxdna_drm_hwctx_entry { 541 /** @context_id: Context ID. */ 542 __u32 context_id; 543 /** @start_col: Start AIE array column assigned to context. */ 544 __u32 start_col; 545 /** @num_col: Number of AIE array columns assigned to context. */ 546 __u32 num_col; 547 /** @hwctx_id: The real hardware context id. */ 548 __u32 hwctx_id; 549 /** @pid: ID of process which created this context. */ 550 __s64 pid; 551 /** @command_submissions: Number of commands submitted. */ 552 __u64 command_submissions; 553 /** @command_completions: Number of commands completed. */ 554 __u64 command_completions; 555 /** @migrations: Number of times been migrated. */ 556 __u64 migrations; 557 /** @preemptions: Number of times been preempted. */ 558 __u64 preemptions; 559 /** @errors: Number of errors happened. */ 560 __u64 errors; 561 /** @priority: Context priority. */ 562 __u64 priority; 563 /** @heap_usage: Usage of device heap buffer. */ 564 __u64 heap_usage; 565 /** @suspensions: Number of times been suspended. */ 566 __u64 suspensions; 567 /** 568 * @state: Context state. 569 * %AMDXDNA_HWCTX_STATE_IDLE 570 * %AMDXDNA_HWCTX_STATE_ACTIVE 571 */ 572 __u32 state; 573 /** @pasid: PASID been bound. */ 574 __u32 pasid; 575 /** @gops: Giga operations per second. */ 576 __u32 gops; 577 /** @fps: Frames per second. */ 578 __u32 fps; 579 /** @dma_bandwidth: DMA bandwidth. */ 580 __u32 dma_bandwidth; 581 /** @latency: Frame response latency. */ 582 __u32 latency; 583 /** @frame_exec_time: Frame execution time. */ 584 __u32 frame_exec_time; 585 /** @txn_op_idx: Index of last control code executed. */ 586 __u32 txn_op_idx; 587 /** @ctx_pc: Program counter. */ 588 __u32 ctx_pc; 589 /** @fatal_error_type: Fatal error type if context crashes. */ 590 __u32 fatal_error_type; 591 /** @fatal_error_exception_type: Firmware exception type. */ 592 __u32 fatal_error_exception_type; 593 /** @fatal_error_exception_pc: Firmware exception program counter. */ 594 __u32 fatal_error_exception_pc; 595 /** @fatal_error_app_module: Exception module name. */ 596 __u32 fatal_error_app_module; 597 /** @pad: Structure pad. */ 598 __u32 pad; 599 }; 600 601 /** 602 * struct amdxdna_async_error - XDNA async error structure 603 */ 604 struct amdxdna_async_error { 605 /** @err_code: Error code. */ 606 __u64 err_code; 607 /** @ts_us: Timestamp. */ 608 __u64 ts_us; 609 /** @ex_err_code: Extra error code */ 610 __u64 ex_err_code; 611 }; 612 613 /** 614 * struct amdxdna_drm_bo_usage - all types of BO usage 615 * BOs managed by XRT/SHIM/driver is counted as internal. 616 * Others are counted as external which are managed by applications. 617 * 618 * Among all types of BOs: 619 * AMDXDNA_BO_DEV_HEAP - is counted for internal. 620 * AMDXDNA_BO_SHARE - is counted for external. 621 * AMDXDNA_BO_CMD - is counted for internal. 622 * AMDXDNA_BO_DEV - is counted by heap_usage only, not internal 623 * or external. It does not add to the total memory 624 * footprint since its mem comes from heap which is 625 * already counted as internal. 626 */ 627 struct amdxdna_drm_bo_usage { 628 /** @pid: The ID of the process to query from. */ 629 __s64 pid; 630 /** @total_usage: Total BO size used by process. */ 631 __u64 total_usage; 632 /** @internal_usage: Total internal BO size used by process. */ 633 __u64 internal_usage; 634 /** @heap_usage: Total device BO size used by process. */ 635 __u64 heap_usage; 636 }; 637 638 /* 639 * Supported params in struct amdxdna_drm_get_array 640 */ 641 #define DRM_AMDXDNA_HW_CONTEXT_ALL 0 642 #define DRM_AMDXDNA_HW_LAST_ASYNC_ERR 2 643 #define DRM_AMDXDNA_BO_USAGE 6 644 645 /** 646 * struct amdxdna_drm_get_array - Get information array. 647 */ 648 struct amdxdna_drm_get_array { 649 /** 650 * @param: 651 * 652 * Supported params: 653 * 654 * %DRM_AMDXDNA_HW_CONTEXT_ALL: 655 * Returns all created hardware contexts. 656 * 657 * %DRM_AMDXDNA_HW_LAST_ASYNC_ERR: 658 * Returns last async error. 659 * 660 * %DRM_AMDXDNA_BO_USAGE: 661 * Returns usage of heap/internal/external BOs. 662 */ 663 __u32 param; 664 /** 665 * @element_size: 666 * 667 * Specifies maximum element size and returns the actual element size. 668 */ 669 __u32 element_size; 670 /** 671 * @num_element: 672 * 673 * Specifies maximum number of elements and returns the actual number 674 * of elements. 675 */ 676 __u32 num_element; /* in/out */ 677 /** @pad: MBZ */ 678 __u32 pad; 679 /** 680 * @buffer: 681 * 682 * Specifies the match conditions and returns the matched information 683 * array. 684 */ 685 __u64 buffer; 686 }; 687 688 enum amdxdna_drm_set_param { 689 DRM_AMDXDNA_SET_POWER_MODE, 690 DRM_AMDXDNA_WRITE_AIE_MEM, 691 DRM_AMDXDNA_WRITE_AIE_REG, 692 DRM_AMDXDNA_SET_FORCE_PREEMPT, 693 DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT, 694 }; 695 696 /** 697 * struct amdxdna_drm_set_state - Set the state of the AIE hardware. 698 * @param: Value in enum amdxdna_drm_set_param. 699 * @buffer_size: Size of the input param. 700 * @buffer: Pointer to the input param. 701 */ 702 struct amdxdna_drm_set_state { 703 __u32 param; /* in */ 704 __u32 buffer_size; /* in */ 705 __u64 buffer; /* in */ 706 }; 707 708 /** 709 * struct amdxdna_drm_set_power_mode - Set the power mode of the AIE hardware 710 * @power_mode: The sensor type from enum amdxdna_power_mode_type 711 * @pad: MBZ. 712 */ 713 struct amdxdna_drm_set_power_mode { 714 __u8 power_mode; 715 __u8 pad[7]; 716 }; 717 718 #define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \ 719 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \ 720 struct amdxdna_drm_create_hwctx) 721 722 #define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \ 723 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \ 724 struct amdxdna_drm_destroy_hwctx) 725 726 #define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \ 727 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \ 728 struct amdxdna_drm_config_hwctx) 729 730 #define DRM_IOCTL_AMDXDNA_CREATE_BO \ 731 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \ 732 struct amdxdna_drm_create_bo) 733 734 #define DRM_IOCTL_AMDXDNA_GET_BO_INFO \ 735 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \ 736 struct amdxdna_drm_get_bo_info) 737 738 #define DRM_IOCTL_AMDXDNA_SYNC_BO \ 739 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \ 740 struct amdxdna_drm_sync_bo) 741 742 #define DRM_IOCTL_AMDXDNA_EXEC_CMD \ 743 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \ 744 struct amdxdna_drm_exec_cmd) 745 746 #define DRM_IOCTL_AMDXDNA_GET_INFO \ 747 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \ 748 struct amdxdna_drm_get_info) 749 750 #define DRM_IOCTL_AMDXDNA_SET_STATE \ 751 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \ 752 struct amdxdna_drm_set_state) 753 754 #define DRM_IOCTL_AMDXDNA_GET_ARRAY \ 755 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_ARRAY, \ 756 struct amdxdna_drm_get_array) 757 758 #define DRM_IOCTL_AMDXDNA_WAIT_CMD \ 759 DRM_IOW(DRM_COMMAND_BASE + DRM_AMDXDNA_WAIT_CMD, \ 760 struct amdxdna_drm_wait_cmd) 761 762 #if defined(__cplusplus) 763 } /* extern c end */ 764 #endif 765 766 #endif /* _UAPI_AMDXDNA_ACCEL_H_ */ 767