1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef _UAPI_AMDXDNA_ACCEL_H_ 7 #define _UAPI_AMDXDNA_ACCEL_H_ 8 9 #include <linux/stddef.h> 10 #include "drm.h" 11 12 #if defined(__cplusplus) 13 extern "C" { 14 #endif 15 16 #define AMDXDNA_INVALID_CMD_HANDLE (~0UL) 17 #define AMDXDNA_INVALID_ADDR (~0UL) 18 #define AMDXDNA_INVALID_CTX_HANDLE 0 19 #define AMDXDNA_INVALID_BO_HANDLE 0 20 #define AMDXDNA_INVALID_FENCE_HANDLE 0 21 22 enum amdxdna_device_type { 23 AMDXDNA_DEV_TYPE_UNKNOWN = -1, 24 AMDXDNA_DEV_TYPE_KMQ, 25 }; 26 27 enum amdxdna_drm_ioctl_id { 28 DRM_AMDXDNA_CREATE_HWCTX, 29 DRM_AMDXDNA_DESTROY_HWCTX, 30 DRM_AMDXDNA_CONFIG_HWCTX, 31 DRM_AMDXDNA_CREATE_BO, 32 DRM_AMDXDNA_GET_BO_INFO, 33 DRM_AMDXDNA_SYNC_BO, 34 DRM_AMDXDNA_EXEC_CMD, 35 DRM_AMDXDNA_GET_INFO, 36 DRM_AMDXDNA_SET_STATE, 37 }; 38 39 /** 40 * struct qos_info - QoS information for driver. 41 * @gops: Giga operations per second. 42 * @fps: Frames per second. 43 * @dma_bandwidth: DMA bandwidtha. 44 * @latency: Frame response latency. 45 * @frame_exec_time: Frame execution time. 46 * @priority: Request priority. 47 * 48 * User program can provide QoS hints to driver. 49 */ 50 struct amdxdna_qos_info { 51 __u32 gops; 52 __u32 fps; 53 __u32 dma_bandwidth; 54 __u32 latency; 55 __u32 frame_exec_time; 56 __u32 priority; 57 }; 58 59 /** 60 * struct amdxdna_drm_create_hwctx - Create hardware context. 61 * @ext: MBZ. 62 * @ext_flags: MBZ. 63 * @qos_p: Address of QoS info. 64 * @umq_bo: BO handle for user mode queue(UMQ). 65 * @log_buf_bo: BO handle for log buffer. 66 * @max_opc: Maximum operations per cycle. 67 * @num_tiles: Number of AIE tiles. 68 * @mem_size: Size of AIE tile memory. 69 * @umq_doorbell: Returned offset of doorbell associated with UMQ. 70 * @handle: Returned hardware context handle. 71 * @syncobj_handle: Returned syncobj handle for command completion. 72 */ 73 struct amdxdna_drm_create_hwctx { 74 __u64 ext; 75 __u64 ext_flags; 76 __u64 qos_p; 77 __u32 umq_bo; 78 __u32 log_buf_bo; 79 __u32 max_opc; 80 __u32 num_tiles; 81 __u32 mem_size; 82 __u32 umq_doorbell; 83 __u32 handle; 84 __u32 syncobj_handle; 85 }; 86 87 /** 88 * struct amdxdna_drm_destroy_hwctx - Destroy hardware context. 89 * @handle: Hardware context handle. 90 * @pad: MBZ. 91 */ 92 struct amdxdna_drm_destroy_hwctx { 93 __u32 handle; 94 __u32 pad; 95 }; 96 97 /** 98 * struct amdxdna_cu_config - configuration for one CU 99 * @cu_bo: CU configuration buffer bo handle. 100 * @cu_func: Function of a CU. 101 * @pad: MBZ. 102 */ 103 struct amdxdna_cu_config { 104 __u32 cu_bo; 105 __u8 cu_func; 106 __u8 pad[3]; 107 }; 108 109 /** 110 * struct amdxdna_hwctx_param_config_cu - configuration for CUs in hardware context 111 * @num_cus: Number of CUs to configure. 112 * @pad: MBZ. 113 * @cu_configs: Array of CU configurations of struct amdxdna_cu_config. 114 */ 115 struct amdxdna_hwctx_param_config_cu { 116 __u16 num_cus; 117 __u16 pad[3]; 118 struct amdxdna_cu_config cu_configs[] __counted_by(num_cus); 119 }; 120 121 enum amdxdna_drm_config_hwctx_param { 122 DRM_AMDXDNA_HWCTX_CONFIG_CU, 123 DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF, 124 DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF, 125 }; 126 127 /** 128 * struct amdxdna_drm_config_hwctx - Configure hardware context. 129 * @handle: hardware context handle. 130 * @param_type: Value in enum amdxdna_drm_config_hwctx_param. Specifies the 131 * structure passed in via param_val. 132 * @param_val: A structure specified by the param_type struct member. 133 * @param_val_size: Size of the parameter buffer pointed to by the param_val. 134 * If param_val is not a pointer, driver can ignore this. 135 * @pad: MBZ. 136 * 137 * Note: if the param_val is a pointer pointing to a buffer, the maximum size 138 * of the buffer is 4KiB(PAGE_SIZE). 139 */ 140 struct amdxdna_drm_config_hwctx { 141 __u32 handle; 142 __u32 param_type; 143 __u64 param_val; 144 __u32 param_val_size; 145 __u32 pad; 146 }; 147 148 enum amdxdna_bo_type { 149 AMDXDNA_BO_INVALID = 0, 150 AMDXDNA_BO_SHMEM, 151 AMDXDNA_BO_DEV_HEAP, 152 AMDXDNA_BO_DEV, 153 AMDXDNA_BO_CMD, 154 }; 155 156 /** 157 * struct amdxdna_drm_va_entry 158 * @vaddr: Virtual address. 159 * @len: Size of entry. 160 */ 161 struct amdxdna_drm_va_entry { 162 __u64 vaddr; 163 __u64 len; 164 }; 165 166 /** 167 * struct amdxdna_drm_va_tbl 168 * @dmabuf_fd: The fd of dmabuf. 169 * @num_entries: Number of va entries. 170 * @va_entries: Array of va entries. 171 * 172 * The input can be either a dmabuf fd or a virtual address entry table. 173 * When dmabuf_fd is used, num_entries must be zero. 174 */ 175 struct amdxdna_drm_va_tbl { 176 __s32 dmabuf_fd; 177 __u32 num_entries; 178 struct amdxdna_drm_va_entry va_entries[]; 179 }; 180 181 /** 182 * struct amdxdna_drm_create_bo - Create a buffer object. 183 * @flags: Buffer flags. MBZ. 184 * @vaddr: User VA of buffer if applied. MBZ. 185 * @size: Size in bytes. 186 * @type: Buffer type. 187 * @handle: Returned DRM buffer object handle. 188 */ 189 struct amdxdna_drm_create_bo { 190 __u64 flags; 191 __u64 vaddr; 192 __u64 size; 193 __u32 type; 194 __u32 handle; 195 }; 196 197 /** 198 * struct amdxdna_drm_get_bo_info - Get buffer object information. 199 * @ext: MBZ. 200 * @ext_flags: MBZ. 201 * @handle: DRM buffer object handle. 202 * @pad: MBZ. 203 * @map_offset: Returned DRM fake offset for mmap(). 204 * @vaddr: Returned user VA of buffer. 0 in case user needs mmap(). 205 * @xdna_addr: Returned XDNA device virtual address. 206 */ 207 struct amdxdna_drm_get_bo_info { 208 __u64 ext; 209 __u64 ext_flags; 210 __u32 handle; 211 __u32 pad; 212 __u64 map_offset; 213 __u64 vaddr; 214 __u64 xdna_addr; 215 }; 216 217 /** 218 * struct amdxdna_drm_sync_bo - Sync buffer object. 219 * @handle: Buffer object handle. 220 * @direction: Direction of sync, can be from device or to device. 221 * @offset: Offset in the buffer to sync. 222 * @size: Size in bytes. 223 */ 224 struct amdxdna_drm_sync_bo { 225 __u32 handle; 226 #define SYNC_DIRECT_TO_DEVICE 0U 227 #define SYNC_DIRECT_FROM_DEVICE 1U 228 __u32 direction; 229 __u64 offset; 230 __u64 size; 231 }; 232 233 enum amdxdna_cmd_type { 234 AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0, 235 AMDXDNA_CMD_SUBMIT_DEPENDENCY, 236 AMDXDNA_CMD_SUBMIT_SIGNAL, 237 }; 238 239 /** 240 * struct amdxdna_drm_exec_cmd - Execute command. 241 * @ext: MBZ. 242 * @ext_flags: MBZ. 243 * @hwctx: Hardware context handle. 244 * @type: One of command type in enum amdxdna_cmd_type. 245 * @cmd_handles: Array of command handles or the command handle itself 246 * in case of just one. 247 * @args: Array of arguments for all command handles. 248 * @cmd_count: Number of command handles in the cmd_handles array. 249 * @arg_count: Number of arguments in the args array. 250 * @seq: Returned sequence number for this command. 251 */ 252 struct amdxdna_drm_exec_cmd { 253 __u64 ext; 254 __u64 ext_flags; 255 __u32 hwctx; 256 __u32 type; 257 __u64 cmd_handles; 258 __u64 args; 259 __u32 cmd_count; 260 __u32 arg_count; 261 __u64 seq; 262 }; 263 264 /** 265 * struct amdxdna_drm_query_aie_status - Query the status of the AIE hardware 266 * @buffer: The user space buffer that will return the AIE status. 267 * @buffer_size: The size of the user space buffer. 268 * @cols_filled: A bitmap of AIE columns whose data has been returned in the buffer. 269 */ 270 struct amdxdna_drm_query_aie_status { 271 __u64 buffer; /* out */ 272 __u32 buffer_size; /* in */ 273 __u32 cols_filled; /* out */ 274 }; 275 276 /** 277 * struct amdxdna_drm_query_aie_version - Query the version of the AIE hardware 278 * @major: The major version number. 279 * @minor: The minor version number. 280 */ 281 struct amdxdna_drm_query_aie_version { 282 __u32 major; /* out */ 283 __u32 minor; /* out */ 284 }; 285 286 /** 287 * struct amdxdna_drm_query_aie_tile_metadata - Query the metadata of AIE tile (core, mem, shim) 288 * @row_count: The number of rows. 289 * @row_start: The starting row number. 290 * @dma_channel_count: The number of dma channels. 291 * @lock_count: The number of locks. 292 * @event_reg_count: The number of events. 293 * @pad: Structure padding. 294 */ 295 struct amdxdna_drm_query_aie_tile_metadata { 296 __u16 row_count; 297 __u16 row_start; 298 __u16 dma_channel_count; 299 __u16 lock_count; 300 __u16 event_reg_count; 301 __u16 pad[3]; 302 }; 303 304 /** 305 * struct amdxdna_drm_query_aie_metadata - Query the metadata of the AIE hardware 306 * @col_size: The size of a column in bytes. 307 * @cols: The total number of columns. 308 * @rows: The total number of rows. 309 * @version: The version of the AIE hardware. 310 * @core: The metadata for all core tiles. 311 * @mem: The metadata for all mem tiles. 312 * @shim: The metadata for all shim tiles. 313 */ 314 struct amdxdna_drm_query_aie_metadata { 315 __u32 col_size; 316 __u16 cols; 317 __u16 rows; 318 struct amdxdna_drm_query_aie_version version; 319 struct amdxdna_drm_query_aie_tile_metadata core; 320 struct amdxdna_drm_query_aie_tile_metadata mem; 321 struct amdxdna_drm_query_aie_tile_metadata shim; 322 }; 323 324 /** 325 * struct amdxdna_drm_query_clock - Metadata for a clock 326 * @name: The clock name. 327 * @freq_mhz: The clock frequency. 328 * @pad: Structure padding. 329 */ 330 struct amdxdna_drm_query_clock { 331 __u8 name[16]; 332 __u32 freq_mhz; 333 __u32 pad; 334 }; 335 336 /** 337 * struct amdxdna_drm_query_clock_metadata - Query metadata for clocks 338 * @mp_npu_clock: The metadata for MP-NPU clock. 339 * @h_clock: The metadata for H clock. 340 */ 341 struct amdxdna_drm_query_clock_metadata { 342 struct amdxdna_drm_query_clock mp_npu_clock; 343 struct amdxdna_drm_query_clock h_clock; 344 }; 345 346 enum amdxdna_sensor_type { 347 AMDXDNA_SENSOR_TYPE_POWER 348 }; 349 350 /** 351 * struct amdxdna_drm_query_sensor - The data for single sensor. 352 * @label: The name for a sensor. 353 * @input: The current value of the sensor. 354 * @max: The maximum value possible for the sensor. 355 * @average: The average value of the sensor. 356 * @highest: The highest recorded sensor value for this driver load for the sensor. 357 * @status: The sensor status. 358 * @units: The sensor units. 359 * @unitm: Translates value member variables into the correct unit via (pow(10, unitm) * value). 360 * @type: The sensor type from enum amdxdna_sensor_type. 361 * @pad: Structure padding. 362 */ 363 struct amdxdna_drm_query_sensor { 364 __u8 label[64]; 365 __u32 input; 366 __u32 max; 367 __u32 average; 368 __u32 highest; 369 __u8 status[64]; 370 __u8 units[16]; 371 __s8 unitm; 372 __u8 type; 373 __u8 pad[6]; 374 }; 375 376 /** 377 * struct amdxdna_drm_query_hwctx - The data for single context. 378 * @context_id: The ID for this context. 379 * @start_col: The starting column for the partition assigned to this context. 380 * @num_col: The number of columns in the partition assigned to this context. 381 * @pad: Structure padding. 382 * @pid: The Process ID of the process that created this context. 383 * @command_submissions: The number of commands submitted to this context. 384 * @command_completions: The number of commands completed by this context. 385 * @migrations: The number of times this context has been moved to a different partition. 386 * @preemptions: The number of times this context has been preempted by another context in the 387 * same partition. 388 * @errors: The errors for this context. 389 */ 390 struct amdxdna_drm_query_hwctx { 391 __u32 context_id; 392 __u32 start_col; 393 __u32 num_col; 394 __u32 pad; 395 __s64 pid; 396 __u64 command_submissions; 397 __u64 command_completions; 398 __u64 migrations; 399 __u64 preemptions; 400 __u64 errors; 401 }; 402 403 enum amdxdna_power_mode_type { 404 POWER_MODE_DEFAULT, /* Fallback to calculated DPM */ 405 POWER_MODE_LOW, /* Set frequency to lowest DPM */ 406 POWER_MODE_MEDIUM, /* Set frequency to medium DPM */ 407 POWER_MODE_HIGH, /* Set frequency to highest DPM */ 408 POWER_MODE_TURBO, /* Maximum power */ 409 }; 410 411 /** 412 * struct amdxdna_drm_get_power_mode - Get the configured power mode 413 * @power_mode: The mode type from enum amdxdna_power_mode_type 414 * @pad: Structure padding. 415 */ 416 struct amdxdna_drm_get_power_mode { 417 __u8 power_mode; 418 __u8 pad[7]; 419 }; 420 421 /** 422 * struct amdxdna_drm_query_firmware_version - Query the firmware version 423 * @major: The major version number 424 * @minor: The minor version number 425 * @patch: The patch level version number 426 * @build: The build ID 427 */ 428 struct amdxdna_drm_query_firmware_version { 429 __u32 major; /* out */ 430 __u32 minor; /* out */ 431 __u32 patch; /* out */ 432 __u32 build; /* out */ 433 }; 434 435 enum amdxdna_drm_get_param { 436 DRM_AMDXDNA_QUERY_AIE_STATUS, 437 DRM_AMDXDNA_QUERY_AIE_METADATA, 438 DRM_AMDXDNA_QUERY_AIE_VERSION, 439 DRM_AMDXDNA_QUERY_CLOCK_METADATA, 440 DRM_AMDXDNA_QUERY_SENSORS, 441 DRM_AMDXDNA_QUERY_HW_CONTEXTS, 442 DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8, 443 DRM_AMDXDNA_GET_POWER_MODE, 444 }; 445 446 /** 447 * struct amdxdna_drm_get_info - Get some information from the AIE hardware. 448 * @param: Value in enum amdxdna_drm_get_param. Specifies the structure passed in the buffer. 449 * @buffer_size: Size of the input buffer. Size needed/written by the kernel. 450 * @buffer: A structure specified by the param struct member. 451 */ 452 struct amdxdna_drm_get_info { 453 __u32 param; /* in */ 454 __u32 buffer_size; /* in/out */ 455 __u64 buffer; /* in/out */ 456 }; 457 458 enum amdxdna_drm_set_param { 459 DRM_AMDXDNA_SET_POWER_MODE, 460 DRM_AMDXDNA_WRITE_AIE_MEM, 461 DRM_AMDXDNA_WRITE_AIE_REG, 462 }; 463 464 /** 465 * struct amdxdna_drm_set_state - Set the state of the AIE hardware. 466 * @param: Value in enum amdxdna_drm_set_param. 467 * @buffer_size: Size of the input param. 468 * @buffer: Pointer to the input param. 469 */ 470 struct amdxdna_drm_set_state { 471 __u32 param; /* in */ 472 __u32 buffer_size; /* in */ 473 __u64 buffer; /* in */ 474 }; 475 476 /** 477 * struct amdxdna_drm_set_power_mode - Set the power mode of the AIE hardware 478 * @power_mode: The sensor type from enum amdxdna_power_mode_type 479 * @pad: MBZ. 480 */ 481 struct amdxdna_drm_set_power_mode { 482 __u8 power_mode; 483 __u8 pad[7]; 484 }; 485 486 #define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \ 487 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \ 488 struct amdxdna_drm_create_hwctx) 489 490 #define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \ 491 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \ 492 struct amdxdna_drm_destroy_hwctx) 493 494 #define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \ 495 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \ 496 struct amdxdna_drm_config_hwctx) 497 498 #define DRM_IOCTL_AMDXDNA_CREATE_BO \ 499 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \ 500 struct amdxdna_drm_create_bo) 501 502 #define DRM_IOCTL_AMDXDNA_GET_BO_INFO \ 503 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \ 504 struct amdxdna_drm_get_bo_info) 505 506 #define DRM_IOCTL_AMDXDNA_SYNC_BO \ 507 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \ 508 struct amdxdna_drm_sync_bo) 509 510 #define DRM_IOCTL_AMDXDNA_EXEC_CMD \ 511 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \ 512 struct amdxdna_drm_exec_cmd) 513 514 #define DRM_IOCTL_AMDXDNA_GET_INFO \ 515 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \ 516 struct amdxdna_drm_get_info) 517 518 #define DRM_IOCTL_AMDXDNA_SET_STATE \ 519 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \ 520 struct amdxdna_drm_set_state) 521 522 #if defined(__cplusplus) 523 } /* extern c end */ 524 #endif 525 526 #endif /* _UAPI_AMDXDNA_ACCEL_H_ */ 527