1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef _UAPI_AMDXDNA_ACCEL_H_ 7 #define _UAPI_AMDXDNA_ACCEL_H_ 8 9 #include <linux/stddef.h> 10 #include "drm.h" 11 12 #if defined(__cplusplus) 13 extern "C" { 14 #endif 15 16 #define AMDXDNA_INVALID_CMD_HANDLE (~0UL) 17 #define AMDXDNA_INVALID_ADDR (~0UL) 18 #define AMDXDNA_INVALID_CTX_HANDLE 0 19 #define AMDXDNA_INVALID_BO_HANDLE 0 20 #define AMDXDNA_INVALID_FENCE_HANDLE 0 21 22 /* 23 * Define hardware context priority 24 */ 25 #define AMDXDNA_QOS_REALTIME_PRIORITY 0x100 26 #define AMDXDNA_QOS_HIGH_PRIORITY 0x180 27 #define AMDXDNA_QOS_NORMAL_PRIORITY 0x200 28 #define AMDXDNA_QOS_LOW_PRIORITY 0x280 29 30 enum amdxdna_device_type { 31 AMDXDNA_DEV_TYPE_UNKNOWN = -1, 32 AMDXDNA_DEV_TYPE_KMQ, 33 }; 34 35 enum amdxdna_drm_ioctl_id { 36 DRM_AMDXDNA_CREATE_HWCTX, 37 DRM_AMDXDNA_DESTROY_HWCTX, 38 DRM_AMDXDNA_CONFIG_HWCTX, 39 DRM_AMDXDNA_CREATE_BO, 40 DRM_AMDXDNA_GET_BO_INFO, 41 DRM_AMDXDNA_SYNC_BO, 42 DRM_AMDXDNA_EXEC_CMD, 43 DRM_AMDXDNA_GET_INFO, 44 DRM_AMDXDNA_SET_STATE, 45 DRM_AMDXDNA_GET_ARRAY = 10, 46 }; 47 48 /** 49 * struct qos_info - QoS information for driver. 50 * @gops: Giga operations per second. 51 * @fps: Frames per second. 52 * @dma_bandwidth: DMA bandwidtha. 53 * @latency: Frame response latency. 54 * @frame_exec_time: Frame execution time. 55 * @priority: Request priority. 56 * 57 * User program can provide QoS hints to driver. 58 */ 59 struct amdxdna_qos_info { 60 __u32 gops; 61 __u32 fps; 62 __u32 dma_bandwidth; 63 __u32 latency; 64 __u32 frame_exec_time; 65 __u32 priority; 66 }; 67 68 /** 69 * struct amdxdna_drm_create_hwctx - Create hardware context. 70 * @ext: MBZ. 71 * @ext_flags: MBZ. 72 * @qos_p: Address of QoS info. 73 * @umq_bo: BO handle for user mode queue(UMQ). 74 * @log_buf_bo: BO handle for log buffer. 75 * @max_opc: Maximum operations per cycle. 76 * @num_tiles: Number of AIE tiles. 77 * @mem_size: Size of AIE tile memory. 78 * @umq_doorbell: Returned offset of doorbell associated with UMQ. 79 * @handle: Returned hardware context handle. 80 * @syncobj_handle: Returned syncobj handle for command completion. 81 */ 82 struct amdxdna_drm_create_hwctx { 83 __u64 ext; 84 __u64 ext_flags; 85 __u64 qos_p; 86 __u32 umq_bo; 87 __u32 log_buf_bo; 88 __u32 max_opc; 89 __u32 num_tiles; 90 __u32 mem_size; 91 __u32 umq_doorbell; 92 __u32 handle; 93 __u32 syncobj_handle; 94 }; 95 96 /** 97 * struct amdxdna_drm_destroy_hwctx - Destroy hardware context. 98 * @handle: Hardware context handle. 99 * @pad: MBZ. 100 */ 101 struct amdxdna_drm_destroy_hwctx { 102 __u32 handle; 103 __u32 pad; 104 }; 105 106 /** 107 * struct amdxdna_cu_config - configuration for one CU 108 * @cu_bo: CU configuration buffer bo handle. 109 * @cu_func: Function of a CU. 110 * @pad: MBZ. 111 */ 112 struct amdxdna_cu_config { 113 __u32 cu_bo; 114 __u8 cu_func; 115 __u8 pad[3]; 116 }; 117 118 /** 119 * struct amdxdna_hwctx_param_config_cu - configuration for CUs in hardware context 120 * @num_cus: Number of CUs to configure. 121 * @pad: MBZ. 122 * @cu_configs: Array of CU configurations of struct amdxdna_cu_config. 123 */ 124 struct amdxdna_hwctx_param_config_cu { 125 __u16 num_cus; 126 __u16 pad[3]; 127 struct amdxdna_cu_config cu_configs[] __counted_by(num_cus); 128 }; 129 130 enum amdxdna_drm_config_hwctx_param { 131 DRM_AMDXDNA_HWCTX_CONFIG_CU, 132 DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF, 133 DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF, 134 }; 135 136 /** 137 * struct amdxdna_drm_config_hwctx - Configure hardware context. 138 * @handle: hardware context handle. 139 * @param_type: Value in enum amdxdna_drm_config_hwctx_param. Specifies the 140 * structure passed in via param_val. 141 * @param_val: A structure specified by the param_type struct member. 142 * @param_val_size: Size of the parameter buffer pointed to by the param_val. 143 * If param_val is not a pointer, driver can ignore this. 144 * @pad: MBZ. 145 * 146 * Note: if the param_val is a pointer pointing to a buffer, the maximum size 147 * of the buffer is 4KiB(PAGE_SIZE). 148 */ 149 struct amdxdna_drm_config_hwctx { 150 __u32 handle; 151 __u32 param_type; 152 __u64 param_val; 153 __u32 param_val_size; 154 __u32 pad; 155 }; 156 157 enum amdxdna_bo_type { 158 AMDXDNA_BO_INVALID = 0, 159 AMDXDNA_BO_SHMEM, 160 AMDXDNA_BO_DEV_HEAP, 161 AMDXDNA_BO_DEV, 162 AMDXDNA_BO_CMD, 163 }; 164 165 /** 166 * struct amdxdna_drm_va_entry 167 * @vaddr: Virtual address. 168 * @len: Size of entry. 169 */ 170 struct amdxdna_drm_va_entry { 171 __u64 vaddr; 172 __u64 len; 173 }; 174 175 /** 176 * struct amdxdna_drm_va_tbl 177 * @dmabuf_fd: The fd of dmabuf. 178 * @num_entries: Number of va entries. 179 * @va_entries: Array of va entries. 180 * 181 * The input can be either a dmabuf fd or a virtual address entry table. 182 * When dmabuf_fd is used, num_entries must be zero. 183 */ 184 struct amdxdna_drm_va_tbl { 185 __s32 dmabuf_fd; 186 __u32 num_entries; 187 struct amdxdna_drm_va_entry va_entries[]; 188 }; 189 190 /** 191 * struct amdxdna_drm_create_bo - Create a buffer object. 192 * @flags: Buffer flags. MBZ. 193 * @vaddr: User VA of buffer if applied. MBZ. 194 * @size: Size in bytes. 195 * @type: Buffer type. 196 * @handle: Returned DRM buffer object handle. 197 */ 198 struct amdxdna_drm_create_bo { 199 __u64 flags; 200 __u64 vaddr; 201 __u64 size; 202 __u32 type; 203 __u32 handle; 204 }; 205 206 /** 207 * struct amdxdna_drm_get_bo_info - Get buffer object information. 208 * @ext: MBZ. 209 * @ext_flags: MBZ. 210 * @handle: DRM buffer object handle. 211 * @pad: MBZ. 212 * @map_offset: Returned DRM fake offset for mmap(). 213 * @vaddr: Returned user VA of buffer. 0 in case user needs mmap(). 214 * @xdna_addr: Returned XDNA device virtual address. 215 */ 216 struct amdxdna_drm_get_bo_info { 217 __u64 ext; 218 __u64 ext_flags; 219 __u32 handle; 220 __u32 pad; 221 __u64 map_offset; 222 __u64 vaddr; 223 __u64 xdna_addr; 224 }; 225 226 /** 227 * struct amdxdna_drm_sync_bo - Sync buffer object. 228 * @handle: Buffer object handle. 229 * @direction: Direction of sync, can be from device or to device. 230 * @offset: Offset in the buffer to sync. 231 * @size: Size in bytes. 232 */ 233 struct amdxdna_drm_sync_bo { 234 __u32 handle; 235 #define SYNC_DIRECT_TO_DEVICE 0U 236 #define SYNC_DIRECT_FROM_DEVICE 1U 237 __u32 direction; 238 __u64 offset; 239 __u64 size; 240 }; 241 242 enum amdxdna_cmd_type { 243 AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0, 244 AMDXDNA_CMD_SUBMIT_DEPENDENCY, 245 AMDXDNA_CMD_SUBMIT_SIGNAL, 246 }; 247 248 /** 249 * struct amdxdna_drm_exec_cmd - Execute command. 250 * @ext: MBZ. 251 * @ext_flags: MBZ. 252 * @hwctx: Hardware context handle. 253 * @type: One of command type in enum amdxdna_cmd_type. 254 * @cmd_handles: Array of command handles or the command handle itself 255 * in case of just one. 256 * @args: Array of arguments for all command handles. 257 * @cmd_count: Number of command handles in the cmd_handles array. 258 * @arg_count: Number of arguments in the args array. 259 * @seq: Returned sequence number for this command. 260 */ 261 struct amdxdna_drm_exec_cmd { 262 __u64 ext; 263 __u64 ext_flags; 264 __u32 hwctx; 265 __u32 type; 266 __u64 cmd_handles; 267 __u64 args; 268 __u32 cmd_count; 269 __u32 arg_count; 270 __u64 seq; 271 }; 272 273 /** 274 * struct amdxdna_drm_query_aie_status - Query the status of the AIE hardware 275 * @buffer: The user space buffer that will return the AIE status. 276 * @buffer_size: The size of the user space buffer. 277 * @cols_filled: A bitmap of AIE columns whose data has been returned in the buffer. 278 */ 279 struct amdxdna_drm_query_aie_status { 280 __u64 buffer; /* out */ 281 __u32 buffer_size; /* in */ 282 __u32 cols_filled; /* out */ 283 }; 284 285 /** 286 * struct amdxdna_drm_query_aie_version - Query the version of the AIE hardware 287 * @major: The major version number. 288 * @minor: The minor version number. 289 */ 290 struct amdxdna_drm_query_aie_version { 291 __u32 major; /* out */ 292 __u32 minor; /* out */ 293 }; 294 295 /** 296 * struct amdxdna_drm_query_aie_tile_metadata - Query the metadata of AIE tile (core, mem, shim) 297 * @row_count: The number of rows. 298 * @row_start: The starting row number. 299 * @dma_channel_count: The number of dma channels. 300 * @lock_count: The number of locks. 301 * @event_reg_count: The number of events. 302 * @pad: Structure padding. 303 */ 304 struct amdxdna_drm_query_aie_tile_metadata { 305 __u16 row_count; 306 __u16 row_start; 307 __u16 dma_channel_count; 308 __u16 lock_count; 309 __u16 event_reg_count; 310 __u16 pad[3]; 311 }; 312 313 /** 314 * struct amdxdna_drm_query_aie_metadata - Query the metadata of the AIE hardware 315 * @col_size: The size of a column in bytes. 316 * @cols: The total number of columns. 317 * @rows: The total number of rows. 318 * @version: The version of the AIE hardware. 319 * @core: The metadata for all core tiles. 320 * @mem: The metadata for all mem tiles. 321 * @shim: The metadata for all shim tiles. 322 */ 323 struct amdxdna_drm_query_aie_metadata { 324 __u32 col_size; 325 __u16 cols; 326 __u16 rows; 327 struct amdxdna_drm_query_aie_version version; 328 struct amdxdna_drm_query_aie_tile_metadata core; 329 struct amdxdna_drm_query_aie_tile_metadata mem; 330 struct amdxdna_drm_query_aie_tile_metadata shim; 331 }; 332 333 /** 334 * struct amdxdna_drm_query_clock - Metadata for a clock 335 * @name: The clock name. 336 * @freq_mhz: The clock frequency. 337 * @pad: Structure padding. 338 */ 339 struct amdxdna_drm_query_clock { 340 __u8 name[16]; 341 __u32 freq_mhz; 342 __u32 pad; 343 }; 344 345 /** 346 * struct amdxdna_drm_query_clock_metadata - Query metadata for clocks 347 * @mp_npu_clock: The metadata for MP-NPU clock. 348 * @h_clock: The metadata for H clock. 349 */ 350 struct amdxdna_drm_query_clock_metadata { 351 struct amdxdna_drm_query_clock mp_npu_clock; 352 struct amdxdna_drm_query_clock h_clock; 353 }; 354 355 enum amdxdna_sensor_type { 356 AMDXDNA_SENSOR_TYPE_POWER, 357 AMDXDNA_SENSOR_TYPE_COLUMN_UTILIZATION 358 }; 359 360 /** 361 * struct amdxdna_drm_query_sensor - The data for single sensor. 362 * @label: The name for a sensor. 363 * @input: The current value of the sensor. 364 * @max: The maximum value possible for the sensor. 365 * @average: The average value of the sensor. 366 * @highest: The highest recorded sensor value for this driver load for the sensor. 367 * @status: The sensor status. 368 * @units: The sensor units. 369 * @unitm: Translates value member variables into the correct unit via (pow(10, unitm) * value). 370 * @type: The sensor type from enum amdxdna_sensor_type. 371 * @pad: Structure padding. 372 */ 373 struct amdxdna_drm_query_sensor { 374 __u8 label[64]; 375 __u32 input; 376 __u32 max; 377 __u32 average; 378 __u32 highest; 379 __u8 status[64]; 380 __u8 units[16]; 381 __s8 unitm; 382 __u8 type; 383 __u8 pad[6]; 384 }; 385 386 /** 387 * struct amdxdna_drm_query_hwctx - The data for single context. 388 * @context_id: The ID for this context. 389 * @start_col: The starting column for the partition assigned to this context. 390 * @num_col: The number of columns in the partition assigned to this context. 391 * @pad: Structure padding. 392 * @pid: The Process ID of the process that created this context. 393 * @command_submissions: The number of commands submitted to this context. 394 * @command_completions: The number of commands completed by this context. 395 * @migrations: The number of times this context has been moved to a different partition. 396 * @preemptions: The number of times this context has been preempted by another context in the 397 * same partition. 398 * @errors: The errors for this context. 399 */ 400 struct amdxdna_drm_query_hwctx { 401 __u32 context_id; 402 __u32 start_col; 403 __u32 num_col; 404 __u32 pad; 405 __s64 pid; 406 __u64 command_submissions; 407 __u64 command_completions; 408 __u64 migrations; 409 __u64 preemptions; 410 __u64 errors; 411 }; 412 413 enum amdxdna_power_mode_type { 414 POWER_MODE_DEFAULT, /* Fallback to calculated DPM */ 415 POWER_MODE_LOW, /* Set frequency to lowest DPM */ 416 POWER_MODE_MEDIUM, /* Set frequency to medium DPM */ 417 POWER_MODE_HIGH, /* Set frequency to highest DPM */ 418 POWER_MODE_TURBO, /* Maximum power */ 419 }; 420 421 /** 422 * struct amdxdna_drm_get_power_mode - Get the configured power mode 423 * @power_mode: The mode type from enum amdxdna_power_mode_type 424 * @pad: Structure padding. 425 */ 426 struct amdxdna_drm_get_power_mode { 427 __u8 power_mode; 428 __u8 pad[7]; 429 }; 430 431 /** 432 * struct amdxdna_drm_query_firmware_version - Query the firmware version 433 * @major: The major version number 434 * @minor: The minor version number 435 * @patch: The patch level version number 436 * @build: The build ID 437 */ 438 struct amdxdna_drm_query_firmware_version { 439 __u32 major; /* out */ 440 __u32 minor; /* out */ 441 __u32 patch; /* out */ 442 __u32 build; /* out */ 443 }; 444 445 enum amdxdna_drm_get_param { 446 DRM_AMDXDNA_QUERY_AIE_STATUS, 447 DRM_AMDXDNA_QUERY_AIE_METADATA, 448 DRM_AMDXDNA_QUERY_AIE_VERSION, 449 DRM_AMDXDNA_QUERY_CLOCK_METADATA, 450 DRM_AMDXDNA_QUERY_SENSORS, 451 DRM_AMDXDNA_QUERY_HW_CONTEXTS, 452 DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8, 453 DRM_AMDXDNA_GET_POWER_MODE, 454 DRM_AMDXDNA_QUERY_TELEMETRY, 455 DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE, 456 DRM_AMDXDNA_QUERY_RESOURCE_INFO, 457 DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE, 458 }; 459 460 /** 461 * struct amdxdna_drm_get_resource_info - Get resource information 462 */ 463 struct amdxdna_drm_get_resource_info { 464 /** @npu_clk_max: max H-Clocks */ 465 __u64 npu_clk_max; 466 /** @npu_tops_max: max TOPs */ 467 __u64 npu_tops_max; 468 /** @npu_task_max: max number of tasks */ 469 __u64 npu_task_max; 470 /** @npu_tops_curr: current TOPs */ 471 __u64 npu_tops_curr; 472 /** @npu_task_curr: current number of tasks */ 473 __u64 npu_task_curr; 474 }; 475 476 /** 477 * struct amdxdna_drm_attribute_state - State of an attribute 478 */ 479 struct amdxdna_drm_attribute_state { 480 /** @state: enabled or disabled */ 481 __u8 state; 482 /** @pad: MBZ */ 483 __u8 pad[7]; 484 }; 485 486 /** 487 * struct amdxdna_drm_query_telemetry_header - Telemetry data header 488 */ 489 struct amdxdna_drm_query_telemetry_header { 490 /** @major: Firmware telemetry interface major version number */ 491 __u32 major; 492 /** @minor: Firmware telemetry interface minor version number */ 493 __u32 minor; 494 /** @type: Telemetry query type */ 495 __u32 type; 496 /** @map_num_elements: Total number of elements in the map table */ 497 __u32 map_num_elements; 498 /** @map: Element map */ 499 __u32 map[]; 500 }; 501 502 /** 503 * struct amdxdna_drm_get_info - Get some information from the AIE hardware. 504 * @param: Value in enum amdxdna_drm_get_param. Specifies the structure passed in the buffer. 505 * @buffer_size: Size of the input buffer. Size needed/written by the kernel. 506 * @buffer: A structure specified by the param struct member. 507 */ 508 struct amdxdna_drm_get_info { 509 __u32 param; /* in */ 510 __u32 buffer_size; /* in/out */ 511 __u64 buffer; /* in/out */ 512 }; 513 514 #define AMDXDNA_HWCTX_STATE_IDLE 0 515 #define AMDXDNA_HWCTX_STATE_ACTIVE 1 516 517 /** 518 * struct amdxdna_drm_hwctx_entry - The hardware context array entry 519 */ 520 struct amdxdna_drm_hwctx_entry { 521 /** @context_id: Context ID. */ 522 __u32 context_id; 523 /** @start_col: Start AIE array column assigned to context. */ 524 __u32 start_col; 525 /** @num_col: Number of AIE array columns assigned to context. */ 526 __u32 num_col; 527 /** @hwctx_id: The real hardware context id. */ 528 __u32 hwctx_id; 529 /** @pid: ID of process which created this context. */ 530 __s64 pid; 531 /** @command_submissions: Number of commands submitted. */ 532 __u64 command_submissions; 533 /** @command_completions: Number of commands completed. */ 534 __u64 command_completions; 535 /** @migrations: Number of times been migrated. */ 536 __u64 migrations; 537 /** @preemptions: Number of times been preempted. */ 538 __u64 preemptions; 539 /** @errors: Number of errors happened. */ 540 __u64 errors; 541 /** @priority: Context priority. */ 542 __u64 priority; 543 /** @heap_usage: Usage of device heap buffer. */ 544 __u64 heap_usage; 545 /** @suspensions: Number of times been suspended. */ 546 __u64 suspensions; 547 /** 548 * @state: Context state. 549 * %AMDXDNA_HWCTX_STATE_IDLE 550 * %AMDXDNA_HWCTX_STATE_ACTIVE 551 */ 552 __u32 state; 553 /** @pasid: PASID been bound. */ 554 __u32 pasid; 555 /** @gops: Giga operations per second. */ 556 __u32 gops; 557 /** @fps: Frames per second. */ 558 __u32 fps; 559 /** @dma_bandwidth: DMA bandwidth. */ 560 __u32 dma_bandwidth; 561 /** @latency: Frame response latency. */ 562 __u32 latency; 563 /** @frame_exec_time: Frame execution time. */ 564 __u32 frame_exec_time; 565 /** @txn_op_idx: Index of last control code executed. */ 566 __u32 txn_op_idx; 567 /** @ctx_pc: Program counter. */ 568 __u32 ctx_pc; 569 /** @fatal_error_type: Fatal error type if context crashes. */ 570 __u32 fatal_error_type; 571 /** @fatal_error_exception_type: Firmware exception type. */ 572 __u32 fatal_error_exception_type; 573 /** @fatal_error_exception_pc: Firmware exception program counter. */ 574 __u32 fatal_error_exception_pc; 575 /** @fatal_error_app_module: Exception module name. */ 576 __u32 fatal_error_app_module; 577 /** @pad: Structure pad. */ 578 __u32 pad; 579 }; 580 581 /** 582 * struct amdxdna_async_error - XDNA async error structure 583 */ 584 struct amdxdna_async_error { 585 /** @err_code: Error code. */ 586 __u64 err_code; 587 /** @ts_us: Timestamp. */ 588 __u64 ts_us; 589 /** @ex_err_code: Extra error code */ 590 __u64 ex_err_code; 591 }; 592 593 #define DRM_AMDXDNA_HW_CONTEXT_ALL 0 594 #define DRM_AMDXDNA_HW_LAST_ASYNC_ERR 2 595 596 /** 597 * struct amdxdna_drm_get_array - Get information array. 598 */ 599 struct amdxdna_drm_get_array { 600 /** 601 * @param: 602 * 603 * Supported params: 604 * 605 * %DRM_AMDXDNA_HW_CONTEXT_ALL: 606 * Returns all created hardware contexts. 607 */ 608 __u32 param; 609 /** 610 * @element_size: 611 * 612 * Specifies maximum element size and returns the actual element size. 613 */ 614 __u32 element_size; 615 /** 616 * @num_element: 617 * 618 * Specifies maximum number of elements and returns the actual number 619 * of elements. 620 */ 621 __u32 num_element; /* in/out */ 622 /** @pad: MBZ */ 623 __u32 pad; 624 /** 625 * @buffer: 626 * 627 * Specifies the match conditions and returns the matched information 628 * array. 629 */ 630 __u64 buffer; 631 }; 632 633 enum amdxdna_drm_set_param { 634 DRM_AMDXDNA_SET_POWER_MODE, 635 DRM_AMDXDNA_WRITE_AIE_MEM, 636 DRM_AMDXDNA_WRITE_AIE_REG, 637 DRM_AMDXDNA_SET_FORCE_PREEMPT, 638 DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT, 639 }; 640 641 /** 642 * struct amdxdna_drm_set_state - Set the state of the AIE hardware. 643 * @param: Value in enum amdxdna_drm_set_param. 644 * @buffer_size: Size of the input param. 645 * @buffer: Pointer to the input param. 646 */ 647 struct amdxdna_drm_set_state { 648 __u32 param; /* in */ 649 __u32 buffer_size; /* in */ 650 __u64 buffer; /* in */ 651 }; 652 653 /** 654 * struct amdxdna_drm_set_power_mode - Set the power mode of the AIE hardware 655 * @power_mode: The sensor type from enum amdxdna_power_mode_type 656 * @pad: MBZ. 657 */ 658 struct amdxdna_drm_set_power_mode { 659 __u8 power_mode; 660 __u8 pad[7]; 661 }; 662 663 #define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \ 664 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \ 665 struct amdxdna_drm_create_hwctx) 666 667 #define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \ 668 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \ 669 struct amdxdna_drm_destroy_hwctx) 670 671 #define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \ 672 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \ 673 struct amdxdna_drm_config_hwctx) 674 675 #define DRM_IOCTL_AMDXDNA_CREATE_BO \ 676 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \ 677 struct amdxdna_drm_create_bo) 678 679 #define DRM_IOCTL_AMDXDNA_GET_BO_INFO \ 680 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \ 681 struct amdxdna_drm_get_bo_info) 682 683 #define DRM_IOCTL_AMDXDNA_SYNC_BO \ 684 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \ 685 struct amdxdna_drm_sync_bo) 686 687 #define DRM_IOCTL_AMDXDNA_EXEC_CMD \ 688 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \ 689 struct amdxdna_drm_exec_cmd) 690 691 #define DRM_IOCTL_AMDXDNA_GET_INFO \ 692 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \ 693 struct amdxdna_drm_get_info) 694 695 #define DRM_IOCTL_AMDXDNA_SET_STATE \ 696 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \ 697 struct amdxdna_drm_set_state) 698 699 #define DRM_IOCTL_AMDXDNA_GET_ARRAY \ 700 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_ARRAY, \ 701 struct amdxdna_drm_get_array) 702 703 #if defined(__cplusplus) 704 } /* extern c end */ 705 #endif 706 707 #endif /* _UAPI_AMDXDNA_ACCEL_H_ */ 708