1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 56 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 57 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 58 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 59 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 60 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 61 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 62 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 63 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 64 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 65 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 66 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 67 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 68 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 69 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 70 71 #define AMDGPU_GEM_DOMAIN_CPU 0x1 72 #define AMDGPU_GEM_DOMAIN_GTT 0x2 73 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 74 #define AMDGPU_GEM_DOMAIN_GDS 0x8 75 #define AMDGPU_GEM_DOMAIN_GWS 0x10 76 #define AMDGPU_GEM_DOMAIN_OA 0x20 77 78 /* Flag that CPU access will be required for the case of VRAM domain */ 79 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 80 /* Flag that CPU access will not work, this VRAM domain is invisible */ 81 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 82 /* Flag that USWC attributes should be used for GTT */ 83 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 84 /* Flag that the memory should be in VRAM and cleared */ 85 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 86 /* Flag that create shadow bo(GTT) while allocating vram bo */ 87 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 88 /* Flag that allocating the BO should use linear VRAM */ 89 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 90 /* Flag that BO is always valid in this VM */ 91 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 92 93 struct drm_amdgpu_gem_create_in { 94 /** the requested memory size */ 95 __u64 bo_size; 96 /** physical start_addr alignment in bytes for some HW requirements */ 97 __u64 alignment; 98 /** the requested memory domains */ 99 __u64 domains; 100 /** allocation flags */ 101 __u64 domain_flags; 102 }; 103 104 struct drm_amdgpu_gem_create_out { 105 /** returned GEM object handle */ 106 __u32 handle; 107 __u32 _pad; 108 }; 109 110 union drm_amdgpu_gem_create { 111 struct drm_amdgpu_gem_create_in in; 112 struct drm_amdgpu_gem_create_out out; 113 }; 114 115 /** Opcode to create new residency list. */ 116 #define AMDGPU_BO_LIST_OP_CREATE 0 117 /** Opcode to destroy previously created residency list */ 118 #define AMDGPU_BO_LIST_OP_DESTROY 1 119 /** Opcode to update resource information in the list */ 120 #define AMDGPU_BO_LIST_OP_UPDATE 2 121 122 struct drm_amdgpu_bo_list_in { 123 /** Type of operation */ 124 __u32 operation; 125 /** Handle of list or 0 if we want to create one */ 126 __u32 list_handle; 127 /** Number of BOs in list */ 128 __u32 bo_number; 129 /** Size of each element describing BO */ 130 __u32 bo_info_size; 131 /** Pointer to array describing BOs */ 132 __u64 bo_info_ptr; 133 }; 134 135 struct drm_amdgpu_bo_list_entry { 136 /** Handle of BO */ 137 __u32 bo_handle; 138 /** New (if specified) BO priority to be used during migration */ 139 __u32 bo_priority; 140 }; 141 142 struct drm_amdgpu_bo_list_out { 143 /** Handle of resource list */ 144 __u32 list_handle; 145 __u32 _pad; 146 }; 147 148 union drm_amdgpu_bo_list { 149 struct drm_amdgpu_bo_list_in in; 150 struct drm_amdgpu_bo_list_out out; 151 }; 152 153 /* context related */ 154 #define AMDGPU_CTX_OP_ALLOC_CTX 1 155 #define AMDGPU_CTX_OP_FREE_CTX 2 156 #define AMDGPU_CTX_OP_QUERY_STATE 3 157 158 /* GPU reset status */ 159 #define AMDGPU_CTX_NO_RESET 0 160 /* this the context caused it */ 161 #define AMDGPU_CTX_GUILTY_RESET 1 162 /* some other context caused it */ 163 #define AMDGPU_CTX_INNOCENT_RESET 2 164 /* unknown cause */ 165 #define AMDGPU_CTX_UNKNOWN_RESET 3 166 167 struct drm_amdgpu_ctx_in { 168 /** AMDGPU_CTX_OP_* */ 169 __u32 op; 170 /** For future use, no flags defined so far */ 171 __u32 flags; 172 __u32 ctx_id; 173 __u32 _pad; 174 }; 175 176 union drm_amdgpu_ctx_out { 177 struct { 178 __u32 ctx_id; 179 __u32 _pad; 180 } alloc; 181 182 struct { 183 /** For future use, no flags defined so far */ 184 __u64 flags; 185 /** Number of resets caused by this context so far. */ 186 __u32 hangs; 187 /** Reset status since the last call of the ioctl. */ 188 __u32 reset_status; 189 } state; 190 }; 191 192 union drm_amdgpu_ctx { 193 struct drm_amdgpu_ctx_in in; 194 union drm_amdgpu_ctx_out out; 195 }; 196 197 /* vm ioctl */ 198 #define AMDGPU_VM_OP_RESERVE_VMID 1 199 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 200 201 struct drm_amdgpu_vm_in { 202 /** AMDGPU_VM_OP_* */ 203 __u32 op; 204 __u32 flags; 205 }; 206 207 struct drm_amdgpu_vm_out { 208 /** For future use, no flags defined so far */ 209 __u64 flags; 210 }; 211 212 union drm_amdgpu_vm { 213 struct drm_amdgpu_vm_in in; 214 struct drm_amdgpu_vm_out out; 215 }; 216 217 /* 218 * This is not a reliable API and you should expect it to fail for any 219 * number of reasons and have fallback path that do not use userptr to 220 * perform any operation. 221 */ 222 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 223 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 224 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 225 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 226 227 struct drm_amdgpu_gem_userptr { 228 __u64 addr; 229 __u64 size; 230 /* AMDGPU_GEM_USERPTR_* */ 231 __u32 flags; 232 /* Resulting GEM handle */ 233 __u32 handle; 234 }; 235 236 /* SI-CI-VI: */ 237 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 238 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 239 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 240 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 241 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 242 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 243 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 244 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 245 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 246 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 247 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 248 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 249 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 250 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 251 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 252 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 253 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 254 255 /* GFX9 and later: */ 256 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 257 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 258 259 /* Set/Get helpers for tiling flags. */ 260 #define AMDGPU_TILING_SET(field, value) \ 261 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 262 #define AMDGPU_TILING_GET(value, field) \ 263 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 264 265 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 266 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 267 268 /** The same structure is shared for input/output */ 269 struct drm_amdgpu_gem_metadata { 270 /** GEM Object handle */ 271 __u32 handle; 272 /** Do we want get or set metadata */ 273 __u32 op; 274 struct { 275 /** For future use, no flags defined so far */ 276 __u64 flags; 277 /** family specific tiling info */ 278 __u64 tiling_info; 279 __u32 data_size_bytes; 280 __u32 data[64]; 281 } data; 282 }; 283 284 struct drm_amdgpu_gem_mmap_in { 285 /** the GEM object handle */ 286 __u32 handle; 287 __u32 _pad; 288 }; 289 290 struct drm_amdgpu_gem_mmap_out { 291 /** mmap offset from the vma offset manager */ 292 __u64 addr_ptr; 293 }; 294 295 union drm_amdgpu_gem_mmap { 296 struct drm_amdgpu_gem_mmap_in in; 297 struct drm_amdgpu_gem_mmap_out out; 298 }; 299 300 struct drm_amdgpu_gem_wait_idle_in { 301 /** GEM object handle */ 302 __u32 handle; 303 /** For future use, no flags defined so far */ 304 __u32 flags; 305 /** Absolute timeout to wait */ 306 __u64 timeout; 307 }; 308 309 struct drm_amdgpu_gem_wait_idle_out { 310 /** BO status: 0 - BO is idle, 1 - BO is busy */ 311 __u32 status; 312 /** Returned current memory domain */ 313 __u32 domain; 314 }; 315 316 union drm_amdgpu_gem_wait_idle { 317 struct drm_amdgpu_gem_wait_idle_in in; 318 struct drm_amdgpu_gem_wait_idle_out out; 319 }; 320 321 struct drm_amdgpu_wait_cs_in { 322 /* Command submission handle 323 * handle equals 0 means none to wait for 324 * handle equals ~0ull means wait for the latest sequence number 325 */ 326 __u64 handle; 327 /** Absolute timeout to wait */ 328 __u64 timeout; 329 __u32 ip_type; 330 __u32 ip_instance; 331 __u32 ring; 332 __u32 ctx_id; 333 }; 334 335 struct drm_amdgpu_wait_cs_out { 336 /** CS status: 0 - CS completed, 1 - CS still busy */ 337 __u64 status; 338 }; 339 340 union drm_amdgpu_wait_cs { 341 struct drm_amdgpu_wait_cs_in in; 342 struct drm_amdgpu_wait_cs_out out; 343 }; 344 345 struct drm_amdgpu_fence { 346 __u32 ctx_id; 347 __u32 ip_type; 348 __u32 ip_instance; 349 __u32 ring; 350 __u64 seq_no; 351 }; 352 353 struct drm_amdgpu_wait_fences_in { 354 /** This points to uint64_t * which points to fences */ 355 __u64 fences; 356 __u32 fence_count; 357 __u32 wait_all; 358 __u64 timeout_ns; 359 }; 360 361 struct drm_amdgpu_wait_fences_out { 362 __u32 status; 363 __u32 first_signaled; 364 }; 365 366 union drm_amdgpu_wait_fences { 367 struct drm_amdgpu_wait_fences_in in; 368 struct drm_amdgpu_wait_fences_out out; 369 }; 370 371 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 372 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 373 374 /* Sets or returns a value associated with a buffer. */ 375 struct drm_amdgpu_gem_op { 376 /** GEM object handle */ 377 __u32 handle; 378 /** AMDGPU_GEM_OP_* */ 379 __u32 op; 380 /** Input or return value */ 381 __u64 value; 382 }; 383 384 #define AMDGPU_VA_OP_MAP 1 385 #define AMDGPU_VA_OP_UNMAP 2 386 #define AMDGPU_VA_OP_CLEAR 3 387 #define AMDGPU_VA_OP_REPLACE 4 388 389 /* Delay the page table update till the next CS */ 390 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 391 392 /* Mapping flags */ 393 /* readable mapping */ 394 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 395 /* writable mapping */ 396 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 397 /* executable mapping, new for VI */ 398 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 399 /* partially resident texture */ 400 #define AMDGPU_VM_PAGE_PRT (1 << 4) 401 /* MTYPE flags use bit 5 to 8 */ 402 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 403 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 404 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 405 /* Use NC MTYPE instead of default MTYPE */ 406 #define AMDGPU_VM_MTYPE_NC (1 << 5) 407 /* Use WC MTYPE instead of default MTYPE */ 408 #define AMDGPU_VM_MTYPE_WC (2 << 5) 409 /* Use CC MTYPE instead of default MTYPE */ 410 #define AMDGPU_VM_MTYPE_CC (3 << 5) 411 /* Use UC MTYPE instead of default MTYPE */ 412 #define AMDGPU_VM_MTYPE_UC (4 << 5) 413 414 struct drm_amdgpu_gem_va { 415 /** GEM object handle */ 416 __u32 handle; 417 __u32 _pad; 418 /** AMDGPU_VA_OP_* */ 419 __u32 operation; 420 /** AMDGPU_VM_PAGE_* */ 421 __u32 flags; 422 /** va address to assign . Must be correctly aligned.*/ 423 __u64 va_address; 424 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 425 __u64 offset_in_bo; 426 /** Specify mapping size. Must be correctly aligned. */ 427 __u64 map_size; 428 }; 429 430 #define AMDGPU_HW_IP_GFX 0 431 #define AMDGPU_HW_IP_COMPUTE 1 432 #define AMDGPU_HW_IP_DMA 2 433 #define AMDGPU_HW_IP_UVD 3 434 #define AMDGPU_HW_IP_VCE 4 435 #define AMDGPU_HW_IP_UVD_ENC 5 436 #define AMDGPU_HW_IP_VCN_DEC 6 437 #define AMDGPU_HW_IP_VCN_ENC 7 438 #define AMDGPU_HW_IP_NUM 8 439 440 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 441 442 #define AMDGPU_CHUNK_ID_IB 0x01 443 #define AMDGPU_CHUNK_ID_FENCE 0x02 444 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 445 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 446 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 447 448 struct drm_amdgpu_cs_chunk { 449 __u32 chunk_id; 450 __u32 length_dw; 451 __u64 chunk_data; 452 }; 453 454 struct drm_amdgpu_cs_in { 455 /** Rendering context id */ 456 __u32 ctx_id; 457 /** Handle of resource list associated with CS */ 458 __u32 bo_list_handle; 459 __u32 num_chunks; 460 __u32 _pad; 461 /** this points to __u64 * which point to cs chunks */ 462 __u64 chunks; 463 }; 464 465 struct drm_amdgpu_cs_out { 466 __u64 handle; 467 }; 468 469 union drm_amdgpu_cs { 470 struct drm_amdgpu_cs_in in; 471 struct drm_amdgpu_cs_out out; 472 }; 473 474 /* Specify flags to be used for IB */ 475 476 /* This IB should be submitted to CE */ 477 #define AMDGPU_IB_FLAG_CE (1<<0) 478 479 /* Preamble flag, which means the IB could be dropped if no context switch */ 480 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 481 482 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 483 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 484 485 struct drm_amdgpu_cs_chunk_ib { 486 __u32 _pad; 487 /** AMDGPU_IB_FLAG_* */ 488 __u32 flags; 489 /** Virtual address to begin IB execution */ 490 __u64 va_start; 491 /** Size of submission */ 492 __u32 ib_bytes; 493 /** HW IP to submit to */ 494 __u32 ip_type; 495 /** HW IP index of the same type to submit to */ 496 __u32 ip_instance; 497 /** Ring index to submit to */ 498 __u32 ring; 499 }; 500 501 struct drm_amdgpu_cs_chunk_dep { 502 __u32 ip_type; 503 __u32 ip_instance; 504 __u32 ring; 505 __u32 ctx_id; 506 __u64 handle; 507 }; 508 509 struct drm_amdgpu_cs_chunk_fence { 510 __u32 handle; 511 __u32 offset; 512 }; 513 514 struct drm_amdgpu_cs_chunk_sem { 515 __u32 handle; 516 }; 517 518 struct drm_amdgpu_cs_chunk_data { 519 union { 520 struct drm_amdgpu_cs_chunk_ib ib_data; 521 struct drm_amdgpu_cs_chunk_fence fence_data; 522 }; 523 }; 524 525 /** 526 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 527 * 528 */ 529 #define AMDGPU_IDS_FLAGS_FUSION 0x1 530 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 531 532 /* indicate if acceleration can be working */ 533 #define AMDGPU_INFO_ACCEL_WORKING 0x00 534 /* get the crtc_id from the mode object id? */ 535 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 536 /* query hw IP info */ 537 #define AMDGPU_INFO_HW_IP_INFO 0x02 538 /* query hw IP instance count for the specified type */ 539 #define AMDGPU_INFO_HW_IP_COUNT 0x03 540 /* timestamp for GL_ARB_timer_query */ 541 #define AMDGPU_INFO_TIMESTAMP 0x05 542 /* Query the firmware version */ 543 #define AMDGPU_INFO_FW_VERSION 0x0e 544 /* Subquery id: Query VCE firmware version */ 545 #define AMDGPU_INFO_FW_VCE 0x1 546 /* Subquery id: Query UVD firmware version */ 547 #define AMDGPU_INFO_FW_UVD 0x2 548 /* Subquery id: Query GMC firmware version */ 549 #define AMDGPU_INFO_FW_GMC 0x03 550 /* Subquery id: Query GFX ME firmware version */ 551 #define AMDGPU_INFO_FW_GFX_ME 0x04 552 /* Subquery id: Query GFX PFP firmware version */ 553 #define AMDGPU_INFO_FW_GFX_PFP 0x05 554 /* Subquery id: Query GFX CE firmware version */ 555 #define AMDGPU_INFO_FW_GFX_CE 0x06 556 /* Subquery id: Query GFX RLC firmware version */ 557 #define AMDGPU_INFO_FW_GFX_RLC 0x07 558 /* Subquery id: Query GFX MEC firmware version */ 559 #define AMDGPU_INFO_FW_GFX_MEC 0x08 560 /* Subquery id: Query SMC firmware version */ 561 #define AMDGPU_INFO_FW_SMC 0x0a 562 /* Subquery id: Query SDMA firmware version */ 563 #define AMDGPU_INFO_FW_SDMA 0x0b 564 /* Subquery id: Query PSP SOS firmware version */ 565 #define AMDGPU_INFO_FW_SOS 0x0c 566 /* Subquery id: Query PSP ASD firmware version */ 567 #define AMDGPU_INFO_FW_ASD 0x0d 568 /* number of bytes moved for TTM migration */ 569 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 570 /* the used VRAM size */ 571 #define AMDGPU_INFO_VRAM_USAGE 0x10 572 /* the used GTT size */ 573 #define AMDGPU_INFO_GTT_USAGE 0x11 574 /* Information about GDS, etc. resource configuration */ 575 #define AMDGPU_INFO_GDS_CONFIG 0x13 576 /* Query information about VRAM and GTT domains */ 577 #define AMDGPU_INFO_VRAM_GTT 0x14 578 /* Query information about register in MMR address space*/ 579 #define AMDGPU_INFO_READ_MMR_REG 0x15 580 /* Query information about device: rev id, family, etc. */ 581 #define AMDGPU_INFO_DEV_INFO 0x16 582 /* visible vram usage */ 583 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 584 /* number of TTM buffer evictions */ 585 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 586 /* Query memory about VRAM and GTT domains */ 587 #define AMDGPU_INFO_MEMORY 0x19 588 /* Query vce clock table */ 589 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 590 /* Query vbios related information */ 591 #define AMDGPU_INFO_VBIOS 0x1B 592 /* Subquery id: Query vbios size */ 593 #define AMDGPU_INFO_VBIOS_SIZE 0x1 594 /* Subquery id: Query vbios image */ 595 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 596 /* Query UVD handles */ 597 #define AMDGPU_INFO_NUM_HANDLES 0x1C 598 /* Query sensor related information */ 599 #define AMDGPU_INFO_SENSOR 0x1D 600 /* Subquery id: Query GPU shader clock */ 601 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 602 /* Subquery id: Query GPU memory clock */ 603 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 604 /* Subquery id: Query GPU temperature */ 605 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 606 /* Subquery id: Query GPU load */ 607 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 608 /* Subquery id: Query average GPU power */ 609 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 610 /* Subquery id: Query northbridge voltage */ 611 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 612 /* Subquery id: Query graphics voltage */ 613 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 614 /* Number of VRAM page faults on CPU access. */ 615 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 616 617 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 618 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 619 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 620 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 621 622 struct drm_amdgpu_query_fw { 623 /** AMDGPU_INFO_FW_* */ 624 __u32 fw_type; 625 /** 626 * Index of the IP if there are more IPs of 627 * the same type. 628 */ 629 __u32 ip_instance; 630 /** 631 * Index of the engine. Whether this is used depends 632 * on the firmware type. (e.g. MEC, SDMA) 633 */ 634 __u32 index; 635 __u32 _pad; 636 }; 637 638 /* Input structure for the INFO ioctl */ 639 struct drm_amdgpu_info { 640 /* Where the return value will be stored */ 641 __u64 return_pointer; 642 /* The size of the return value. Just like "size" in "snprintf", 643 * it limits how many bytes the kernel can write. */ 644 __u32 return_size; 645 /* The query request id. */ 646 __u32 query; 647 648 union { 649 struct { 650 __u32 id; 651 __u32 _pad; 652 } mode_crtc; 653 654 struct { 655 /** AMDGPU_HW_IP_* */ 656 __u32 type; 657 /** 658 * Index of the IP if there are more IPs of the same 659 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 660 */ 661 __u32 ip_instance; 662 } query_hw_ip; 663 664 struct { 665 __u32 dword_offset; 666 /** number of registers to read */ 667 __u32 count; 668 __u32 instance; 669 /** For future use, no flags defined so far */ 670 __u32 flags; 671 } read_mmr_reg; 672 673 struct drm_amdgpu_query_fw query_fw; 674 675 struct { 676 __u32 type; 677 __u32 offset; 678 } vbios_info; 679 680 struct { 681 __u32 type; 682 } sensor_info; 683 }; 684 }; 685 686 struct drm_amdgpu_info_gds { 687 /** GDS GFX partition size */ 688 __u32 gds_gfx_partition_size; 689 /** GDS compute partition size */ 690 __u32 compute_partition_size; 691 /** total GDS memory size */ 692 __u32 gds_total_size; 693 /** GWS size per GFX partition */ 694 __u32 gws_per_gfx_partition; 695 /** GSW size per compute partition */ 696 __u32 gws_per_compute_partition; 697 /** OA size per GFX partition */ 698 __u32 oa_per_gfx_partition; 699 /** OA size per compute partition */ 700 __u32 oa_per_compute_partition; 701 __u32 _pad; 702 }; 703 704 struct drm_amdgpu_info_vram_gtt { 705 __u64 vram_size; 706 __u64 vram_cpu_accessible_size; 707 __u64 gtt_size; 708 }; 709 710 struct drm_amdgpu_heap_info { 711 /** max. physical memory */ 712 __u64 total_heap_size; 713 714 /** Theoretical max. available memory in the given heap */ 715 __u64 usable_heap_size; 716 717 /** 718 * Number of bytes allocated in the heap. This includes all processes 719 * and private allocations in the kernel. It changes when new buffers 720 * are allocated, freed, and moved. It cannot be larger than 721 * heap_size. 722 */ 723 __u64 heap_usage; 724 725 /** 726 * Theoretical possible max. size of buffer which 727 * could be allocated in the given heap 728 */ 729 __u64 max_allocation; 730 }; 731 732 struct drm_amdgpu_memory_info { 733 struct drm_amdgpu_heap_info vram; 734 struct drm_amdgpu_heap_info cpu_accessible_vram; 735 struct drm_amdgpu_heap_info gtt; 736 }; 737 738 struct drm_amdgpu_info_firmware { 739 __u32 ver; 740 __u32 feature; 741 }; 742 743 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 744 #define AMDGPU_VRAM_TYPE_GDDR1 1 745 #define AMDGPU_VRAM_TYPE_DDR2 2 746 #define AMDGPU_VRAM_TYPE_GDDR3 3 747 #define AMDGPU_VRAM_TYPE_GDDR4 4 748 #define AMDGPU_VRAM_TYPE_GDDR5 5 749 #define AMDGPU_VRAM_TYPE_HBM 6 750 #define AMDGPU_VRAM_TYPE_DDR3 7 751 752 struct drm_amdgpu_info_device { 753 /** PCI Device ID */ 754 __u32 device_id; 755 /** Internal chip revision: A0, A1, etc.) */ 756 __u32 chip_rev; 757 __u32 external_rev; 758 /** Revision id in PCI Config space */ 759 __u32 pci_rev; 760 __u32 family; 761 __u32 num_shader_engines; 762 __u32 num_shader_arrays_per_engine; 763 /* in KHz */ 764 __u32 gpu_counter_freq; 765 __u64 max_engine_clock; 766 __u64 max_memory_clock; 767 /* cu information */ 768 __u32 cu_active_number; 769 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 770 __u32 cu_ao_mask; 771 __u32 cu_bitmap[4][4]; 772 /** Render backend pipe mask. One render backend is CB+DB. */ 773 __u32 enabled_rb_pipes_mask; 774 __u32 num_rb_pipes; 775 __u32 num_hw_gfx_contexts; 776 __u32 _pad; 777 __u64 ids_flags; 778 /** Starting virtual address for UMDs. */ 779 __u64 virtual_address_offset; 780 /** The maximum virtual address */ 781 __u64 virtual_address_max; 782 /** Required alignment of virtual addresses. */ 783 __u32 virtual_address_alignment; 784 /** Page table entry - fragment size */ 785 __u32 pte_fragment_size; 786 __u32 gart_page_size; 787 /** constant engine ram size*/ 788 __u32 ce_ram_size; 789 /** video memory type info*/ 790 __u32 vram_type; 791 /** video memory bit width*/ 792 __u32 vram_bit_width; 793 /* vce harvesting instance */ 794 __u32 vce_harvest_config; 795 /* gfx double offchip LDS buffers */ 796 __u32 gc_double_offchip_lds_buf; 797 /* NGG Primitive Buffer */ 798 __u64 prim_buf_gpu_addr; 799 /* NGG Position Buffer */ 800 __u64 pos_buf_gpu_addr; 801 /* NGG Control Sideband */ 802 __u64 cntl_sb_buf_gpu_addr; 803 /* NGG Parameter Cache */ 804 __u64 param_buf_gpu_addr; 805 __u32 prim_buf_size; 806 __u32 pos_buf_size; 807 __u32 cntl_sb_buf_size; 808 __u32 param_buf_size; 809 /* wavefront size*/ 810 __u32 wave_front_size; 811 /* shader visible vgprs*/ 812 __u32 num_shader_visible_vgprs; 813 /* CU per shader array*/ 814 __u32 num_cu_per_sh; 815 /* number of tcc blocks*/ 816 __u32 num_tcc_blocks; 817 /* gs vgt table depth*/ 818 __u32 gs_vgt_table_depth; 819 /* gs primitive buffer depth*/ 820 __u32 gs_prim_buffer_depth; 821 /* max gs wavefront per vgt*/ 822 __u32 max_gs_waves_per_vgt; 823 __u32 _pad1; 824 /* always on cu bitmap */ 825 __u32 cu_ao_bitmap[4][4]; 826 }; 827 828 struct drm_amdgpu_info_hw_ip { 829 /** Version of h/w IP */ 830 __u32 hw_ip_version_major; 831 __u32 hw_ip_version_minor; 832 /** Capabilities */ 833 __u64 capabilities_flags; 834 /** command buffer address start alignment*/ 835 __u32 ib_start_alignment; 836 /** command buffer size alignment*/ 837 __u32 ib_size_alignment; 838 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 839 __u32 available_rings; 840 __u32 _pad; 841 }; 842 843 struct drm_amdgpu_info_num_handles { 844 /** Max handles as supported by firmware for UVD */ 845 __u32 uvd_max_handles; 846 /** Handles currently in use for UVD */ 847 __u32 uvd_used_handles; 848 }; 849 850 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 851 852 struct drm_amdgpu_info_vce_clock_table_entry { 853 /** System clock */ 854 __u32 sclk; 855 /** Memory clock */ 856 __u32 mclk; 857 /** VCE clock */ 858 __u32 eclk; 859 __u32 pad; 860 }; 861 862 struct drm_amdgpu_info_vce_clock_table { 863 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 864 __u32 num_valid_entries; 865 __u32 pad; 866 }; 867 868 /* 869 * Supported GPU families 870 */ 871 #define AMDGPU_FAMILY_UNKNOWN 0 872 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 873 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 874 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 875 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 876 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 877 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 878 #define AMDGPU_FAMILY_RV 142 /* Raven */ 879 880 #if defined(__cplusplus) 881 } 882 #endif 883 884 #endif 885