1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 55 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 56 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 57 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 58 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 59 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 60 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 61 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 62 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 63 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 64 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 65 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 66 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 67 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 68 69 #define AMDGPU_GEM_DOMAIN_CPU 0x1 70 #define AMDGPU_GEM_DOMAIN_GTT 0x2 71 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 72 #define AMDGPU_GEM_DOMAIN_GDS 0x8 73 #define AMDGPU_GEM_DOMAIN_GWS 0x10 74 #define AMDGPU_GEM_DOMAIN_OA 0x20 75 76 /* Flag that CPU access will be required for the case of VRAM domain */ 77 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 78 /* Flag that CPU access will not work, this VRAM domain is invisible */ 79 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 80 /* Flag that USWC attributes should be used for GTT */ 81 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 82 /* Flag that the memory should be in VRAM and cleared */ 83 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 84 /* Flag that create shadow bo(GTT) while allocating vram bo */ 85 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 86 /* Flag that allocating the BO should use linear VRAM */ 87 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 88 89 struct drm_amdgpu_gem_create_in { 90 /** the requested memory size */ 91 __u64 bo_size; 92 /** physical start_addr alignment in bytes for some HW requirements */ 93 __u64 alignment; 94 /** the requested memory domains */ 95 __u64 domains; 96 /** allocation flags */ 97 __u64 domain_flags; 98 }; 99 100 struct drm_amdgpu_gem_create_out { 101 /** returned GEM object handle */ 102 __u32 handle; 103 __u32 _pad; 104 }; 105 106 union drm_amdgpu_gem_create { 107 struct drm_amdgpu_gem_create_in in; 108 struct drm_amdgpu_gem_create_out out; 109 }; 110 111 /** Opcode to create new residency list. */ 112 #define AMDGPU_BO_LIST_OP_CREATE 0 113 /** Opcode to destroy previously created residency list */ 114 #define AMDGPU_BO_LIST_OP_DESTROY 1 115 /** Opcode to update resource information in the list */ 116 #define AMDGPU_BO_LIST_OP_UPDATE 2 117 118 struct drm_amdgpu_bo_list_in { 119 /** Type of operation */ 120 __u32 operation; 121 /** Handle of list or 0 if we want to create one */ 122 __u32 list_handle; 123 /** Number of BOs in list */ 124 __u32 bo_number; 125 /** Size of each element describing BO */ 126 __u32 bo_info_size; 127 /** Pointer to array describing BOs */ 128 __u64 bo_info_ptr; 129 }; 130 131 struct drm_amdgpu_bo_list_entry { 132 /** Handle of BO */ 133 __u32 bo_handle; 134 /** New (if specified) BO priority to be used during migration */ 135 __u32 bo_priority; 136 }; 137 138 struct drm_amdgpu_bo_list_out { 139 /** Handle of resource list */ 140 __u32 list_handle; 141 __u32 _pad; 142 }; 143 144 union drm_amdgpu_bo_list { 145 struct drm_amdgpu_bo_list_in in; 146 struct drm_amdgpu_bo_list_out out; 147 }; 148 149 /* context related */ 150 #define AMDGPU_CTX_OP_ALLOC_CTX 1 151 #define AMDGPU_CTX_OP_FREE_CTX 2 152 #define AMDGPU_CTX_OP_QUERY_STATE 3 153 154 /* GPU reset status */ 155 #define AMDGPU_CTX_NO_RESET 0 156 /* this the context caused it */ 157 #define AMDGPU_CTX_GUILTY_RESET 1 158 /* some other context caused it */ 159 #define AMDGPU_CTX_INNOCENT_RESET 2 160 /* unknown cause */ 161 #define AMDGPU_CTX_UNKNOWN_RESET 3 162 163 struct drm_amdgpu_ctx_in { 164 /** AMDGPU_CTX_OP_* */ 165 __u32 op; 166 /** For future use, no flags defined so far */ 167 __u32 flags; 168 __u32 ctx_id; 169 __u32 _pad; 170 }; 171 172 union drm_amdgpu_ctx_out { 173 struct { 174 __u32 ctx_id; 175 __u32 _pad; 176 } alloc; 177 178 struct { 179 /** For future use, no flags defined so far */ 180 __u64 flags; 181 /** Number of resets caused by this context so far. */ 182 __u32 hangs; 183 /** Reset status since the last call of the ioctl. */ 184 __u32 reset_status; 185 } state; 186 }; 187 188 union drm_amdgpu_ctx { 189 struct drm_amdgpu_ctx_in in; 190 union drm_amdgpu_ctx_out out; 191 }; 192 193 /* 194 * This is not a reliable API and you should expect it to fail for any 195 * number of reasons and have fallback path that do not use userptr to 196 * perform any operation. 197 */ 198 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 199 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 200 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 201 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 202 203 struct drm_amdgpu_gem_userptr { 204 __u64 addr; 205 __u64 size; 206 /* AMDGPU_GEM_USERPTR_* */ 207 __u32 flags; 208 /* Resulting GEM handle */ 209 __u32 handle; 210 }; 211 212 /* SI-CI-VI: */ 213 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 214 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 215 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 216 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 217 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 218 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 219 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 220 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 221 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 222 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 223 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 224 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 225 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 226 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 227 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 228 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 229 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 230 231 /* GFX9 and later: */ 232 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 233 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 234 235 /* Set/Get helpers for tiling flags. */ 236 #define AMDGPU_TILING_SET(field, value) \ 237 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 238 #define AMDGPU_TILING_GET(value, field) \ 239 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 240 241 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 242 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 243 244 /** The same structure is shared for input/output */ 245 struct drm_amdgpu_gem_metadata { 246 /** GEM Object handle */ 247 __u32 handle; 248 /** Do we want get or set metadata */ 249 __u32 op; 250 struct { 251 /** For future use, no flags defined so far */ 252 __u64 flags; 253 /** family specific tiling info */ 254 __u64 tiling_info; 255 __u32 data_size_bytes; 256 __u32 data[64]; 257 } data; 258 }; 259 260 struct drm_amdgpu_gem_mmap_in { 261 /** the GEM object handle */ 262 __u32 handle; 263 __u32 _pad; 264 }; 265 266 struct drm_amdgpu_gem_mmap_out { 267 /** mmap offset from the vma offset manager */ 268 __u64 addr_ptr; 269 }; 270 271 union drm_amdgpu_gem_mmap { 272 struct drm_amdgpu_gem_mmap_in in; 273 struct drm_amdgpu_gem_mmap_out out; 274 }; 275 276 struct drm_amdgpu_gem_wait_idle_in { 277 /** GEM object handle */ 278 __u32 handle; 279 /** For future use, no flags defined so far */ 280 __u32 flags; 281 /** Absolute timeout to wait */ 282 __u64 timeout; 283 }; 284 285 struct drm_amdgpu_gem_wait_idle_out { 286 /** BO status: 0 - BO is idle, 1 - BO is busy */ 287 __u32 status; 288 /** Returned current memory domain */ 289 __u32 domain; 290 }; 291 292 union drm_amdgpu_gem_wait_idle { 293 struct drm_amdgpu_gem_wait_idle_in in; 294 struct drm_amdgpu_gem_wait_idle_out out; 295 }; 296 297 struct drm_amdgpu_wait_cs_in { 298 /* Command submission handle 299 * handle equals 0 means none to wait for 300 * handle equals ~0ull means wait for the latest sequence number 301 */ 302 __u64 handle; 303 /** Absolute timeout to wait */ 304 __u64 timeout; 305 __u32 ip_type; 306 __u32 ip_instance; 307 __u32 ring; 308 __u32 ctx_id; 309 }; 310 311 struct drm_amdgpu_wait_cs_out { 312 /** CS status: 0 - CS completed, 1 - CS still busy */ 313 __u64 status; 314 }; 315 316 union drm_amdgpu_wait_cs { 317 struct drm_amdgpu_wait_cs_in in; 318 struct drm_amdgpu_wait_cs_out out; 319 }; 320 321 struct drm_amdgpu_fence { 322 __u32 ctx_id; 323 __u32 ip_type; 324 __u32 ip_instance; 325 __u32 ring; 326 __u64 seq_no; 327 }; 328 329 struct drm_amdgpu_wait_fences_in { 330 /** This points to uint64_t * which points to fences */ 331 __u64 fences; 332 __u32 fence_count; 333 __u32 wait_all; 334 __u64 timeout_ns; 335 }; 336 337 struct drm_amdgpu_wait_fences_out { 338 __u32 status; 339 __u32 first_signaled; 340 }; 341 342 union drm_amdgpu_wait_fences { 343 struct drm_amdgpu_wait_fences_in in; 344 struct drm_amdgpu_wait_fences_out out; 345 }; 346 347 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 348 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 349 350 /* Sets or returns a value associated with a buffer. */ 351 struct drm_amdgpu_gem_op { 352 /** GEM object handle */ 353 __u32 handle; 354 /** AMDGPU_GEM_OP_* */ 355 __u32 op; 356 /** Input or return value */ 357 __u64 value; 358 }; 359 360 #define AMDGPU_VA_OP_MAP 1 361 #define AMDGPU_VA_OP_UNMAP 2 362 #define AMDGPU_VA_OP_CLEAR 3 363 #define AMDGPU_VA_OP_REPLACE 4 364 365 /* Delay the page table update till the next CS */ 366 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 367 368 /* Mapping flags */ 369 /* readable mapping */ 370 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 371 /* writable mapping */ 372 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 373 /* executable mapping, new for VI */ 374 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 375 /* partially resident texture */ 376 #define AMDGPU_VM_PAGE_PRT (1 << 4) 377 /* MTYPE flags use bit 5 to 8 */ 378 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 379 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 380 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 381 /* Use NC MTYPE instead of default MTYPE */ 382 #define AMDGPU_VM_MTYPE_NC (1 << 5) 383 /* Use WC MTYPE instead of default MTYPE */ 384 #define AMDGPU_VM_MTYPE_WC (2 << 5) 385 /* Use CC MTYPE instead of default MTYPE */ 386 #define AMDGPU_VM_MTYPE_CC (3 << 5) 387 /* Use UC MTYPE instead of default MTYPE */ 388 #define AMDGPU_VM_MTYPE_UC (4 << 5) 389 390 struct drm_amdgpu_gem_va { 391 /** GEM object handle */ 392 __u32 handle; 393 __u32 _pad; 394 /** AMDGPU_VA_OP_* */ 395 __u32 operation; 396 /** AMDGPU_VM_PAGE_* */ 397 __u32 flags; 398 /** va address to assign . Must be correctly aligned.*/ 399 __u64 va_address; 400 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 401 __u64 offset_in_bo; 402 /** Specify mapping size. Must be correctly aligned. */ 403 __u64 map_size; 404 }; 405 406 #define AMDGPU_HW_IP_GFX 0 407 #define AMDGPU_HW_IP_COMPUTE 1 408 #define AMDGPU_HW_IP_DMA 2 409 #define AMDGPU_HW_IP_UVD 3 410 #define AMDGPU_HW_IP_VCE 4 411 #define AMDGPU_HW_IP_UVD_ENC 5 412 #define AMDGPU_HW_IP_NUM 6 413 414 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 415 416 #define AMDGPU_CHUNK_ID_IB 0x01 417 #define AMDGPU_CHUNK_ID_FENCE 0x02 418 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 419 420 struct drm_amdgpu_cs_chunk { 421 __u32 chunk_id; 422 __u32 length_dw; 423 __u64 chunk_data; 424 }; 425 426 struct drm_amdgpu_cs_in { 427 /** Rendering context id */ 428 __u32 ctx_id; 429 /** Handle of resource list associated with CS */ 430 __u32 bo_list_handle; 431 __u32 num_chunks; 432 __u32 _pad; 433 /** this points to __u64 * which point to cs chunks */ 434 __u64 chunks; 435 }; 436 437 struct drm_amdgpu_cs_out { 438 __u64 handle; 439 }; 440 441 union drm_amdgpu_cs { 442 struct drm_amdgpu_cs_in in; 443 struct drm_amdgpu_cs_out out; 444 }; 445 446 /* Specify flags to be used for IB */ 447 448 /* This IB should be submitted to CE */ 449 #define AMDGPU_IB_FLAG_CE (1<<0) 450 451 /* Preamble flag, which means the IB could be dropped if no context switch */ 452 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 453 454 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 455 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 456 457 struct drm_amdgpu_cs_chunk_ib { 458 __u32 _pad; 459 /** AMDGPU_IB_FLAG_* */ 460 __u32 flags; 461 /** Virtual address to begin IB execution */ 462 __u64 va_start; 463 /** Size of submission */ 464 __u32 ib_bytes; 465 /** HW IP to submit to */ 466 __u32 ip_type; 467 /** HW IP index of the same type to submit to */ 468 __u32 ip_instance; 469 /** Ring index to submit to */ 470 __u32 ring; 471 }; 472 473 struct drm_amdgpu_cs_chunk_dep { 474 __u32 ip_type; 475 __u32 ip_instance; 476 __u32 ring; 477 __u32 ctx_id; 478 __u64 handle; 479 }; 480 481 struct drm_amdgpu_cs_chunk_fence { 482 __u32 handle; 483 __u32 offset; 484 }; 485 486 struct drm_amdgpu_cs_chunk_data { 487 union { 488 struct drm_amdgpu_cs_chunk_ib ib_data; 489 struct drm_amdgpu_cs_chunk_fence fence_data; 490 }; 491 }; 492 493 /** 494 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 495 * 496 */ 497 #define AMDGPU_IDS_FLAGS_FUSION 0x1 498 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 499 500 /* indicate if acceleration can be working */ 501 #define AMDGPU_INFO_ACCEL_WORKING 0x00 502 /* get the crtc_id from the mode object id? */ 503 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 504 /* query hw IP info */ 505 #define AMDGPU_INFO_HW_IP_INFO 0x02 506 /* query hw IP instance count for the specified type */ 507 #define AMDGPU_INFO_HW_IP_COUNT 0x03 508 /* timestamp for GL_ARB_timer_query */ 509 #define AMDGPU_INFO_TIMESTAMP 0x05 510 /* Query the firmware version */ 511 #define AMDGPU_INFO_FW_VERSION 0x0e 512 /* Subquery id: Query VCE firmware version */ 513 #define AMDGPU_INFO_FW_VCE 0x1 514 /* Subquery id: Query UVD firmware version */ 515 #define AMDGPU_INFO_FW_UVD 0x2 516 /* Subquery id: Query GMC firmware version */ 517 #define AMDGPU_INFO_FW_GMC 0x03 518 /* Subquery id: Query GFX ME firmware version */ 519 #define AMDGPU_INFO_FW_GFX_ME 0x04 520 /* Subquery id: Query GFX PFP firmware version */ 521 #define AMDGPU_INFO_FW_GFX_PFP 0x05 522 /* Subquery id: Query GFX CE firmware version */ 523 #define AMDGPU_INFO_FW_GFX_CE 0x06 524 /* Subquery id: Query GFX RLC firmware version */ 525 #define AMDGPU_INFO_FW_GFX_RLC 0x07 526 /* Subquery id: Query GFX MEC firmware version */ 527 #define AMDGPU_INFO_FW_GFX_MEC 0x08 528 /* Subquery id: Query SMC firmware version */ 529 #define AMDGPU_INFO_FW_SMC 0x0a 530 /* Subquery id: Query SDMA firmware version */ 531 #define AMDGPU_INFO_FW_SDMA 0x0b 532 /* Subquery id: Query PSP SOS firmware version */ 533 #define AMDGPU_INFO_FW_SOS 0x0c 534 /* Subquery id: Query PSP ASD firmware version */ 535 #define AMDGPU_INFO_FW_ASD 0x0d 536 /* number of bytes moved for TTM migration */ 537 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 538 /* the used VRAM size */ 539 #define AMDGPU_INFO_VRAM_USAGE 0x10 540 /* the used GTT size */ 541 #define AMDGPU_INFO_GTT_USAGE 0x11 542 /* Information about GDS, etc. resource configuration */ 543 #define AMDGPU_INFO_GDS_CONFIG 0x13 544 /* Query information about VRAM and GTT domains */ 545 #define AMDGPU_INFO_VRAM_GTT 0x14 546 /* Query information about register in MMR address space*/ 547 #define AMDGPU_INFO_READ_MMR_REG 0x15 548 /* Query information about device: rev id, family, etc. */ 549 #define AMDGPU_INFO_DEV_INFO 0x16 550 /* visible vram usage */ 551 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 552 /* number of TTM buffer evictions */ 553 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 554 /* Query memory about VRAM and GTT domains */ 555 #define AMDGPU_INFO_MEMORY 0x19 556 /* Query vce clock table */ 557 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 558 /* Query vbios related information */ 559 #define AMDGPU_INFO_VBIOS 0x1B 560 /* Subquery id: Query vbios size */ 561 #define AMDGPU_INFO_VBIOS_SIZE 0x1 562 /* Subquery id: Query vbios image */ 563 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 564 /* Query UVD handles */ 565 #define AMDGPU_INFO_NUM_HANDLES 0x1C 566 /* Query sensor related information */ 567 #define AMDGPU_INFO_SENSOR 0x1D 568 /* Subquery id: Query GPU shader clock */ 569 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 570 /* Subquery id: Query GPU memory clock */ 571 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 572 /* Subquery id: Query GPU temperature */ 573 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 574 /* Subquery id: Query GPU load */ 575 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 576 /* Subquery id: Query average GPU power */ 577 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 578 /* Subquery id: Query northbridge voltage */ 579 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 580 /* Subquery id: Query graphics voltage */ 581 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 582 583 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 584 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 585 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 586 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 587 588 struct drm_amdgpu_query_fw { 589 /** AMDGPU_INFO_FW_* */ 590 __u32 fw_type; 591 /** 592 * Index of the IP if there are more IPs of 593 * the same type. 594 */ 595 __u32 ip_instance; 596 /** 597 * Index of the engine. Whether this is used depends 598 * on the firmware type. (e.g. MEC, SDMA) 599 */ 600 __u32 index; 601 __u32 _pad; 602 }; 603 604 /* Input structure for the INFO ioctl */ 605 struct drm_amdgpu_info { 606 /* Where the return value will be stored */ 607 __u64 return_pointer; 608 /* The size of the return value. Just like "size" in "snprintf", 609 * it limits how many bytes the kernel can write. */ 610 __u32 return_size; 611 /* The query request id. */ 612 __u32 query; 613 614 union { 615 struct { 616 __u32 id; 617 __u32 _pad; 618 } mode_crtc; 619 620 struct { 621 /** AMDGPU_HW_IP_* */ 622 __u32 type; 623 /** 624 * Index of the IP if there are more IPs of the same 625 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 626 */ 627 __u32 ip_instance; 628 } query_hw_ip; 629 630 struct { 631 __u32 dword_offset; 632 /** number of registers to read */ 633 __u32 count; 634 __u32 instance; 635 /** For future use, no flags defined so far */ 636 __u32 flags; 637 } read_mmr_reg; 638 639 struct drm_amdgpu_query_fw query_fw; 640 641 struct { 642 __u32 type; 643 __u32 offset; 644 } vbios_info; 645 646 struct { 647 __u32 type; 648 } sensor_info; 649 }; 650 }; 651 652 struct drm_amdgpu_info_gds { 653 /** GDS GFX partition size */ 654 __u32 gds_gfx_partition_size; 655 /** GDS compute partition size */ 656 __u32 compute_partition_size; 657 /** total GDS memory size */ 658 __u32 gds_total_size; 659 /** GWS size per GFX partition */ 660 __u32 gws_per_gfx_partition; 661 /** GSW size per compute partition */ 662 __u32 gws_per_compute_partition; 663 /** OA size per GFX partition */ 664 __u32 oa_per_gfx_partition; 665 /** OA size per compute partition */ 666 __u32 oa_per_compute_partition; 667 __u32 _pad; 668 }; 669 670 struct drm_amdgpu_info_vram_gtt { 671 __u64 vram_size; 672 __u64 vram_cpu_accessible_size; 673 __u64 gtt_size; 674 }; 675 676 struct drm_amdgpu_heap_info { 677 /** max. physical memory */ 678 __u64 total_heap_size; 679 680 /** Theoretical max. available memory in the given heap */ 681 __u64 usable_heap_size; 682 683 /** 684 * Number of bytes allocated in the heap. This includes all processes 685 * and private allocations in the kernel. It changes when new buffers 686 * are allocated, freed, and moved. It cannot be larger than 687 * heap_size. 688 */ 689 __u64 heap_usage; 690 691 /** 692 * Theoretical possible max. size of buffer which 693 * could be allocated in the given heap 694 */ 695 __u64 max_allocation; 696 }; 697 698 struct drm_amdgpu_memory_info { 699 struct drm_amdgpu_heap_info vram; 700 struct drm_amdgpu_heap_info cpu_accessible_vram; 701 struct drm_amdgpu_heap_info gtt; 702 }; 703 704 struct drm_amdgpu_info_firmware { 705 __u32 ver; 706 __u32 feature; 707 }; 708 709 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 710 #define AMDGPU_VRAM_TYPE_GDDR1 1 711 #define AMDGPU_VRAM_TYPE_DDR2 2 712 #define AMDGPU_VRAM_TYPE_GDDR3 3 713 #define AMDGPU_VRAM_TYPE_GDDR4 4 714 #define AMDGPU_VRAM_TYPE_GDDR5 5 715 #define AMDGPU_VRAM_TYPE_HBM 6 716 #define AMDGPU_VRAM_TYPE_DDR3 7 717 718 struct drm_amdgpu_info_device { 719 /** PCI Device ID */ 720 __u32 device_id; 721 /** Internal chip revision: A0, A1, etc.) */ 722 __u32 chip_rev; 723 __u32 external_rev; 724 /** Revision id in PCI Config space */ 725 __u32 pci_rev; 726 __u32 family; 727 __u32 num_shader_engines; 728 __u32 num_shader_arrays_per_engine; 729 /* in KHz */ 730 __u32 gpu_counter_freq; 731 __u64 max_engine_clock; 732 __u64 max_memory_clock; 733 /* cu information */ 734 __u32 cu_active_number; 735 __u32 cu_ao_mask; 736 __u32 cu_bitmap[4][4]; 737 /** Render backend pipe mask. One render backend is CB+DB. */ 738 __u32 enabled_rb_pipes_mask; 739 __u32 num_rb_pipes; 740 __u32 num_hw_gfx_contexts; 741 __u32 _pad; 742 __u64 ids_flags; 743 /** Starting virtual address for UMDs. */ 744 __u64 virtual_address_offset; 745 /** The maximum virtual address */ 746 __u64 virtual_address_max; 747 /** Required alignment of virtual addresses. */ 748 __u32 virtual_address_alignment; 749 /** Page table entry - fragment size */ 750 __u32 pte_fragment_size; 751 __u32 gart_page_size; 752 /** constant engine ram size*/ 753 __u32 ce_ram_size; 754 /** video memory type info*/ 755 __u32 vram_type; 756 /** video memory bit width*/ 757 __u32 vram_bit_width; 758 /* vce harvesting instance */ 759 __u32 vce_harvest_config; 760 /* gfx double offchip LDS buffers */ 761 __u32 gc_double_offchip_lds_buf; 762 /* NGG Primitive Buffer */ 763 __u64 prim_buf_gpu_addr; 764 /* NGG Position Buffer */ 765 __u64 pos_buf_gpu_addr; 766 /* NGG Control Sideband */ 767 __u64 cntl_sb_buf_gpu_addr; 768 /* NGG Parameter Cache */ 769 __u64 param_buf_gpu_addr; 770 __u32 prim_buf_size; 771 __u32 pos_buf_size; 772 __u32 cntl_sb_buf_size; 773 __u32 param_buf_size; 774 /* wavefront size*/ 775 __u32 wave_front_size; 776 /* shader visible vgprs*/ 777 __u32 num_shader_visible_vgprs; 778 /* CU per shader array*/ 779 __u32 num_cu_per_sh; 780 /* number of tcc blocks*/ 781 __u32 num_tcc_blocks; 782 /* gs vgt table depth*/ 783 __u32 gs_vgt_table_depth; 784 /* gs primitive buffer depth*/ 785 __u32 gs_prim_buffer_depth; 786 /* max gs wavefront per vgt*/ 787 __u32 max_gs_waves_per_vgt; 788 __u32 _pad1; 789 }; 790 791 struct drm_amdgpu_info_hw_ip { 792 /** Version of h/w IP */ 793 __u32 hw_ip_version_major; 794 __u32 hw_ip_version_minor; 795 /** Capabilities */ 796 __u64 capabilities_flags; 797 /** command buffer address start alignment*/ 798 __u32 ib_start_alignment; 799 /** command buffer size alignment*/ 800 __u32 ib_size_alignment; 801 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 802 __u32 available_rings; 803 __u32 _pad; 804 }; 805 806 struct drm_amdgpu_info_num_handles { 807 /** Max handles as supported by firmware for UVD */ 808 __u32 uvd_max_handles; 809 /** Handles currently in use for UVD */ 810 __u32 uvd_used_handles; 811 }; 812 813 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 814 815 struct drm_amdgpu_info_vce_clock_table_entry { 816 /** System clock */ 817 __u32 sclk; 818 /** Memory clock */ 819 __u32 mclk; 820 /** VCE clock */ 821 __u32 eclk; 822 __u32 pad; 823 }; 824 825 struct drm_amdgpu_info_vce_clock_table { 826 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 827 __u32 num_valid_entries; 828 __u32 pad; 829 }; 830 831 /* 832 * Supported GPU families 833 */ 834 #define AMDGPU_FAMILY_UNKNOWN 0 835 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 836 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 837 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 838 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 839 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 840 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 841 842 #if defined(__cplusplus) 843 } 844 #endif 845 846 #endif 847