1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 #define DRM_AMDGPU_USERQ 0x16 58 #define DRM_AMDGPU_USERQ_SIGNAL 0x17 59 #define DRM_AMDGPU_USERQ_WAIT 0x18 60 61 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 62 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 63 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 64 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 65 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 66 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 67 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 68 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 69 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 70 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 71 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 72 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 73 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 74 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 75 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 76 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 77 #define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) 78 #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) 79 #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) 80 81 /** 82 * DOC: memory domains 83 * 84 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 85 * Memory in this pool could be swapped out to disk if there is pressure. 86 * 87 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 88 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 89 * pages of system memory, allows GPU access system memory in a linearized 90 * fashion. 91 * 92 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 93 * carved out by the BIOS. 94 * 95 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 96 * across shader threads. 97 * 98 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 99 * execution of all the waves on a device. 100 * 101 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 102 * for appending data. 103 * 104 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 105 * signalling user mode queues. 106 */ 107 #define AMDGPU_GEM_DOMAIN_CPU 0x1 108 #define AMDGPU_GEM_DOMAIN_GTT 0x2 109 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 110 #define AMDGPU_GEM_DOMAIN_GDS 0x8 111 #define AMDGPU_GEM_DOMAIN_GWS 0x10 112 #define AMDGPU_GEM_DOMAIN_OA 0x20 113 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 114 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 115 AMDGPU_GEM_DOMAIN_GTT | \ 116 AMDGPU_GEM_DOMAIN_VRAM | \ 117 AMDGPU_GEM_DOMAIN_GDS | \ 118 AMDGPU_GEM_DOMAIN_GWS | \ 119 AMDGPU_GEM_DOMAIN_OA | \ 120 AMDGPU_GEM_DOMAIN_DOORBELL) 121 122 /* Flag that CPU access will be required for the case of VRAM domain */ 123 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 124 /* Flag that CPU access will not work, this VRAM domain is invisible */ 125 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 126 /* Flag that USWC attributes should be used for GTT */ 127 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 128 /* Flag that the memory should be in VRAM and cleared */ 129 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 130 /* Flag that allocating the BO should use linear VRAM */ 131 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 132 /* Flag that BO is always valid in this VM */ 133 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 134 /* Flag that BO sharing will be explicitly synchronized */ 135 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 136 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 137 * for the second page onward should be set to NC. It should never 138 * be used by user space applications. 139 */ 140 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 141 /* Flag that BO may contain sensitive data that must be wiped before 142 * releasing the memory 143 */ 144 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 145 /* Flag that BO will be encrypted and that the TMZ bit should be 146 * set in the PTEs when mapping this buffer via GPUVM or 147 * accessing it with various hw blocks 148 */ 149 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 150 /* Flag that BO will be used only in preemptible context, which does 151 * not require GTT memory accounting 152 */ 153 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 154 /* Flag that BO can be discarded under memory pressure without keeping the 155 * content. 156 */ 157 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 158 /* Flag that BO is shared coherently between multiple devices or CPU threads. 159 * May depend on GPU instructions to flush caches to system scope explicitly. 160 * 161 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 162 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 163 */ 164 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 165 /* Flag that BO should not be cached by GPU. Coherent without having to flush 166 * GPU caches explicitly 167 * 168 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 169 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 170 */ 171 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 172 /* Flag that BO should be coherent across devices when using device-level 173 * atomics. May depend on GPU instructions to flush caches to device scope 174 * explicitly, promoting them to system scope automatically. 175 * 176 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 177 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 178 */ 179 #define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 180 /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */ 181 #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) 182 183 struct drm_amdgpu_gem_create_in { 184 /** the requested memory size */ 185 __u64 bo_size; 186 /** physical start_addr alignment in bytes for some HW requirements */ 187 __u64 alignment; 188 /** the requested memory domains */ 189 __u64 domains; 190 /** allocation flags */ 191 __u64 domain_flags; 192 }; 193 194 struct drm_amdgpu_gem_create_out { 195 /** returned GEM object handle */ 196 __u32 handle; 197 __u32 _pad; 198 }; 199 200 union drm_amdgpu_gem_create { 201 struct drm_amdgpu_gem_create_in in; 202 struct drm_amdgpu_gem_create_out out; 203 }; 204 205 /** Opcode to create new residency list. */ 206 #define AMDGPU_BO_LIST_OP_CREATE 0 207 /** Opcode to destroy previously created residency list */ 208 #define AMDGPU_BO_LIST_OP_DESTROY 1 209 /** Opcode to update resource information in the list */ 210 #define AMDGPU_BO_LIST_OP_UPDATE 2 211 212 struct drm_amdgpu_bo_list_in { 213 /** Type of operation */ 214 __u32 operation; 215 /** Handle of list or 0 if we want to create one */ 216 __u32 list_handle; 217 /** Number of BOs in list */ 218 __u32 bo_number; 219 /** Size of each element describing BO */ 220 __u32 bo_info_size; 221 /** Pointer to array describing BOs */ 222 __u64 bo_info_ptr; 223 }; 224 225 struct drm_amdgpu_bo_list_entry { 226 /** Handle of BO */ 227 __u32 bo_handle; 228 /** New (if specified) BO priority to be used during migration */ 229 __u32 bo_priority; 230 }; 231 232 struct drm_amdgpu_bo_list_out { 233 /** Handle of resource list */ 234 __u32 list_handle; 235 __u32 _pad; 236 }; 237 238 union drm_amdgpu_bo_list { 239 struct drm_amdgpu_bo_list_in in; 240 struct drm_amdgpu_bo_list_out out; 241 }; 242 243 /* context related */ 244 #define AMDGPU_CTX_OP_ALLOC_CTX 1 245 #define AMDGPU_CTX_OP_FREE_CTX 2 246 #define AMDGPU_CTX_OP_QUERY_STATE 3 247 #define AMDGPU_CTX_OP_QUERY_STATE2 4 248 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 249 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 250 251 /* GPU reset status */ 252 #define AMDGPU_CTX_NO_RESET 0 253 /* this the context caused it */ 254 #define AMDGPU_CTX_GUILTY_RESET 1 255 /* some other context caused it */ 256 #define AMDGPU_CTX_INNOCENT_RESET 2 257 /* unknown cause */ 258 #define AMDGPU_CTX_UNKNOWN_RESET 3 259 260 /* indicate gpu reset occurred after ctx created */ 261 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 262 /* indicate vram lost occurred after ctx created */ 263 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 264 /* indicate some job from this context once cause gpu hang */ 265 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 266 /* indicate some errors are detected by RAS */ 267 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 268 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 269 /* indicate that the reset hasn't completed yet */ 270 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 271 272 /* Context priority level */ 273 #define AMDGPU_CTX_PRIORITY_UNSET -2048 274 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 275 #define AMDGPU_CTX_PRIORITY_LOW -512 276 #define AMDGPU_CTX_PRIORITY_NORMAL 0 277 /* 278 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 279 * CAP_SYS_NICE or DRM_MASTER 280 */ 281 #define AMDGPU_CTX_PRIORITY_HIGH 512 282 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 283 284 /* select a stable profiling pstate for perfmon tools */ 285 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 286 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 287 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 288 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 289 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 290 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 291 292 struct drm_amdgpu_ctx_in { 293 /** AMDGPU_CTX_OP_* */ 294 __u32 op; 295 /** Flags */ 296 __u32 flags; 297 __u32 ctx_id; 298 /** AMDGPU_CTX_PRIORITY_* */ 299 __s32 priority; 300 }; 301 302 union drm_amdgpu_ctx_out { 303 struct { 304 __u32 ctx_id; 305 __u32 _pad; 306 } alloc; 307 308 struct { 309 /** For future use, no flags defined so far */ 310 __u64 flags; 311 /** Number of resets caused by this context so far. */ 312 __u32 hangs; 313 /** Reset status since the last call of the ioctl. */ 314 __u32 reset_status; 315 } state; 316 317 struct { 318 __u32 flags; 319 __u32 _pad; 320 } pstate; 321 }; 322 323 union drm_amdgpu_ctx { 324 struct drm_amdgpu_ctx_in in; 325 union drm_amdgpu_ctx_out out; 326 }; 327 328 /* user queue IOCTL operations */ 329 #define AMDGPU_USERQ_OP_CREATE 1 330 #define AMDGPU_USERQ_OP_FREE 2 331 332 /* 333 * This structure is a container to pass input configuration 334 * info for all supported userqueue related operations. 335 * For operation AMDGPU_USERQ_OP_CREATE: user is expected 336 * to set all fields, excep the parameter 'queue_id'. 337 * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected 338 * to be set is 'queue_id', eveything else is ignored. 339 */ 340 struct drm_amdgpu_userq_in { 341 /** AMDGPU_USERQ_OP_* */ 342 __u32 op; 343 /** Queue id passed for operation USERQ_OP_FREE */ 344 __u32 queue_id; 345 /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */ 346 __u32 ip_type; 347 /** 348 * @doorbell_handle: the handle of doorbell GEM object 349 * associated with this userqueue client. 350 */ 351 __u32 doorbell_handle; 352 /** 353 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo. 354 * Kernel will generate absolute doorbell offset using doorbell_handle 355 * and doorbell_offset in the doorbell bo. 356 */ 357 __u32 doorbell_offset; 358 __u32 _pad; 359 /** 360 * @queue_va: Virtual address of the GPU memory which holds the queue 361 * object. The queue holds the workload packets. 362 */ 363 __u64 queue_va; 364 /** 365 * @queue_size: Size of the queue in bytes, this needs to be 256-byte 366 * aligned. 367 */ 368 __u64 queue_size; 369 /** 370 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR. 371 * This object must be at least 8 byte in size and aligned to 8-byte offset. 372 */ 373 __u64 rptr_va; 374 /** 375 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR. 376 * This object must be at least 8 byte in size and aligned to 8-byte offset. 377 * 378 * Queue, RPTR and WPTR can come from the same object, as long as the size 379 * and alignment related requirements are met. 380 */ 381 __u64 wptr_va; 382 /** 383 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow 384 * the GPU to uniquely define and identify a usermode queue. 385 * 386 * MQD data can be of different size for different GPU IP/engine and 387 * their respective versions/revisions, so this points to a __u64 * 388 * which holds IP specific MQD of this usermode queue. 389 */ 390 __u64 mqd; 391 /** 392 * @size: size of MQD data in bytes, it must match the MQD structure 393 * size of the respective engine/revision defined in UAPI for ex, for 394 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11). 395 */ 396 __u64 mqd_size; 397 }; 398 399 /* The structure to carry output of userqueue ops */ 400 struct drm_amdgpu_userq_out { 401 /** 402 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique 403 * queue ID to represent the newly created userqueue in the system, otherwise 404 * it should be ignored. 405 */ 406 __u32 queue_id; 407 __u32 _pad; 408 }; 409 410 union drm_amdgpu_userq { 411 struct drm_amdgpu_userq_in in; 412 struct drm_amdgpu_userq_out out; 413 }; 414 415 /* GFX V11 IP specific MQD parameters */ 416 struct drm_amdgpu_userq_mqd_gfx11 { 417 /** 418 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer. 419 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 420 */ 421 __u64 shadow_va; 422 /** 423 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 424 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 425 */ 426 __u64 csa_va; 427 }; 428 429 /* GFX V11 SDMA IP specific MQD parameters */ 430 struct drm_amdgpu_userq_mqd_sdma_gfx11 { 431 /** 432 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 433 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 434 * to get the size. 435 */ 436 __u64 csa_va; 437 }; 438 439 /* GFX V11 Compute IP specific MQD parameters */ 440 struct drm_amdgpu_userq_mqd_compute_gfx11 { 441 /** 442 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer. 443 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 444 * to get the size. 445 */ 446 __u64 eop_va; 447 }; 448 449 /* userq signal/wait ioctl */ 450 struct drm_amdgpu_userq_signal { 451 /** 452 * @queue_id: Queue handle used by the userq fence creation function 453 * to retrieve the WPTR. 454 */ 455 __u32 queue_id; 456 __u32 pad; 457 /** 458 * @syncobj_handles: The list of syncobj handles submitted by the user queue 459 * job to be signaled. 460 */ 461 __u64 syncobj_handles; 462 /** 463 * @num_syncobj_handles: A count that represents the number of syncobj handles in 464 * @syncobj_handles. 465 */ 466 __u64 num_syncobj_handles; 467 /** 468 * @bo_read_handles: The list of BO handles that the submitted user queue job 469 * is using for read only. This will update BO fences in the kernel. 470 */ 471 __u64 bo_read_handles; 472 /** 473 * @bo_write_handles: The list of BO handles that the submitted user queue job 474 * is using for write only. This will update BO fences in the kernel. 475 */ 476 __u64 bo_write_handles; 477 /** 478 * @num_bo_read_handles: A count that represents the number of read BO handles in 479 * @bo_read_handles. 480 */ 481 __u32 num_bo_read_handles; 482 /** 483 * @num_bo_write_handles: A count that represents the number of write BO handles in 484 * @bo_write_handles. 485 */ 486 __u32 num_bo_write_handles; 487 }; 488 489 struct drm_amdgpu_userq_fence_info { 490 /** 491 * @va: A gpu address allocated for each queue which stores the 492 * read pointer (RPTR) value. 493 */ 494 __u64 va; 495 /** 496 * @value: A 64 bit value represents the write pointer (WPTR) of the 497 * queue commands which compared with the RPTR value to signal the 498 * fences. 499 */ 500 __u64 value; 501 }; 502 503 struct drm_amdgpu_userq_wait { 504 /** 505 * @syncobj_handles: The list of syncobj handles submitted by the user queue 506 * job to get the va/value pairs. 507 */ 508 __u64 syncobj_handles; 509 /** 510 * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by 511 * the user queue job to get the va/value pairs at given @syncobj_timeline_points. 512 */ 513 __u64 syncobj_timeline_handles; 514 /** 515 * @syncobj_timeline_points: The list of timeline syncobj points submitted by the 516 * user queue job for the corresponding @syncobj_timeline_handles. 517 */ 518 __u64 syncobj_timeline_points; 519 /** 520 * @bo_read_handles: The list of read BO handles submitted by the user queue 521 * job to get the va/value pairs. 522 */ 523 __u64 bo_read_handles; 524 /** 525 * @bo_write_handles: The list of write BO handles submitted by the user queue 526 * job to get the va/value pairs. 527 */ 528 __u64 bo_write_handles; 529 /** 530 * @num_syncobj_timeline_handles: A count that represents the number of timeline 531 * syncobj handles in @syncobj_timeline_handles. 532 */ 533 __u16 num_syncobj_timeline_handles; 534 /** 535 * @num_fences: This field can be used both as input and output. As input it defines 536 * the maximum number of fences that can be returned and as output it will specify 537 * how many fences were actually returned from the ioctl. 538 */ 539 __u16 num_fences; 540 /** 541 * @num_syncobj_handles: A count that represents the number of syncobj handles in 542 * @syncobj_handles. 543 */ 544 __u32 num_syncobj_handles; 545 /** 546 * @num_bo_read_handles: A count that represents the number of read BO handles in 547 * @bo_read_handles. 548 */ 549 __u32 num_bo_read_handles; 550 /** 551 * @num_bo_write_handles: A count that represents the number of write BO handles in 552 * @bo_write_handles. 553 */ 554 __u32 num_bo_write_handles; 555 /** 556 * @out_fences: The field is a return value from the ioctl containing the list of 557 * address/value pairs to wait for. 558 */ 559 __u64 out_fences; 560 }; 561 562 /* vm ioctl */ 563 #define AMDGPU_VM_OP_RESERVE_VMID 1 564 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 565 566 struct drm_amdgpu_vm_in { 567 /** AMDGPU_VM_OP_* */ 568 __u32 op; 569 __u32 flags; 570 }; 571 572 struct drm_amdgpu_vm_out { 573 /** For future use, no flags defined so far */ 574 __u64 flags; 575 }; 576 577 union drm_amdgpu_vm { 578 struct drm_amdgpu_vm_in in; 579 struct drm_amdgpu_vm_out out; 580 }; 581 582 /* sched ioctl */ 583 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 584 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 585 586 struct drm_amdgpu_sched_in { 587 /* AMDGPU_SCHED_OP_* */ 588 __u32 op; 589 __u32 fd; 590 /** AMDGPU_CTX_PRIORITY_* */ 591 __s32 priority; 592 __u32 ctx_id; 593 }; 594 595 union drm_amdgpu_sched { 596 struct drm_amdgpu_sched_in in; 597 }; 598 599 /* 600 * This is not a reliable API and you should expect it to fail for any 601 * number of reasons and have fallback path that do not use userptr to 602 * perform any operation. 603 */ 604 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 605 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 606 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 607 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 608 609 struct drm_amdgpu_gem_userptr { 610 __u64 addr; 611 __u64 size; 612 /* AMDGPU_GEM_USERPTR_* */ 613 __u32 flags; 614 /* Resulting GEM handle */ 615 __u32 handle; 616 }; 617 618 /* SI-CI-VI: */ 619 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 620 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 621 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 622 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 623 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 624 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 625 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 626 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 627 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 628 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 629 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 630 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 631 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 632 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 633 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 634 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 635 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 636 637 /* GFX9 - GFX11: */ 638 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 639 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 640 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 641 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 642 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 643 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 644 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 645 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 646 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 647 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 648 #define AMDGPU_TILING_SCANOUT_SHIFT 63 649 #define AMDGPU_TILING_SCANOUT_MASK 0x1 650 651 /* GFX12 and later: */ 652 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 653 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 654 /* These are DCC recompression settings for memory management: */ 655 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 656 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ 657 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 658 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ 659 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 660 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 661 /* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata 662 * to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */ 663 #define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14 664 #define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1 665 /* bit gap */ 666 #define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63 667 #define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1 668 669 /* Set/Get helpers for tiling flags. */ 670 #define AMDGPU_TILING_SET(field, value) \ 671 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 672 #define AMDGPU_TILING_GET(value, field) \ 673 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 674 675 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 676 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 677 678 /** The same structure is shared for input/output */ 679 struct drm_amdgpu_gem_metadata { 680 /** GEM Object handle */ 681 __u32 handle; 682 /** Do we want get or set metadata */ 683 __u32 op; 684 struct { 685 /** For future use, no flags defined so far */ 686 __u64 flags; 687 /** family specific tiling info */ 688 __u64 tiling_info; 689 __u32 data_size_bytes; 690 __u32 data[64]; 691 } data; 692 }; 693 694 struct drm_amdgpu_gem_mmap_in { 695 /** the GEM object handle */ 696 __u32 handle; 697 __u32 _pad; 698 }; 699 700 struct drm_amdgpu_gem_mmap_out { 701 /** mmap offset from the vma offset manager */ 702 __u64 addr_ptr; 703 }; 704 705 union drm_amdgpu_gem_mmap { 706 struct drm_amdgpu_gem_mmap_in in; 707 struct drm_amdgpu_gem_mmap_out out; 708 }; 709 710 struct drm_amdgpu_gem_wait_idle_in { 711 /** GEM object handle */ 712 __u32 handle; 713 /** For future use, no flags defined so far */ 714 __u32 flags; 715 /** Absolute timeout to wait */ 716 __u64 timeout; 717 }; 718 719 struct drm_amdgpu_gem_wait_idle_out { 720 /** BO status: 0 - BO is idle, 1 - BO is busy */ 721 __u32 status; 722 /** Returned current memory domain */ 723 __u32 domain; 724 }; 725 726 union drm_amdgpu_gem_wait_idle { 727 struct drm_amdgpu_gem_wait_idle_in in; 728 struct drm_amdgpu_gem_wait_idle_out out; 729 }; 730 731 struct drm_amdgpu_wait_cs_in { 732 /* Command submission handle 733 * handle equals 0 means none to wait for 734 * handle equals ~0ull means wait for the latest sequence number 735 */ 736 __u64 handle; 737 /** Absolute timeout to wait */ 738 __u64 timeout; 739 __u32 ip_type; 740 __u32 ip_instance; 741 __u32 ring; 742 __u32 ctx_id; 743 }; 744 745 struct drm_amdgpu_wait_cs_out { 746 /** CS status: 0 - CS completed, 1 - CS still busy */ 747 __u64 status; 748 }; 749 750 union drm_amdgpu_wait_cs { 751 struct drm_amdgpu_wait_cs_in in; 752 struct drm_amdgpu_wait_cs_out out; 753 }; 754 755 struct drm_amdgpu_fence { 756 __u32 ctx_id; 757 __u32 ip_type; 758 __u32 ip_instance; 759 __u32 ring; 760 __u64 seq_no; 761 }; 762 763 struct drm_amdgpu_wait_fences_in { 764 /** This points to uint64_t * which points to fences */ 765 __u64 fences; 766 __u32 fence_count; 767 __u32 wait_all; 768 __u64 timeout_ns; 769 }; 770 771 struct drm_amdgpu_wait_fences_out { 772 __u32 status; 773 __u32 first_signaled; 774 }; 775 776 union drm_amdgpu_wait_fences { 777 struct drm_amdgpu_wait_fences_in in; 778 struct drm_amdgpu_wait_fences_out out; 779 }; 780 781 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 782 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 783 784 /* Sets or returns a value associated with a buffer. */ 785 struct drm_amdgpu_gem_op { 786 /** GEM object handle */ 787 __u32 handle; 788 /** AMDGPU_GEM_OP_* */ 789 __u32 op; 790 /** Input or return value */ 791 __u64 value; 792 }; 793 794 #define AMDGPU_VA_OP_MAP 1 795 #define AMDGPU_VA_OP_UNMAP 2 796 #define AMDGPU_VA_OP_CLEAR 3 797 #define AMDGPU_VA_OP_REPLACE 4 798 799 /* Delay the page table update till the next CS */ 800 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 801 802 /* Mapping flags */ 803 /* readable mapping */ 804 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 805 /* writable mapping */ 806 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 807 /* executable mapping, new for VI */ 808 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 809 /* partially resident texture */ 810 #define AMDGPU_VM_PAGE_PRT (1 << 4) 811 /* MTYPE flags use bit 5 to 8 */ 812 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 813 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 814 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 815 /* Use Non Coherent MTYPE instead of default MTYPE */ 816 #define AMDGPU_VM_MTYPE_NC (1 << 5) 817 /* Use Write Combine MTYPE instead of default MTYPE */ 818 #define AMDGPU_VM_MTYPE_WC (2 << 5) 819 /* Use Cache Coherent MTYPE instead of default MTYPE */ 820 #define AMDGPU_VM_MTYPE_CC (3 << 5) 821 /* Use UnCached MTYPE instead of default MTYPE */ 822 #define AMDGPU_VM_MTYPE_UC (4 << 5) 823 /* Use Read Write MTYPE instead of default MTYPE */ 824 #define AMDGPU_VM_MTYPE_RW (5 << 5) 825 /* don't allocate MALL */ 826 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 827 828 struct drm_amdgpu_gem_va { 829 /** GEM object handle */ 830 __u32 handle; 831 __u32 _pad; 832 /** AMDGPU_VA_OP_* */ 833 __u32 operation; 834 /** AMDGPU_VM_PAGE_* */ 835 __u32 flags; 836 /** va address to assign . Must be correctly aligned.*/ 837 __u64 va_address; 838 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 839 __u64 offset_in_bo; 840 /** Specify mapping size. Must be correctly aligned. */ 841 __u64 map_size; 842 /** 843 * vm_timeline_point is a sequence number used to add new timeline point. 844 */ 845 __u64 vm_timeline_point; 846 /** 847 * The vm page table update fence is installed in given vm_timeline_syncobj_out 848 * at vm_timeline_point. 849 */ 850 __u32 vm_timeline_syncobj_out; 851 /** the number of syncobj handles in @input_fence_syncobj_handles */ 852 __u32 num_syncobj_handles; 853 /** Array of sync object handle to wait for given input fences */ 854 __u64 input_fence_syncobj_handles; 855 }; 856 857 #define AMDGPU_HW_IP_GFX 0 858 #define AMDGPU_HW_IP_COMPUTE 1 859 #define AMDGPU_HW_IP_DMA 2 860 #define AMDGPU_HW_IP_UVD 3 861 #define AMDGPU_HW_IP_VCE 4 862 #define AMDGPU_HW_IP_UVD_ENC 5 863 #define AMDGPU_HW_IP_VCN_DEC 6 864 /* 865 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 866 * both encoding and decoding jobs. 867 */ 868 #define AMDGPU_HW_IP_VCN_ENC 7 869 #define AMDGPU_HW_IP_VCN_JPEG 8 870 #define AMDGPU_HW_IP_VPE 9 871 #define AMDGPU_HW_IP_NUM 10 872 873 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 874 875 #define AMDGPU_CHUNK_ID_IB 0x01 876 #define AMDGPU_CHUNK_ID_FENCE 0x02 877 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 878 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 879 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 880 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 881 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 882 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 883 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 884 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 885 886 struct drm_amdgpu_cs_chunk { 887 __u32 chunk_id; 888 __u32 length_dw; 889 __u64 chunk_data; 890 }; 891 892 struct drm_amdgpu_cs_in { 893 /** Rendering context id */ 894 __u32 ctx_id; 895 /** Handle of resource list associated with CS */ 896 __u32 bo_list_handle; 897 __u32 num_chunks; 898 __u32 flags; 899 /** this points to __u64 * which point to cs chunks */ 900 __u64 chunks; 901 }; 902 903 struct drm_amdgpu_cs_out { 904 __u64 handle; 905 }; 906 907 union drm_amdgpu_cs { 908 struct drm_amdgpu_cs_in in; 909 struct drm_amdgpu_cs_out out; 910 }; 911 912 /* Specify flags to be used for IB */ 913 914 /* This IB should be submitted to CE */ 915 #define AMDGPU_IB_FLAG_CE (1<<0) 916 917 /* Preamble flag, which means the IB could be dropped if no context switch */ 918 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 919 920 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 921 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 922 923 /* The IB fence should do the L2 writeback but not invalidate any shader 924 * caches (L2/vL1/sL1/I$). */ 925 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 926 927 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 928 * This will reset wave ID counters for the IB. 929 */ 930 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 931 932 /* Flag the IB as secure (TMZ) 933 */ 934 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 935 936 /* Tell KMD to flush and invalidate caches 937 */ 938 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 939 940 struct drm_amdgpu_cs_chunk_ib { 941 __u32 _pad; 942 /** AMDGPU_IB_FLAG_* */ 943 __u32 flags; 944 /** Virtual address to begin IB execution */ 945 __u64 va_start; 946 /** Size of submission */ 947 __u32 ib_bytes; 948 /** HW IP to submit to */ 949 __u32 ip_type; 950 /** HW IP index of the same type to submit to */ 951 __u32 ip_instance; 952 /** Ring index to submit to */ 953 __u32 ring; 954 }; 955 956 struct drm_amdgpu_cs_chunk_dep { 957 __u32 ip_type; 958 __u32 ip_instance; 959 __u32 ring; 960 __u32 ctx_id; 961 __u64 handle; 962 }; 963 964 struct drm_amdgpu_cs_chunk_fence { 965 __u32 handle; 966 __u32 offset; 967 }; 968 969 struct drm_amdgpu_cs_chunk_sem { 970 __u32 handle; 971 }; 972 973 struct drm_amdgpu_cs_chunk_syncobj { 974 __u32 handle; 975 __u32 flags; 976 __u64 point; 977 }; 978 979 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 980 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 981 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 982 983 union drm_amdgpu_fence_to_handle { 984 struct { 985 struct drm_amdgpu_fence fence; 986 __u32 what; 987 __u32 pad; 988 } in; 989 struct { 990 __u32 handle; 991 } out; 992 }; 993 994 struct drm_amdgpu_cs_chunk_data { 995 union { 996 struct drm_amdgpu_cs_chunk_ib ib_data; 997 struct drm_amdgpu_cs_chunk_fence fence_data; 998 }; 999 }; 1000 1001 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 1002 1003 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 1004 __u64 shadow_va; 1005 __u64 csa_va; 1006 __u64 gds_va; 1007 __u64 flags; 1008 }; 1009 1010 /* 1011 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 1012 * 1013 */ 1014 #define AMDGPU_IDS_FLAGS_FUSION 0x1 1015 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 1016 #define AMDGPU_IDS_FLAGS_TMZ 0x4 1017 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 1018 1019 /* 1020 * Query h/w info: Flag identifying VF/PF/PT mode 1021 * 1022 */ 1023 #define AMDGPU_IDS_FLAGS_MODE_MASK 0x300 1024 #define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8 1025 #define AMDGPU_IDS_FLAGS_MODE_PF 0x0 1026 #define AMDGPU_IDS_FLAGS_MODE_VF 0x1 1027 #define AMDGPU_IDS_FLAGS_MODE_PT 0x2 1028 1029 /* indicate if acceleration can be working */ 1030 #define AMDGPU_INFO_ACCEL_WORKING 0x00 1031 /* get the crtc_id from the mode object id? */ 1032 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 1033 /* query hw IP info */ 1034 #define AMDGPU_INFO_HW_IP_INFO 0x02 1035 /* query hw IP instance count for the specified type */ 1036 #define AMDGPU_INFO_HW_IP_COUNT 0x03 1037 /* timestamp for GL_ARB_timer_query */ 1038 #define AMDGPU_INFO_TIMESTAMP 0x05 1039 /* Query the firmware version */ 1040 #define AMDGPU_INFO_FW_VERSION 0x0e 1041 /* Subquery id: Query VCE firmware version */ 1042 #define AMDGPU_INFO_FW_VCE 0x1 1043 /* Subquery id: Query UVD firmware version */ 1044 #define AMDGPU_INFO_FW_UVD 0x2 1045 /* Subquery id: Query GMC firmware version */ 1046 #define AMDGPU_INFO_FW_GMC 0x03 1047 /* Subquery id: Query GFX ME firmware version */ 1048 #define AMDGPU_INFO_FW_GFX_ME 0x04 1049 /* Subquery id: Query GFX PFP firmware version */ 1050 #define AMDGPU_INFO_FW_GFX_PFP 0x05 1051 /* Subquery id: Query GFX CE firmware version */ 1052 #define AMDGPU_INFO_FW_GFX_CE 0x06 1053 /* Subquery id: Query GFX RLC firmware version */ 1054 #define AMDGPU_INFO_FW_GFX_RLC 0x07 1055 /* Subquery id: Query GFX MEC firmware version */ 1056 #define AMDGPU_INFO_FW_GFX_MEC 0x08 1057 /* Subquery id: Query SMC firmware version */ 1058 #define AMDGPU_INFO_FW_SMC 0x0a 1059 /* Subquery id: Query SDMA firmware version */ 1060 #define AMDGPU_INFO_FW_SDMA 0x0b 1061 /* Subquery id: Query PSP SOS firmware version */ 1062 #define AMDGPU_INFO_FW_SOS 0x0c 1063 /* Subquery id: Query PSP ASD firmware version */ 1064 #define AMDGPU_INFO_FW_ASD 0x0d 1065 /* Subquery id: Query VCN firmware version */ 1066 #define AMDGPU_INFO_FW_VCN 0x0e 1067 /* Subquery id: Query GFX RLC SRLC firmware version */ 1068 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 1069 /* Subquery id: Query GFX RLC SRLG firmware version */ 1070 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 1071 /* Subquery id: Query GFX RLC SRLS firmware version */ 1072 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 1073 /* Subquery id: Query DMCU firmware version */ 1074 #define AMDGPU_INFO_FW_DMCU 0x12 1075 #define AMDGPU_INFO_FW_TA 0x13 1076 /* Subquery id: Query DMCUB firmware version */ 1077 #define AMDGPU_INFO_FW_DMCUB 0x14 1078 /* Subquery id: Query TOC firmware version */ 1079 #define AMDGPU_INFO_FW_TOC 0x15 1080 /* Subquery id: Query CAP firmware version */ 1081 #define AMDGPU_INFO_FW_CAP 0x16 1082 /* Subquery id: Query GFX RLCP firmware version */ 1083 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 1084 /* Subquery id: Query GFX RLCV firmware version */ 1085 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 1086 /* Subquery id: Query MES_KIQ firmware version */ 1087 #define AMDGPU_INFO_FW_MES_KIQ 0x19 1088 /* Subquery id: Query MES firmware version */ 1089 #define AMDGPU_INFO_FW_MES 0x1a 1090 /* Subquery id: Query IMU firmware version */ 1091 #define AMDGPU_INFO_FW_IMU 0x1b 1092 /* Subquery id: Query VPE firmware version */ 1093 #define AMDGPU_INFO_FW_VPE 0x1c 1094 1095 /* number of bytes moved for TTM migration */ 1096 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 1097 /* the used VRAM size */ 1098 #define AMDGPU_INFO_VRAM_USAGE 0x10 1099 /* the used GTT size */ 1100 #define AMDGPU_INFO_GTT_USAGE 0x11 1101 /* Information about GDS, etc. resource configuration */ 1102 #define AMDGPU_INFO_GDS_CONFIG 0x13 1103 /* Query information about VRAM and GTT domains */ 1104 #define AMDGPU_INFO_VRAM_GTT 0x14 1105 /* Query information about register in MMR address space*/ 1106 #define AMDGPU_INFO_READ_MMR_REG 0x15 1107 /* Query information about device: rev id, family, etc. */ 1108 #define AMDGPU_INFO_DEV_INFO 0x16 1109 /* visible vram usage */ 1110 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 1111 /* number of TTM buffer evictions */ 1112 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 1113 /* Query memory about VRAM and GTT domains */ 1114 #define AMDGPU_INFO_MEMORY 0x19 1115 /* Query vce clock table */ 1116 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 1117 /* Query vbios related information */ 1118 #define AMDGPU_INFO_VBIOS 0x1B 1119 /* Subquery id: Query vbios size */ 1120 #define AMDGPU_INFO_VBIOS_SIZE 0x1 1121 /* Subquery id: Query vbios image */ 1122 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 1123 /* Subquery id: Query vbios info */ 1124 #define AMDGPU_INFO_VBIOS_INFO 0x3 1125 /* Query UVD handles */ 1126 #define AMDGPU_INFO_NUM_HANDLES 0x1C 1127 /* Query sensor related information */ 1128 #define AMDGPU_INFO_SENSOR 0x1D 1129 /* Subquery id: Query GPU shader clock */ 1130 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 1131 /* Subquery id: Query GPU memory clock */ 1132 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 1133 /* Subquery id: Query GPU temperature */ 1134 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 1135 /* Subquery id: Query GPU load */ 1136 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 1137 /* Subquery id: Query average GPU power */ 1138 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 1139 /* Subquery id: Query northbridge voltage */ 1140 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 1141 /* Subquery id: Query graphics voltage */ 1142 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 1143 /* Subquery id: Query GPU stable pstate shader clock */ 1144 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 1145 /* Subquery id: Query GPU stable pstate memory clock */ 1146 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 1147 /* Subquery id: Query GPU peak pstate shader clock */ 1148 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 1149 /* Subquery id: Query GPU peak pstate memory clock */ 1150 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 1151 /* Subquery id: Query input GPU power */ 1152 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 1153 /* Number of VRAM page faults on CPU access. */ 1154 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 1155 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 1156 /* query ras mask of enabled features*/ 1157 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 1158 /* RAS MASK: UMC (VRAM) */ 1159 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 1160 /* RAS MASK: SDMA */ 1161 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 1162 /* RAS MASK: GFX */ 1163 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 1164 /* RAS MASK: MMHUB */ 1165 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 1166 /* RAS MASK: ATHUB */ 1167 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 1168 /* RAS MASK: PCIE */ 1169 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 1170 /* RAS MASK: HDP */ 1171 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 1172 /* RAS MASK: XGMI */ 1173 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 1174 /* RAS MASK: DF */ 1175 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 1176 /* RAS MASK: SMN */ 1177 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 1178 /* RAS MASK: SEM */ 1179 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 1180 /* RAS MASK: MP0 */ 1181 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 1182 /* RAS MASK: MP1 */ 1183 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 1184 /* RAS MASK: FUSE */ 1185 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 1186 /* query video encode/decode caps */ 1187 #define AMDGPU_INFO_VIDEO_CAPS 0x21 1188 /* Subquery id: Decode */ 1189 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 1190 /* Subquery id: Encode */ 1191 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 1192 /* Query the max number of IBs per gang per submission */ 1193 #define AMDGPU_INFO_MAX_IBS 0x22 1194 /* query last page fault info */ 1195 #define AMDGPU_INFO_GPUVM_FAULT 0x23 1196 /* query FW object size and alignment */ 1197 #define AMDGPU_INFO_UQ_FW_AREAS 0x24 1198 1199 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 1200 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 1201 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 1202 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 1203 1204 struct drm_amdgpu_query_fw { 1205 /** AMDGPU_INFO_FW_* */ 1206 __u32 fw_type; 1207 /** 1208 * Index of the IP if there are more IPs of 1209 * the same type. 1210 */ 1211 __u32 ip_instance; 1212 /** 1213 * Index of the engine. Whether this is used depends 1214 * on the firmware type. (e.g. MEC, SDMA) 1215 */ 1216 __u32 index; 1217 __u32 _pad; 1218 }; 1219 1220 /* Input structure for the INFO ioctl */ 1221 struct drm_amdgpu_info { 1222 /* Where the return value will be stored */ 1223 __u64 return_pointer; 1224 /* The size of the return value. Just like "size" in "snprintf", 1225 * it limits how many bytes the kernel can write. */ 1226 __u32 return_size; 1227 /* The query request id. */ 1228 __u32 query; 1229 1230 union { 1231 struct { 1232 __u32 id; 1233 __u32 _pad; 1234 } mode_crtc; 1235 1236 struct { 1237 /** AMDGPU_HW_IP_* */ 1238 __u32 type; 1239 /** 1240 * Index of the IP if there are more IPs of the same 1241 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 1242 */ 1243 __u32 ip_instance; 1244 } query_hw_ip; 1245 1246 struct { 1247 __u32 dword_offset; 1248 /** number of registers to read */ 1249 __u32 count; 1250 __u32 instance; 1251 /** For future use, no flags defined so far */ 1252 __u32 flags; 1253 } read_mmr_reg; 1254 1255 struct drm_amdgpu_query_fw query_fw; 1256 1257 struct { 1258 __u32 type; 1259 __u32 offset; 1260 } vbios_info; 1261 1262 struct { 1263 __u32 type; 1264 } sensor_info; 1265 1266 struct { 1267 __u32 type; 1268 } video_cap; 1269 }; 1270 }; 1271 1272 struct drm_amdgpu_info_gds { 1273 /** GDS GFX partition size */ 1274 __u32 gds_gfx_partition_size; 1275 /** GDS compute partition size */ 1276 __u32 compute_partition_size; 1277 /** total GDS memory size */ 1278 __u32 gds_total_size; 1279 /** GWS size per GFX partition */ 1280 __u32 gws_per_gfx_partition; 1281 /** GSW size per compute partition */ 1282 __u32 gws_per_compute_partition; 1283 /** OA size per GFX partition */ 1284 __u32 oa_per_gfx_partition; 1285 /** OA size per compute partition */ 1286 __u32 oa_per_compute_partition; 1287 __u32 _pad; 1288 }; 1289 1290 struct drm_amdgpu_info_vram_gtt { 1291 __u64 vram_size; 1292 __u64 vram_cpu_accessible_size; 1293 __u64 gtt_size; 1294 }; 1295 1296 struct drm_amdgpu_heap_info { 1297 /** max. physical memory */ 1298 __u64 total_heap_size; 1299 1300 /** Theoretical max. available memory in the given heap */ 1301 __u64 usable_heap_size; 1302 1303 /** 1304 * Number of bytes allocated in the heap. This includes all processes 1305 * and private allocations in the kernel. It changes when new buffers 1306 * are allocated, freed, and moved. It cannot be larger than 1307 * heap_size. 1308 */ 1309 __u64 heap_usage; 1310 1311 /** 1312 * Theoretical possible max. size of buffer which 1313 * could be allocated in the given heap 1314 */ 1315 __u64 max_allocation; 1316 }; 1317 1318 struct drm_amdgpu_memory_info { 1319 struct drm_amdgpu_heap_info vram; 1320 struct drm_amdgpu_heap_info cpu_accessible_vram; 1321 struct drm_amdgpu_heap_info gtt; 1322 }; 1323 1324 struct drm_amdgpu_info_firmware { 1325 __u32 ver; 1326 __u32 feature; 1327 }; 1328 1329 struct drm_amdgpu_info_vbios { 1330 __u8 name[64]; 1331 __u8 vbios_pn[64]; 1332 __u32 version; 1333 __u32 pad; 1334 __u8 vbios_ver_str[32]; 1335 __u8 date[32]; 1336 }; 1337 1338 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 1339 #define AMDGPU_VRAM_TYPE_GDDR1 1 1340 #define AMDGPU_VRAM_TYPE_DDR2 2 1341 #define AMDGPU_VRAM_TYPE_GDDR3 3 1342 #define AMDGPU_VRAM_TYPE_GDDR4 4 1343 #define AMDGPU_VRAM_TYPE_GDDR5 5 1344 #define AMDGPU_VRAM_TYPE_HBM 6 1345 #define AMDGPU_VRAM_TYPE_DDR3 7 1346 #define AMDGPU_VRAM_TYPE_DDR4 8 1347 #define AMDGPU_VRAM_TYPE_GDDR6 9 1348 #define AMDGPU_VRAM_TYPE_DDR5 10 1349 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1350 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1351 1352 struct drm_amdgpu_info_device { 1353 /** PCI Device ID */ 1354 __u32 device_id; 1355 /** Internal chip revision: A0, A1, etc.) */ 1356 __u32 chip_rev; 1357 __u32 external_rev; 1358 /** Revision id in PCI Config space */ 1359 __u32 pci_rev; 1360 __u32 family; 1361 __u32 num_shader_engines; 1362 __u32 num_shader_arrays_per_engine; 1363 /* in KHz */ 1364 __u32 gpu_counter_freq; 1365 __u64 max_engine_clock; 1366 __u64 max_memory_clock; 1367 /* cu information */ 1368 __u32 cu_active_number; 1369 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1370 __u32 cu_ao_mask; 1371 __u32 cu_bitmap[4][4]; 1372 /** Render backend pipe mask. One render backend is CB+DB. */ 1373 __u32 enabled_rb_pipes_mask; 1374 __u32 num_rb_pipes; 1375 __u32 num_hw_gfx_contexts; 1376 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1377 __u32 pcie_gen; 1378 __u64 ids_flags; 1379 /** Starting virtual address for UMDs. */ 1380 __u64 virtual_address_offset; 1381 /** The maximum virtual address */ 1382 __u64 virtual_address_max; 1383 /** Required alignment of virtual addresses. */ 1384 __u32 virtual_address_alignment; 1385 /** Page table entry - fragment size */ 1386 __u32 pte_fragment_size; 1387 __u32 gart_page_size; 1388 /** constant engine ram size*/ 1389 __u32 ce_ram_size; 1390 /** video memory type info*/ 1391 __u32 vram_type; 1392 /** video memory bit width*/ 1393 __u32 vram_bit_width; 1394 /* vce harvesting instance */ 1395 __u32 vce_harvest_config; 1396 /* gfx double offchip LDS buffers */ 1397 __u32 gc_double_offchip_lds_buf; 1398 /* NGG Primitive Buffer */ 1399 __u64 prim_buf_gpu_addr; 1400 /* NGG Position Buffer */ 1401 __u64 pos_buf_gpu_addr; 1402 /* NGG Control Sideband */ 1403 __u64 cntl_sb_buf_gpu_addr; 1404 /* NGG Parameter Cache */ 1405 __u64 param_buf_gpu_addr; 1406 __u32 prim_buf_size; 1407 __u32 pos_buf_size; 1408 __u32 cntl_sb_buf_size; 1409 __u32 param_buf_size; 1410 /* wavefront size*/ 1411 __u32 wave_front_size; 1412 /* shader visible vgprs*/ 1413 __u32 num_shader_visible_vgprs; 1414 /* CU per shader array*/ 1415 __u32 num_cu_per_sh; 1416 /* number of tcc blocks*/ 1417 __u32 num_tcc_blocks; 1418 /* gs vgt table depth*/ 1419 __u32 gs_vgt_table_depth; 1420 /* gs primitive buffer depth*/ 1421 __u32 gs_prim_buffer_depth; 1422 /* max gs wavefront per vgt*/ 1423 __u32 max_gs_waves_per_vgt; 1424 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1425 __u32 pcie_num_lanes; 1426 /* always on cu bitmap */ 1427 __u32 cu_ao_bitmap[4][4]; 1428 /** Starting high virtual address for UMDs. */ 1429 __u64 high_va_offset; 1430 /** The maximum high virtual address */ 1431 __u64 high_va_max; 1432 /* gfx10 pa_sc_tile_steering_override */ 1433 __u32 pa_sc_tile_steering_override; 1434 /* disabled TCCs */ 1435 __u64 tcc_disabled_mask; 1436 __u64 min_engine_clock; 1437 __u64 min_memory_clock; 1438 /* The following fields are only set on gfx11+, older chips set 0. */ 1439 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1440 __u32 num_sqc_per_wgp; 1441 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1442 __u32 sqc_inst_cache_size; 1443 __u32 gl1c_cache_size; 1444 __u32 gl2c_cache_size; 1445 __u64 mall_size; /* AKA infinity cache */ 1446 /* high 32 bits of the rb pipes mask */ 1447 __u32 enabled_rb_pipes_mask_hi; 1448 /* shadow area size for gfx11 */ 1449 __u32 shadow_size; 1450 /* shadow area base virtual alignment for gfx11 */ 1451 __u32 shadow_alignment; 1452 /* context save area size for gfx11 */ 1453 __u32 csa_size; 1454 /* context save area base virtual alignment for gfx11 */ 1455 __u32 csa_alignment; 1456 /* Userq IP mask (1 << AMDGPU_HW_IP_*) */ 1457 __u32 userq_ip_mask; 1458 __u32 pad; 1459 }; 1460 1461 struct drm_amdgpu_info_hw_ip { 1462 /** Version of h/w IP */ 1463 __u32 hw_ip_version_major; 1464 __u32 hw_ip_version_minor; 1465 /** Capabilities */ 1466 __u64 capabilities_flags; 1467 /** command buffer address start alignment*/ 1468 __u32 ib_start_alignment; 1469 /** command buffer size alignment*/ 1470 __u32 ib_size_alignment; 1471 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1472 __u32 available_rings; 1473 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1474 __u32 ip_discovery_version; 1475 }; 1476 1477 /* GFX metadata BO sizes and alignment info (in bytes) */ 1478 struct drm_amdgpu_info_uq_fw_areas_gfx { 1479 /* shadow area size */ 1480 __u32 shadow_size; 1481 /* shadow area base virtual mem alignment */ 1482 __u32 shadow_alignment; 1483 /* context save area size */ 1484 __u32 csa_size; 1485 /* context save area base virtual mem alignment */ 1486 __u32 csa_alignment; 1487 }; 1488 1489 /* IP specific fw related information used in the 1490 * subquery AMDGPU_INFO_UQ_FW_AREAS 1491 */ 1492 struct drm_amdgpu_info_uq_fw_areas { 1493 union { 1494 struct drm_amdgpu_info_uq_fw_areas_gfx gfx; 1495 }; 1496 }; 1497 1498 struct drm_amdgpu_info_num_handles { 1499 /** Max handles as supported by firmware for UVD */ 1500 __u32 uvd_max_handles; 1501 /** Handles currently in use for UVD */ 1502 __u32 uvd_used_handles; 1503 }; 1504 1505 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1506 1507 struct drm_amdgpu_info_vce_clock_table_entry { 1508 /** System clock */ 1509 __u32 sclk; 1510 /** Memory clock */ 1511 __u32 mclk; 1512 /** VCE clock */ 1513 __u32 eclk; 1514 __u32 pad; 1515 }; 1516 1517 struct drm_amdgpu_info_vce_clock_table { 1518 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1519 __u32 num_valid_entries; 1520 __u32 pad; 1521 }; 1522 1523 /* query video encode/decode caps */ 1524 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1525 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1526 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1527 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1528 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1529 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1530 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1531 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1532 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1533 1534 struct drm_amdgpu_info_video_codec_info { 1535 __u32 valid; 1536 __u32 max_width; 1537 __u32 max_height; 1538 __u32 max_pixels_per_frame; 1539 __u32 max_level; 1540 __u32 pad; 1541 }; 1542 1543 struct drm_amdgpu_info_video_caps { 1544 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1545 }; 1546 1547 #define AMDGPU_VMHUB_TYPE_MASK 0xff 1548 #define AMDGPU_VMHUB_TYPE_SHIFT 0 1549 #define AMDGPU_VMHUB_TYPE_GFX 0 1550 #define AMDGPU_VMHUB_TYPE_MM0 1 1551 #define AMDGPU_VMHUB_TYPE_MM1 2 1552 #define AMDGPU_VMHUB_IDX_MASK 0xff00 1553 #define AMDGPU_VMHUB_IDX_SHIFT 8 1554 1555 struct drm_amdgpu_info_gpuvm_fault { 1556 __u64 addr; 1557 __u32 status; 1558 __u32 vmhub; 1559 }; 1560 1561 struct drm_amdgpu_info_uq_metadata_gfx { 1562 /* shadow area size for gfx11 */ 1563 __u32 shadow_size; 1564 /* shadow area base virtual alignment for gfx11 */ 1565 __u32 shadow_alignment; 1566 /* context save area size for gfx11 */ 1567 __u32 csa_size; 1568 /* context save area base virtual alignment for gfx11 */ 1569 __u32 csa_alignment; 1570 }; 1571 1572 struct drm_amdgpu_info_uq_metadata { 1573 union { 1574 struct drm_amdgpu_info_uq_metadata_gfx gfx; 1575 }; 1576 }; 1577 1578 /* 1579 * Supported GPU families 1580 */ 1581 #define AMDGPU_FAMILY_UNKNOWN 0 1582 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1583 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1584 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1585 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1586 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1587 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1588 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1589 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1590 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1591 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1592 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1593 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1594 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1595 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1596 #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ 1597 #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ 1598 1599 /* FIXME wrong namespace! */ 1600 struct drm_color_ctm_3x4 { 1601 /* 1602 * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude 1603 * (not two's complement!) format. 1604 */ 1605 __u64 matrix[12]; 1606 }; 1607 1608 #if defined(__cplusplus) 1609 } 1610 #endif 1611 1612 #endif 1613