1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linezrized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 */ 98 #define AMDGPU_GEM_DOMAIN_CPU 0x1 99 #define AMDGPU_GEM_DOMAIN_GTT 0x2 100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 101 #define AMDGPU_GEM_DOMAIN_GDS 0x8 102 #define AMDGPU_GEM_DOMAIN_GWS 0x10 103 #define AMDGPU_GEM_DOMAIN_OA 0x20 104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 105 AMDGPU_GEM_DOMAIN_GTT | \ 106 AMDGPU_GEM_DOMAIN_VRAM | \ 107 AMDGPU_GEM_DOMAIN_GDS | \ 108 AMDGPU_GEM_DOMAIN_GWS | \ 109 AMDGPU_GEM_DOMAIN_OA) 110 111 /* Flag that CPU access will be required for the case of VRAM domain */ 112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 113 /* Flag that CPU access will not work, this VRAM domain is invisible */ 114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 115 /* Flag that USWC attributes should be used for GTT */ 116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 117 /* Flag that the memory should be in VRAM and cleared */ 118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119 /* Flag that allocating the BO should use linear VRAM */ 120 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 121 /* Flag that BO is always valid in this VM */ 122 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 123 /* Flag that BO sharing will be explicitly synchronized */ 124 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 125 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 126 * for the second page onward should be set to NC. It should never 127 * be used by user space applications. 128 */ 129 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 130 /* Flag that BO may contain sensitive data that must be wiped before 131 * releasing the memory 132 */ 133 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 134 /* Flag that BO will be encrypted and that the TMZ bit should be 135 * set in the PTEs when mapping this buffer via GPUVM or 136 * accessing it with various hw blocks 137 */ 138 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 139 140 struct drm_amdgpu_gem_create_in { 141 /** the requested memory size */ 142 __u64 bo_size; 143 /** physical start_addr alignment in bytes for some HW requirements */ 144 __u64 alignment; 145 /** the requested memory domains */ 146 __u64 domains; 147 /** allocation flags */ 148 __u64 domain_flags; 149 }; 150 151 struct drm_amdgpu_gem_create_out { 152 /** returned GEM object handle */ 153 __u32 handle; 154 __u32 _pad; 155 }; 156 157 union drm_amdgpu_gem_create { 158 struct drm_amdgpu_gem_create_in in; 159 struct drm_amdgpu_gem_create_out out; 160 }; 161 162 /** Opcode to create new residency list. */ 163 #define AMDGPU_BO_LIST_OP_CREATE 0 164 /** Opcode to destroy previously created residency list */ 165 #define AMDGPU_BO_LIST_OP_DESTROY 1 166 /** Opcode to update resource information in the list */ 167 #define AMDGPU_BO_LIST_OP_UPDATE 2 168 169 struct drm_amdgpu_bo_list_in { 170 /** Type of operation */ 171 __u32 operation; 172 /** Handle of list or 0 if we want to create one */ 173 __u32 list_handle; 174 /** Number of BOs in list */ 175 __u32 bo_number; 176 /** Size of each element describing BO */ 177 __u32 bo_info_size; 178 /** Pointer to array describing BOs */ 179 __u64 bo_info_ptr; 180 }; 181 182 struct drm_amdgpu_bo_list_entry { 183 /** Handle of BO */ 184 __u32 bo_handle; 185 /** New (if specified) BO priority to be used during migration */ 186 __u32 bo_priority; 187 }; 188 189 struct drm_amdgpu_bo_list_out { 190 /** Handle of resource list */ 191 __u32 list_handle; 192 __u32 _pad; 193 }; 194 195 union drm_amdgpu_bo_list { 196 struct drm_amdgpu_bo_list_in in; 197 struct drm_amdgpu_bo_list_out out; 198 }; 199 200 /* context related */ 201 #define AMDGPU_CTX_OP_ALLOC_CTX 1 202 #define AMDGPU_CTX_OP_FREE_CTX 2 203 #define AMDGPU_CTX_OP_QUERY_STATE 3 204 #define AMDGPU_CTX_OP_QUERY_STATE2 4 205 206 /* GPU reset status */ 207 #define AMDGPU_CTX_NO_RESET 0 208 /* this the context caused it */ 209 #define AMDGPU_CTX_GUILTY_RESET 1 210 /* some other context caused it */ 211 #define AMDGPU_CTX_INNOCENT_RESET 2 212 /* unknown cause */ 213 #define AMDGPU_CTX_UNKNOWN_RESET 3 214 215 /* indicate gpu reset occured after ctx created */ 216 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 217 /* indicate vram lost occured after ctx created */ 218 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 219 /* indicate some job from this context once cause gpu hang */ 220 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 221 /* indicate some errors are detected by RAS */ 222 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 223 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 224 225 /* Context priority level */ 226 #define AMDGPU_CTX_PRIORITY_UNSET -2048 227 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 228 #define AMDGPU_CTX_PRIORITY_LOW -512 229 #define AMDGPU_CTX_PRIORITY_NORMAL 0 230 /* 231 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 232 * CAP_SYS_NICE or DRM_MASTER 233 */ 234 #define AMDGPU_CTX_PRIORITY_HIGH 512 235 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 236 237 struct drm_amdgpu_ctx_in { 238 /** AMDGPU_CTX_OP_* */ 239 __u32 op; 240 /** For future use, no flags defined so far */ 241 __u32 flags; 242 __u32 ctx_id; 243 /** AMDGPU_CTX_PRIORITY_* */ 244 __s32 priority; 245 }; 246 247 union drm_amdgpu_ctx_out { 248 struct { 249 __u32 ctx_id; 250 __u32 _pad; 251 } alloc; 252 253 struct { 254 /** For future use, no flags defined so far */ 255 __u64 flags; 256 /** Number of resets caused by this context so far. */ 257 __u32 hangs; 258 /** Reset status since the last call of the ioctl. */ 259 __u32 reset_status; 260 } state; 261 }; 262 263 union drm_amdgpu_ctx { 264 struct drm_amdgpu_ctx_in in; 265 union drm_amdgpu_ctx_out out; 266 }; 267 268 /* vm ioctl */ 269 #define AMDGPU_VM_OP_RESERVE_VMID 1 270 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 271 272 struct drm_amdgpu_vm_in { 273 /** AMDGPU_VM_OP_* */ 274 __u32 op; 275 __u32 flags; 276 }; 277 278 struct drm_amdgpu_vm_out { 279 /** For future use, no flags defined so far */ 280 __u64 flags; 281 }; 282 283 union drm_amdgpu_vm { 284 struct drm_amdgpu_vm_in in; 285 struct drm_amdgpu_vm_out out; 286 }; 287 288 /* sched ioctl */ 289 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 290 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 291 292 struct drm_amdgpu_sched_in { 293 /* AMDGPU_SCHED_OP_* */ 294 __u32 op; 295 __u32 fd; 296 /** AMDGPU_CTX_PRIORITY_* */ 297 __s32 priority; 298 __u32 ctx_id; 299 }; 300 301 union drm_amdgpu_sched { 302 struct drm_amdgpu_sched_in in; 303 }; 304 305 /* 306 * This is not a reliable API and you should expect it to fail for any 307 * number of reasons and have fallback path that do not use userptr to 308 * perform any operation. 309 */ 310 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 311 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 312 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 313 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 314 315 struct drm_amdgpu_gem_userptr { 316 __u64 addr; 317 __u64 size; 318 /* AMDGPU_GEM_USERPTR_* */ 319 __u32 flags; 320 /* Resulting GEM handle */ 321 __u32 handle; 322 }; 323 324 /* SI-CI-VI: */ 325 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 326 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 327 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 328 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 329 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 330 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 331 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 332 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 333 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 334 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 335 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 336 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 337 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 338 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 339 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 340 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 341 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 342 343 /* GFX9 and later: */ 344 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 345 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 346 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 347 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 348 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 349 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 350 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 351 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 352 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 353 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 354 #define AMDGPU_TILING_SCANOUT_SHIFT 63 355 #define AMDGPU_TILING_SCANOUT_MASK 0x1 356 357 /* Set/Get helpers for tiling flags. */ 358 #define AMDGPU_TILING_SET(field, value) \ 359 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 360 #define AMDGPU_TILING_GET(value, field) \ 361 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 362 363 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 364 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 365 366 /** The same structure is shared for input/output */ 367 struct drm_amdgpu_gem_metadata { 368 /** GEM Object handle */ 369 __u32 handle; 370 /** Do we want get or set metadata */ 371 __u32 op; 372 struct { 373 /** For future use, no flags defined so far */ 374 __u64 flags; 375 /** family specific tiling info */ 376 __u64 tiling_info; 377 __u32 data_size_bytes; 378 __u32 data[64]; 379 } data; 380 }; 381 382 struct drm_amdgpu_gem_mmap_in { 383 /** the GEM object handle */ 384 __u32 handle; 385 __u32 _pad; 386 }; 387 388 struct drm_amdgpu_gem_mmap_out { 389 /** mmap offset from the vma offset manager */ 390 __u64 addr_ptr; 391 }; 392 393 union drm_amdgpu_gem_mmap { 394 struct drm_amdgpu_gem_mmap_in in; 395 struct drm_amdgpu_gem_mmap_out out; 396 }; 397 398 struct drm_amdgpu_gem_wait_idle_in { 399 /** GEM object handle */ 400 __u32 handle; 401 /** For future use, no flags defined so far */ 402 __u32 flags; 403 /** Absolute timeout to wait */ 404 __u64 timeout; 405 }; 406 407 struct drm_amdgpu_gem_wait_idle_out { 408 /** BO status: 0 - BO is idle, 1 - BO is busy */ 409 __u32 status; 410 /** Returned current memory domain */ 411 __u32 domain; 412 }; 413 414 union drm_amdgpu_gem_wait_idle { 415 struct drm_amdgpu_gem_wait_idle_in in; 416 struct drm_amdgpu_gem_wait_idle_out out; 417 }; 418 419 struct drm_amdgpu_wait_cs_in { 420 /* Command submission handle 421 * handle equals 0 means none to wait for 422 * handle equals ~0ull means wait for the latest sequence number 423 */ 424 __u64 handle; 425 /** Absolute timeout to wait */ 426 __u64 timeout; 427 __u32 ip_type; 428 __u32 ip_instance; 429 __u32 ring; 430 __u32 ctx_id; 431 }; 432 433 struct drm_amdgpu_wait_cs_out { 434 /** CS status: 0 - CS completed, 1 - CS still busy */ 435 __u64 status; 436 }; 437 438 union drm_amdgpu_wait_cs { 439 struct drm_amdgpu_wait_cs_in in; 440 struct drm_amdgpu_wait_cs_out out; 441 }; 442 443 struct drm_amdgpu_fence { 444 __u32 ctx_id; 445 __u32 ip_type; 446 __u32 ip_instance; 447 __u32 ring; 448 __u64 seq_no; 449 }; 450 451 struct drm_amdgpu_wait_fences_in { 452 /** This points to uint64_t * which points to fences */ 453 __u64 fences; 454 __u32 fence_count; 455 __u32 wait_all; 456 __u64 timeout_ns; 457 }; 458 459 struct drm_amdgpu_wait_fences_out { 460 __u32 status; 461 __u32 first_signaled; 462 }; 463 464 union drm_amdgpu_wait_fences { 465 struct drm_amdgpu_wait_fences_in in; 466 struct drm_amdgpu_wait_fences_out out; 467 }; 468 469 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 470 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 471 472 /* Sets or returns a value associated with a buffer. */ 473 struct drm_amdgpu_gem_op { 474 /** GEM object handle */ 475 __u32 handle; 476 /** AMDGPU_GEM_OP_* */ 477 __u32 op; 478 /** Input or return value */ 479 __u64 value; 480 }; 481 482 #define AMDGPU_VA_OP_MAP 1 483 #define AMDGPU_VA_OP_UNMAP 2 484 #define AMDGPU_VA_OP_CLEAR 3 485 #define AMDGPU_VA_OP_REPLACE 4 486 487 /* Delay the page table update till the next CS */ 488 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 489 490 /* Mapping flags */ 491 /* readable mapping */ 492 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 493 /* writable mapping */ 494 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 495 /* executable mapping, new for VI */ 496 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 497 /* partially resident texture */ 498 #define AMDGPU_VM_PAGE_PRT (1 << 4) 499 /* MTYPE flags use bit 5 to 8 */ 500 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 501 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 502 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 503 /* Use Non Coherent MTYPE instead of default MTYPE */ 504 #define AMDGPU_VM_MTYPE_NC (1 << 5) 505 /* Use Write Combine MTYPE instead of default MTYPE */ 506 #define AMDGPU_VM_MTYPE_WC (2 << 5) 507 /* Use Cache Coherent MTYPE instead of default MTYPE */ 508 #define AMDGPU_VM_MTYPE_CC (3 << 5) 509 /* Use UnCached MTYPE instead of default MTYPE */ 510 #define AMDGPU_VM_MTYPE_UC (4 << 5) 511 /* Use Read Write MTYPE instead of default MTYPE */ 512 #define AMDGPU_VM_MTYPE_RW (5 << 5) 513 514 struct drm_amdgpu_gem_va { 515 /** GEM object handle */ 516 __u32 handle; 517 __u32 _pad; 518 /** AMDGPU_VA_OP_* */ 519 __u32 operation; 520 /** AMDGPU_VM_PAGE_* */ 521 __u32 flags; 522 /** va address to assign . Must be correctly aligned.*/ 523 __u64 va_address; 524 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 525 __u64 offset_in_bo; 526 /** Specify mapping size. Must be correctly aligned. */ 527 __u64 map_size; 528 }; 529 530 #define AMDGPU_HW_IP_GFX 0 531 #define AMDGPU_HW_IP_COMPUTE 1 532 #define AMDGPU_HW_IP_DMA 2 533 #define AMDGPU_HW_IP_UVD 3 534 #define AMDGPU_HW_IP_VCE 4 535 #define AMDGPU_HW_IP_UVD_ENC 5 536 #define AMDGPU_HW_IP_VCN_DEC 6 537 #define AMDGPU_HW_IP_VCN_ENC 7 538 #define AMDGPU_HW_IP_VCN_JPEG 8 539 #define AMDGPU_HW_IP_NUM 9 540 541 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 542 543 #define AMDGPU_CHUNK_ID_IB 0x01 544 #define AMDGPU_CHUNK_ID_FENCE 0x02 545 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 546 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 547 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 548 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 549 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 550 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 551 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 552 553 struct drm_amdgpu_cs_chunk { 554 __u32 chunk_id; 555 __u32 length_dw; 556 __u64 chunk_data; 557 }; 558 559 struct drm_amdgpu_cs_in { 560 /** Rendering context id */ 561 __u32 ctx_id; 562 /** Handle of resource list associated with CS */ 563 __u32 bo_list_handle; 564 __u32 num_chunks; 565 __u32 flags; 566 /** this points to __u64 * which point to cs chunks */ 567 __u64 chunks; 568 }; 569 570 struct drm_amdgpu_cs_out { 571 __u64 handle; 572 }; 573 574 union drm_amdgpu_cs { 575 struct drm_amdgpu_cs_in in; 576 struct drm_amdgpu_cs_out out; 577 }; 578 579 /* Specify flags to be used for IB */ 580 581 /* This IB should be submitted to CE */ 582 #define AMDGPU_IB_FLAG_CE (1<<0) 583 584 /* Preamble flag, which means the IB could be dropped if no context switch */ 585 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 586 587 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 588 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 589 590 /* The IB fence should do the L2 writeback but not invalidate any shader 591 * caches (L2/vL1/sL1/I$). */ 592 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 593 594 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 595 * This will reset wave ID counters for the IB. 596 */ 597 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 598 599 /* Flag the IB as secure (TMZ) 600 */ 601 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 602 603 /* Tell KMD to flush and invalidate caches 604 */ 605 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 606 607 struct drm_amdgpu_cs_chunk_ib { 608 __u32 _pad; 609 /** AMDGPU_IB_FLAG_* */ 610 __u32 flags; 611 /** Virtual address to begin IB execution */ 612 __u64 va_start; 613 /** Size of submission */ 614 __u32 ib_bytes; 615 /** HW IP to submit to */ 616 __u32 ip_type; 617 /** HW IP index of the same type to submit to */ 618 __u32 ip_instance; 619 /** Ring index to submit to */ 620 __u32 ring; 621 }; 622 623 struct drm_amdgpu_cs_chunk_dep { 624 __u32 ip_type; 625 __u32 ip_instance; 626 __u32 ring; 627 __u32 ctx_id; 628 __u64 handle; 629 }; 630 631 struct drm_amdgpu_cs_chunk_fence { 632 __u32 handle; 633 __u32 offset; 634 }; 635 636 struct drm_amdgpu_cs_chunk_sem { 637 __u32 handle; 638 }; 639 640 struct drm_amdgpu_cs_chunk_syncobj { 641 __u32 handle; 642 __u32 flags; 643 __u64 point; 644 }; 645 646 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 647 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 648 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 649 650 union drm_amdgpu_fence_to_handle { 651 struct { 652 struct drm_amdgpu_fence fence; 653 __u32 what; 654 __u32 pad; 655 } in; 656 struct { 657 __u32 handle; 658 } out; 659 }; 660 661 struct drm_amdgpu_cs_chunk_data { 662 union { 663 struct drm_amdgpu_cs_chunk_ib ib_data; 664 struct drm_amdgpu_cs_chunk_fence fence_data; 665 }; 666 }; 667 668 /* 669 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 670 * 671 */ 672 #define AMDGPU_IDS_FLAGS_FUSION 0x1 673 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 674 #define AMDGPU_IDS_FLAGS_TMZ 0x4 675 676 /* indicate if acceleration can be working */ 677 #define AMDGPU_INFO_ACCEL_WORKING 0x00 678 /* get the crtc_id from the mode object id? */ 679 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 680 /* query hw IP info */ 681 #define AMDGPU_INFO_HW_IP_INFO 0x02 682 /* query hw IP instance count for the specified type */ 683 #define AMDGPU_INFO_HW_IP_COUNT 0x03 684 /* timestamp for GL_ARB_timer_query */ 685 #define AMDGPU_INFO_TIMESTAMP 0x05 686 /* Query the firmware version */ 687 #define AMDGPU_INFO_FW_VERSION 0x0e 688 /* Subquery id: Query VCE firmware version */ 689 #define AMDGPU_INFO_FW_VCE 0x1 690 /* Subquery id: Query UVD firmware version */ 691 #define AMDGPU_INFO_FW_UVD 0x2 692 /* Subquery id: Query GMC firmware version */ 693 #define AMDGPU_INFO_FW_GMC 0x03 694 /* Subquery id: Query GFX ME firmware version */ 695 #define AMDGPU_INFO_FW_GFX_ME 0x04 696 /* Subquery id: Query GFX PFP firmware version */ 697 #define AMDGPU_INFO_FW_GFX_PFP 0x05 698 /* Subquery id: Query GFX CE firmware version */ 699 #define AMDGPU_INFO_FW_GFX_CE 0x06 700 /* Subquery id: Query GFX RLC firmware version */ 701 #define AMDGPU_INFO_FW_GFX_RLC 0x07 702 /* Subquery id: Query GFX MEC firmware version */ 703 #define AMDGPU_INFO_FW_GFX_MEC 0x08 704 /* Subquery id: Query SMC firmware version */ 705 #define AMDGPU_INFO_FW_SMC 0x0a 706 /* Subquery id: Query SDMA firmware version */ 707 #define AMDGPU_INFO_FW_SDMA 0x0b 708 /* Subquery id: Query PSP SOS firmware version */ 709 #define AMDGPU_INFO_FW_SOS 0x0c 710 /* Subquery id: Query PSP ASD firmware version */ 711 #define AMDGPU_INFO_FW_ASD 0x0d 712 /* Subquery id: Query VCN firmware version */ 713 #define AMDGPU_INFO_FW_VCN 0x0e 714 /* Subquery id: Query GFX RLC SRLC firmware version */ 715 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 716 /* Subquery id: Query GFX RLC SRLG firmware version */ 717 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 718 /* Subquery id: Query GFX RLC SRLS firmware version */ 719 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 720 /* Subquery id: Query DMCU firmware version */ 721 #define AMDGPU_INFO_FW_DMCU 0x12 722 #define AMDGPU_INFO_FW_TA 0x13 723 /* Subquery id: Query DMCUB firmware version */ 724 #define AMDGPU_INFO_FW_DMCUB 0x14 725 /* Subquery id: Query TOC firmware version */ 726 #define AMDGPU_INFO_FW_TOC 0x15 727 728 /* number of bytes moved for TTM migration */ 729 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 730 /* the used VRAM size */ 731 #define AMDGPU_INFO_VRAM_USAGE 0x10 732 /* the used GTT size */ 733 #define AMDGPU_INFO_GTT_USAGE 0x11 734 /* Information about GDS, etc. resource configuration */ 735 #define AMDGPU_INFO_GDS_CONFIG 0x13 736 /* Query information about VRAM and GTT domains */ 737 #define AMDGPU_INFO_VRAM_GTT 0x14 738 /* Query information about register in MMR address space*/ 739 #define AMDGPU_INFO_READ_MMR_REG 0x15 740 /* Query information about device: rev id, family, etc. */ 741 #define AMDGPU_INFO_DEV_INFO 0x16 742 /* visible vram usage */ 743 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 744 /* number of TTM buffer evictions */ 745 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 746 /* Query memory about VRAM and GTT domains */ 747 #define AMDGPU_INFO_MEMORY 0x19 748 /* Query vce clock table */ 749 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 750 /* Query vbios related information */ 751 #define AMDGPU_INFO_VBIOS 0x1B 752 /* Subquery id: Query vbios size */ 753 #define AMDGPU_INFO_VBIOS_SIZE 0x1 754 /* Subquery id: Query vbios image */ 755 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 756 /* Query UVD handles */ 757 #define AMDGPU_INFO_NUM_HANDLES 0x1C 758 /* Query sensor related information */ 759 #define AMDGPU_INFO_SENSOR 0x1D 760 /* Subquery id: Query GPU shader clock */ 761 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 762 /* Subquery id: Query GPU memory clock */ 763 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 764 /* Subquery id: Query GPU temperature */ 765 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 766 /* Subquery id: Query GPU load */ 767 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 768 /* Subquery id: Query average GPU power */ 769 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 770 /* Subquery id: Query northbridge voltage */ 771 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 772 /* Subquery id: Query graphics voltage */ 773 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 774 /* Subquery id: Query GPU stable pstate shader clock */ 775 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 776 /* Subquery id: Query GPU stable pstate memory clock */ 777 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 778 /* Number of VRAM page faults on CPU access. */ 779 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 780 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 781 /* query ras mask of enabled features*/ 782 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 783 /* query video encode/decode caps */ 784 #define AMDGPU_INFO_VIDEO_CAPS 0x21 785 /* Subquery id: Decode */ 786 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 787 /* Subquery id: Encode */ 788 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 789 790 /* RAS MASK: UMC (VRAM) */ 791 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 792 /* RAS MASK: SDMA */ 793 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 794 /* RAS MASK: GFX */ 795 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 796 /* RAS MASK: MMHUB */ 797 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 798 /* RAS MASK: ATHUB */ 799 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 800 /* RAS MASK: PCIE */ 801 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 802 /* RAS MASK: HDP */ 803 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 804 /* RAS MASK: XGMI */ 805 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 806 /* RAS MASK: DF */ 807 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 808 /* RAS MASK: SMN */ 809 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 810 /* RAS MASK: SEM */ 811 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 812 /* RAS MASK: MP0 */ 813 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 814 /* RAS MASK: MP1 */ 815 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 816 /* RAS MASK: FUSE */ 817 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 818 819 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 820 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 821 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 822 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 823 824 struct drm_amdgpu_query_fw { 825 /** AMDGPU_INFO_FW_* */ 826 __u32 fw_type; 827 /** 828 * Index of the IP if there are more IPs of 829 * the same type. 830 */ 831 __u32 ip_instance; 832 /** 833 * Index of the engine. Whether this is used depends 834 * on the firmware type. (e.g. MEC, SDMA) 835 */ 836 __u32 index; 837 __u32 _pad; 838 }; 839 840 /* Input structure for the INFO ioctl */ 841 struct drm_amdgpu_info { 842 /* Where the return value will be stored */ 843 __u64 return_pointer; 844 /* The size of the return value. Just like "size" in "snprintf", 845 * it limits how many bytes the kernel can write. */ 846 __u32 return_size; 847 /* The query request id. */ 848 __u32 query; 849 850 union { 851 struct { 852 __u32 id; 853 __u32 _pad; 854 } mode_crtc; 855 856 struct { 857 /** AMDGPU_HW_IP_* */ 858 __u32 type; 859 /** 860 * Index of the IP if there are more IPs of the same 861 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 862 */ 863 __u32 ip_instance; 864 } query_hw_ip; 865 866 struct { 867 __u32 dword_offset; 868 /** number of registers to read */ 869 __u32 count; 870 __u32 instance; 871 /** For future use, no flags defined so far */ 872 __u32 flags; 873 } read_mmr_reg; 874 875 struct drm_amdgpu_query_fw query_fw; 876 877 struct { 878 __u32 type; 879 __u32 offset; 880 } vbios_info; 881 882 struct { 883 __u32 type; 884 } sensor_info; 885 886 struct { 887 __u32 type; 888 } video_cap; 889 }; 890 }; 891 892 struct drm_amdgpu_info_gds { 893 /** GDS GFX partition size */ 894 __u32 gds_gfx_partition_size; 895 /** GDS compute partition size */ 896 __u32 compute_partition_size; 897 /** total GDS memory size */ 898 __u32 gds_total_size; 899 /** GWS size per GFX partition */ 900 __u32 gws_per_gfx_partition; 901 /** GSW size per compute partition */ 902 __u32 gws_per_compute_partition; 903 /** OA size per GFX partition */ 904 __u32 oa_per_gfx_partition; 905 /** OA size per compute partition */ 906 __u32 oa_per_compute_partition; 907 __u32 _pad; 908 }; 909 910 struct drm_amdgpu_info_vram_gtt { 911 __u64 vram_size; 912 __u64 vram_cpu_accessible_size; 913 __u64 gtt_size; 914 }; 915 916 struct drm_amdgpu_heap_info { 917 /** max. physical memory */ 918 __u64 total_heap_size; 919 920 /** Theoretical max. available memory in the given heap */ 921 __u64 usable_heap_size; 922 923 /** 924 * Number of bytes allocated in the heap. This includes all processes 925 * and private allocations in the kernel. It changes when new buffers 926 * are allocated, freed, and moved. It cannot be larger than 927 * heap_size. 928 */ 929 __u64 heap_usage; 930 931 /** 932 * Theoretical possible max. size of buffer which 933 * could be allocated in the given heap 934 */ 935 __u64 max_allocation; 936 }; 937 938 struct drm_amdgpu_memory_info { 939 struct drm_amdgpu_heap_info vram; 940 struct drm_amdgpu_heap_info cpu_accessible_vram; 941 struct drm_amdgpu_heap_info gtt; 942 }; 943 944 struct drm_amdgpu_info_firmware { 945 __u32 ver; 946 __u32 feature; 947 }; 948 949 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 950 #define AMDGPU_VRAM_TYPE_GDDR1 1 951 #define AMDGPU_VRAM_TYPE_DDR2 2 952 #define AMDGPU_VRAM_TYPE_GDDR3 3 953 #define AMDGPU_VRAM_TYPE_GDDR4 4 954 #define AMDGPU_VRAM_TYPE_GDDR5 5 955 #define AMDGPU_VRAM_TYPE_HBM 6 956 #define AMDGPU_VRAM_TYPE_DDR3 7 957 #define AMDGPU_VRAM_TYPE_DDR4 8 958 #define AMDGPU_VRAM_TYPE_GDDR6 9 959 #define AMDGPU_VRAM_TYPE_DDR5 10 960 961 struct drm_amdgpu_info_device { 962 /** PCI Device ID */ 963 __u32 device_id; 964 /** Internal chip revision: A0, A1, etc.) */ 965 __u32 chip_rev; 966 __u32 external_rev; 967 /** Revision id in PCI Config space */ 968 __u32 pci_rev; 969 __u32 family; 970 __u32 num_shader_engines; 971 __u32 num_shader_arrays_per_engine; 972 /* in KHz */ 973 __u32 gpu_counter_freq; 974 __u64 max_engine_clock; 975 __u64 max_memory_clock; 976 /* cu information */ 977 __u32 cu_active_number; 978 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 979 __u32 cu_ao_mask; 980 __u32 cu_bitmap[4][4]; 981 /** Render backend pipe mask. One render backend is CB+DB. */ 982 __u32 enabled_rb_pipes_mask; 983 __u32 num_rb_pipes; 984 __u32 num_hw_gfx_contexts; 985 __u32 _pad; 986 __u64 ids_flags; 987 /** Starting virtual address for UMDs. */ 988 __u64 virtual_address_offset; 989 /** The maximum virtual address */ 990 __u64 virtual_address_max; 991 /** Required alignment of virtual addresses. */ 992 __u32 virtual_address_alignment; 993 /** Page table entry - fragment size */ 994 __u32 pte_fragment_size; 995 __u32 gart_page_size; 996 /** constant engine ram size*/ 997 __u32 ce_ram_size; 998 /** video memory type info*/ 999 __u32 vram_type; 1000 /** video memory bit width*/ 1001 __u32 vram_bit_width; 1002 /* vce harvesting instance */ 1003 __u32 vce_harvest_config; 1004 /* gfx double offchip LDS buffers */ 1005 __u32 gc_double_offchip_lds_buf; 1006 /* NGG Primitive Buffer */ 1007 __u64 prim_buf_gpu_addr; 1008 /* NGG Position Buffer */ 1009 __u64 pos_buf_gpu_addr; 1010 /* NGG Control Sideband */ 1011 __u64 cntl_sb_buf_gpu_addr; 1012 /* NGG Parameter Cache */ 1013 __u64 param_buf_gpu_addr; 1014 __u32 prim_buf_size; 1015 __u32 pos_buf_size; 1016 __u32 cntl_sb_buf_size; 1017 __u32 param_buf_size; 1018 /* wavefront size*/ 1019 __u32 wave_front_size; 1020 /* shader visible vgprs*/ 1021 __u32 num_shader_visible_vgprs; 1022 /* CU per shader array*/ 1023 __u32 num_cu_per_sh; 1024 /* number of tcc blocks*/ 1025 __u32 num_tcc_blocks; 1026 /* gs vgt table depth*/ 1027 __u32 gs_vgt_table_depth; 1028 /* gs primitive buffer depth*/ 1029 __u32 gs_prim_buffer_depth; 1030 /* max gs wavefront per vgt*/ 1031 __u32 max_gs_waves_per_vgt; 1032 __u32 _pad1; 1033 /* always on cu bitmap */ 1034 __u32 cu_ao_bitmap[4][4]; 1035 /** Starting high virtual address for UMDs. */ 1036 __u64 high_va_offset; 1037 /** The maximum high virtual address */ 1038 __u64 high_va_max; 1039 /* gfx10 pa_sc_tile_steering_override */ 1040 __u32 pa_sc_tile_steering_override; 1041 /* disabled TCCs */ 1042 __u64 tcc_disabled_mask; 1043 }; 1044 1045 struct drm_amdgpu_info_hw_ip { 1046 /** Version of h/w IP */ 1047 __u32 hw_ip_version_major; 1048 __u32 hw_ip_version_minor; 1049 /** Capabilities */ 1050 __u64 capabilities_flags; 1051 /** command buffer address start alignment*/ 1052 __u32 ib_start_alignment; 1053 /** command buffer size alignment*/ 1054 __u32 ib_size_alignment; 1055 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1056 __u32 available_rings; 1057 __u32 _pad; 1058 }; 1059 1060 struct drm_amdgpu_info_num_handles { 1061 /** Max handles as supported by firmware for UVD */ 1062 __u32 uvd_max_handles; 1063 /** Handles currently in use for UVD */ 1064 __u32 uvd_used_handles; 1065 }; 1066 1067 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1068 1069 struct drm_amdgpu_info_vce_clock_table_entry { 1070 /** System clock */ 1071 __u32 sclk; 1072 /** Memory clock */ 1073 __u32 mclk; 1074 /** VCE clock */ 1075 __u32 eclk; 1076 __u32 pad; 1077 }; 1078 1079 struct drm_amdgpu_info_vce_clock_table { 1080 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1081 __u32 num_valid_entries; 1082 __u32 pad; 1083 }; 1084 1085 /* query video encode/decode caps */ 1086 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1087 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1088 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1089 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1090 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1091 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1092 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1093 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1094 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1095 1096 struct drm_amdgpu_info_video_codec_info { 1097 __u32 valid; 1098 __u32 max_width; 1099 __u32 max_height; 1100 __u32 max_pixels_per_frame; 1101 __u32 max_level; 1102 __u32 pad; 1103 }; 1104 1105 struct drm_amdgpu_info_video_caps { 1106 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1107 }; 1108 1109 /* 1110 * Supported GPU families 1111 */ 1112 #define AMDGPU_FAMILY_UNKNOWN 0 1113 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1114 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1115 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1116 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1117 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1118 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1119 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1120 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1121 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1122 1123 #if defined(__cplusplus) 1124 } 1125 #endif 1126 1127 #endif 1128