1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 #define DRM_AMDGPU_USERQ 0x16 58 #define DRM_AMDGPU_USERQ_SIGNAL 0x17 59 #define DRM_AMDGPU_USERQ_WAIT 0x18 60 #define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 61 62 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 63 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 64 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 65 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 66 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 67 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 68 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 69 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 70 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 71 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 72 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 73 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 74 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 75 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 76 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 77 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 78 #define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) 79 #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) 80 #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) 81 #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles) 82 83 /** 84 * DOC: memory domains 85 * 86 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 87 * Memory in this pool could be swapped out to disk if there is pressure. 88 * 89 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 90 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 91 * pages of system memory, allows GPU access system memory in a linearized 92 * fashion. 93 * 94 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 95 * carved out by the BIOS. 96 * 97 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 98 * across shader threads. 99 * 100 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 101 * execution of all the waves on a device. 102 * 103 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 104 * for appending data. 105 * 106 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 107 * signalling user mode queues. 108 * 109 * %AMDGPU_GEM_DOMAIN_MMIO_REMAP MMIO remap page (special mapping for HDP flushing). 110 */ 111 #define AMDGPU_GEM_DOMAIN_CPU 0x1 112 #define AMDGPU_GEM_DOMAIN_GTT 0x2 113 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 114 #define AMDGPU_GEM_DOMAIN_GDS 0x8 115 #define AMDGPU_GEM_DOMAIN_GWS 0x10 116 #define AMDGPU_GEM_DOMAIN_OA 0x20 117 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 118 #define AMDGPU_GEM_DOMAIN_MMIO_REMAP 0x80 119 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 120 AMDGPU_GEM_DOMAIN_GTT | \ 121 AMDGPU_GEM_DOMAIN_VRAM | \ 122 AMDGPU_GEM_DOMAIN_GDS | \ 123 AMDGPU_GEM_DOMAIN_GWS | \ 124 AMDGPU_GEM_DOMAIN_OA | \ 125 AMDGPU_GEM_DOMAIN_DOORBELL | \ 126 AMDGPU_GEM_DOMAIN_MMIO_REMAP) 127 128 /* Flag that CPU access will be required for the case of VRAM domain */ 129 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 130 /* Flag that CPU access will not work, this VRAM domain is invisible */ 131 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 132 /* Flag that USWC attributes should be used for GTT */ 133 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 134 /* Flag that the memory should be in VRAM and cleared */ 135 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 136 /* Flag that allocating the BO should use linear VRAM */ 137 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 138 /* Flag that BO is always valid in this VM */ 139 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 140 /* Flag that BO sharing will be explicitly synchronized */ 141 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 142 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 143 * for the second page onward should be set to NC. It should never 144 * be used by user space applications. 145 */ 146 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 147 /* Flag that BO may contain sensitive data that must be wiped before 148 * releasing the memory 149 */ 150 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 151 /* Flag that BO will be encrypted and that the TMZ bit should be 152 * set in the PTEs when mapping this buffer via GPUVM or 153 * accessing it with various hw blocks 154 */ 155 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 156 /* Flag that BO will be used only in preemptible context, which does 157 * not require GTT memory accounting 158 */ 159 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 160 /* Flag that BO can be discarded under memory pressure without keeping the 161 * content. 162 */ 163 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 164 /* Flag that BO is shared coherently between multiple devices or CPU threads. 165 * May depend on GPU instructions to flush caches to system scope explicitly. 166 * 167 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 168 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 169 */ 170 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 171 /* Flag that BO should not be cached by GPU. Coherent without having to flush 172 * GPU caches explicitly 173 * 174 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 175 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 176 */ 177 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 178 /* Flag that BO should be coherent across devices when using device-level 179 * atomics. May depend on GPU instructions to flush caches to device scope 180 * explicitly, promoting them to system scope automatically. 181 * 182 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 183 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 184 */ 185 #define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 186 /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */ 187 #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) 188 189 struct drm_amdgpu_gem_create_in { 190 /** the requested memory size */ 191 __u64 bo_size; 192 /** physical start_addr alignment in bytes for some HW requirements */ 193 __u64 alignment; 194 /** the requested memory domains */ 195 __u64 domains; 196 /** allocation flags */ 197 __u64 domain_flags; 198 }; 199 200 struct drm_amdgpu_gem_create_out { 201 /** returned GEM object handle */ 202 __u32 handle; 203 __u32 _pad; 204 }; 205 206 union drm_amdgpu_gem_create { 207 struct drm_amdgpu_gem_create_in in; 208 struct drm_amdgpu_gem_create_out out; 209 }; 210 211 /** Opcode to create new residency list. */ 212 #define AMDGPU_BO_LIST_OP_CREATE 0 213 /** Opcode to destroy previously created residency list */ 214 #define AMDGPU_BO_LIST_OP_DESTROY 1 215 /** Opcode to update resource information in the list */ 216 #define AMDGPU_BO_LIST_OP_UPDATE 2 217 218 struct drm_amdgpu_bo_list_in { 219 /** Type of operation */ 220 __u32 operation; 221 /** Handle of list or 0 if we want to create one */ 222 __u32 list_handle; 223 /** Number of BOs in list */ 224 __u32 bo_number; 225 /** Size of each element describing BO */ 226 __u32 bo_info_size; 227 /** Pointer to array describing BOs */ 228 __u64 bo_info_ptr; 229 }; 230 231 struct drm_amdgpu_bo_list_entry { 232 /** Handle of BO */ 233 __u32 bo_handle; 234 /** New (if specified) BO priority to be used during migration */ 235 __u32 bo_priority; 236 }; 237 238 struct drm_amdgpu_bo_list_out { 239 /** Handle of resource list */ 240 __u32 list_handle; 241 __u32 _pad; 242 }; 243 244 union drm_amdgpu_bo_list { 245 struct drm_amdgpu_bo_list_in in; 246 struct drm_amdgpu_bo_list_out out; 247 }; 248 249 /* context related */ 250 #define AMDGPU_CTX_OP_ALLOC_CTX 1 251 #define AMDGPU_CTX_OP_FREE_CTX 2 252 #define AMDGPU_CTX_OP_QUERY_STATE 3 253 #define AMDGPU_CTX_OP_QUERY_STATE2 4 254 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 255 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 256 257 /* GPU reset status */ 258 #define AMDGPU_CTX_NO_RESET 0 259 /* this the context caused it */ 260 #define AMDGPU_CTX_GUILTY_RESET 1 261 /* some other context caused it */ 262 #define AMDGPU_CTX_INNOCENT_RESET 2 263 /* unknown cause */ 264 #define AMDGPU_CTX_UNKNOWN_RESET 3 265 266 /* indicate gpu reset occurred after ctx created */ 267 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 268 /* indicate vram lost occurred after ctx created */ 269 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 270 /* indicate some job from this context once cause gpu hang */ 271 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 272 /* indicate some errors are detected by RAS */ 273 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 274 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 275 /* indicate that the reset hasn't completed yet */ 276 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 277 278 /* Context priority level */ 279 #define AMDGPU_CTX_PRIORITY_UNSET -2048 280 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 281 #define AMDGPU_CTX_PRIORITY_LOW -512 282 #define AMDGPU_CTX_PRIORITY_NORMAL 0 283 /* 284 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 285 * CAP_SYS_NICE or DRM_MASTER 286 */ 287 #define AMDGPU_CTX_PRIORITY_HIGH 512 288 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 289 290 /* select a stable profiling pstate for perfmon tools */ 291 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 292 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 293 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 294 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 295 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 296 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 297 298 struct drm_amdgpu_ctx_in { 299 /** AMDGPU_CTX_OP_* */ 300 __u32 op; 301 /** Flags */ 302 __u32 flags; 303 __u32 ctx_id; 304 /** AMDGPU_CTX_PRIORITY_* */ 305 __s32 priority; 306 }; 307 308 union drm_amdgpu_ctx_out { 309 struct { 310 __u32 ctx_id; 311 __u32 _pad; 312 } alloc; 313 314 struct { 315 /** For future use, no flags defined so far */ 316 __u64 flags; 317 /** Number of resets caused by this context so far. */ 318 __u32 hangs; 319 /** Reset status since the last call of the ioctl. */ 320 __u32 reset_status; 321 } state; 322 323 struct { 324 __u32 flags; 325 __u32 _pad; 326 } pstate; 327 }; 328 329 union drm_amdgpu_ctx { 330 struct drm_amdgpu_ctx_in in; 331 union drm_amdgpu_ctx_out out; 332 }; 333 334 /* user queue IOCTL operations */ 335 #define AMDGPU_USERQ_OP_CREATE 1 336 #define AMDGPU_USERQ_OP_FREE 2 337 338 /* queue priority levels */ 339 /* low < normal low < normal high < high */ 340 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3 341 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0 342 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0 343 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1 344 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2 345 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */ 346 /* for queues that need access to protected content */ 347 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2) 348 349 /* 350 * This structure is a container to pass input configuration 351 * info for all supported userqueue related operations. 352 * For operation AMDGPU_USERQ_OP_CREATE: user is expected 353 * to set all fields, excep the parameter 'queue_id'. 354 * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected 355 * to be set is 'queue_id', eveything else is ignored. 356 */ 357 struct drm_amdgpu_userq_in { 358 /** AMDGPU_USERQ_OP_* */ 359 __u32 op; 360 /** Queue id passed for operation USERQ_OP_FREE */ 361 __u32 queue_id; 362 /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */ 363 __u32 ip_type; 364 /** 365 * @doorbell_handle: the handle of doorbell GEM object 366 * associated with this userqueue client. 367 */ 368 __u32 doorbell_handle; 369 /** 370 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo. 371 * Kernel will generate absolute doorbell offset using doorbell_handle 372 * and doorbell_offset in the doorbell bo. 373 */ 374 __u32 doorbell_offset; 375 /** 376 * @flags: flags used for queue parameters 377 */ 378 __u32 flags; 379 /** 380 * @queue_va: Virtual address of the GPU memory which holds the queue 381 * object. The queue holds the workload packets. 382 */ 383 __u64 queue_va; 384 /** 385 * @queue_size: Size of the queue in bytes, this needs to be 256-byte 386 * aligned. 387 */ 388 __u64 queue_size; 389 /** 390 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR. 391 * This object must be at least 8 byte in size and aligned to 8-byte offset. 392 */ 393 __u64 rptr_va; 394 /** 395 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR. 396 * This object must be at least 8 byte in size and aligned to 8-byte offset. 397 * 398 * Queue, RPTR and WPTR can come from the same object, as long as the size 399 * and alignment related requirements are met. 400 */ 401 __u64 wptr_va; 402 /** 403 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow 404 * the GPU to uniquely define and identify a usermode queue. 405 * 406 * MQD data can be of different size for different GPU IP/engine and 407 * their respective versions/revisions, so this points to a __u64 * 408 * which holds IP specific MQD of this usermode queue. 409 */ 410 __u64 mqd; 411 /** 412 * @size: size of MQD data in bytes, it must match the MQD structure 413 * size of the respective engine/revision defined in UAPI for ex, for 414 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11). 415 */ 416 __u64 mqd_size; 417 }; 418 419 /* The structure to carry output of userqueue ops */ 420 struct drm_amdgpu_userq_out { 421 /** 422 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique 423 * queue ID to represent the newly created userqueue in the system, otherwise 424 * it should be ignored. 425 */ 426 __u32 queue_id; 427 __u32 _pad; 428 }; 429 430 union drm_amdgpu_userq { 431 struct drm_amdgpu_userq_in in; 432 struct drm_amdgpu_userq_out out; 433 }; 434 435 /* GFX V11 IP specific MQD parameters */ 436 struct drm_amdgpu_userq_mqd_gfx11 { 437 /** 438 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer. 439 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 440 */ 441 __u64 shadow_va; 442 /** 443 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 444 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 445 */ 446 __u64 csa_va; 447 }; 448 449 /* GFX V11 SDMA IP specific MQD parameters */ 450 struct drm_amdgpu_userq_mqd_sdma_gfx11 { 451 /** 452 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 453 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 454 * to get the size. 455 */ 456 __u64 csa_va; 457 }; 458 459 /* GFX V11 Compute IP specific MQD parameters */ 460 struct drm_amdgpu_userq_mqd_compute_gfx11 { 461 /** 462 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer. 463 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 464 * to get the size. 465 */ 466 __u64 eop_va; 467 }; 468 469 /* userq signal/wait ioctl */ 470 struct drm_amdgpu_userq_signal { 471 /** 472 * @queue_id: Queue handle used by the userq fence creation function 473 * to retrieve the WPTR. 474 */ 475 __u32 queue_id; 476 __u32 pad; 477 /** 478 * @syncobj_handles: The list of syncobj handles submitted by the user queue 479 * job to be signaled. 480 */ 481 __u64 syncobj_handles; 482 /** 483 * @num_syncobj_handles: A count that represents the number of syncobj handles in 484 * @syncobj_handles. 485 */ 486 __u64 num_syncobj_handles; 487 /** 488 * @bo_read_handles: The list of BO handles that the submitted user queue job 489 * is using for read only. This will update BO fences in the kernel. 490 */ 491 __u64 bo_read_handles; 492 /** 493 * @bo_write_handles: The list of BO handles that the submitted user queue job 494 * is using for write only. This will update BO fences in the kernel. 495 */ 496 __u64 bo_write_handles; 497 /** 498 * @num_bo_read_handles: A count that represents the number of read BO handles in 499 * @bo_read_handles. 500 */ 501 __u32 num_bo_read_handles; 502 /** 503 * @num_bo_write_handles: A count that represents the number of write BO handles in 504 * @bo_write_handles. 505 */ 506 __u32 num_bo_write_handles; 507 }; 508 509 struct drm_amdgpu_userq_fence_info { 510 /** 511 * @va: A gpu address allocated for each queue which stores the 512 * read pointer (RPTR) value. 513 */ 514 __u64 va; 515 /** 516 * @value: A 64 bit value represents the write pointer (WPTR) of the 517 * queue commands which compared with the RPTR value to signal the 518 * fences. 519 */ 520 __u64 value; 521 }; 522 523 struct drm_amdgpu_userq_wait { 524 /** 525 * @waitq_id: Queue handle used by the userq wait IOCTL to retrieve the 526 * wait queue and maintain the fence driver references in it. 527 */ 528 __u32 waitq_id; 529 __u32 pad; 530 /** 531 * @syncobj_handles: The list of syncobj handles submitted by the user queue 532 * job to get the va/value pairs. 533 */ 534 __u64 syncobj_handles; 535 /** 536 * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by 537 * the user queue job to get the va/value pairs at given @syncobj_timeline_points. 538 */ 539 __u64 syncobj_timeline_handles; 540 /** 541 * @syncobj_timeline_points: The list of timeline syncobj points submitted by the 542 * user queue job for the corresponding @syncobj_timeline_handles. 543 */ 544 __u64 syncobj_timeline_points; 545 /** 546 * @bo_read_handles: The list of read BO handles submitted by the user queue 547 * job to get the va/value pairs. 548 */ 549 __u64 bo_read_handles; 550 /** 551 * @bo_write_handles: The list of write BO handles submitted by the user queue 552 * job to get the va/value pairs. 553 */ 554 __u64 bo_write_handles; 555 /** 556 * @num_syncobj_timeline_handles: A count that represents the number of timeline 557 * syncobj handles in @syncobj_timeline_handles. 558 */ 559 __u16 num_syncobj_timeline_handles; 560 /** 561 * @num_fences: This field can be used both as input and output. As input it defines 562 * the maximum number of fences that can be returned and as output it will specify 563 * how many fences were actually returned from the ioctl. 564 */ 565 __u16 num_fences; 566 /** 567 * @num_syncobj_handles: A count that represents the number of syncobj handles in 568 * @syncobj_handles. 569 */ 570 __u32 num_syncobj_handles; 571 /** 572 * @num_bo_read_handles: A count that represents the number of read BO handles in 573 * @bo_read_handles. 574 */ 575 __u32 num_bo_read_handles; 576 /** 577 * @num_bo_write_handles: A count that represents the number of write BO handles in 578 * @bo_write_handles. 579 */ 580 __u32 num_bo_write_handles; 581 /** 582 * @out_fences: The field is a return value from the ioctl containing the list of 583 * address/value pairs to wait for. 584 */ 585 __u64 out_fences; 586 }; 587 588 /* vm ioctl */ 589 #define AMDGPU_VM_OP_RESERVE_VMID 1 590 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 591 592 struct drm_amdgpu_vm_in { 593 /** AMDGPU_VM_OP_* */ 594 __u32 op; 595 __u32 flags; 596 }; 597 598 struct drm_amdgpu_vm_out { 599 /** For future use, no flags defined so far */ 600 __u64 flags; 601 }; 602 603 union drm_amdgpu_vm { 604 struct drm_amdgpu_vm_in in; 605 struct drm_amdgpu_vm_out out; 606 }; 607 608 /* sched ioctl */ 609 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 610 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 611 612 struct drm_amdgpu_sched_in { 613 /* AMDGPU_SCHED_OP_* */ 614 __u32 op; 615 __u32 fd; 616 /** AMDGPU_CTX_PRIORITY_* */ 617 __s32 priority; 618 __u32 ctx_id; 619 }; 620 621 union drm_amdgpu_sched { 622 struct drm_amdgpu_sched_in in; 623 }; 624 625 /* 626 * This is not a reliable API and you should expect it to fail for any 627 * number of reasons and have fallback path that do not use userptr to 628 * perform any operation. 629 */ 630 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 631 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 632 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 633 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 634 635 struct drm_amdgpu_gem_userptr { 636 __u64 addr; 637 __u64 size; 638 /* AMDGPU_GEM_USERPTR_* */ 639 __u32 flags; 640 /* Resulting GEM handle */ 641 __u32 handle; 642 }; 643 644 /* SI-CI-VI: */ 645 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 646 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 647 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 648 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 649 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 650 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 651 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 652 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 653 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 654 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 655 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 656 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 657 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 658 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 659 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 660 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 661 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 662 663 /* GFX9 - GFX11: */ 664 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 665 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 666 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 667 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 668 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 669 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 670 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 671 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 672 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 673 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 674 #define AMDGPU_TILING_SCANOUT_SHIFT 63 675 #define AMDGPU_TILING_SCANOUT_MASK 0x1 676 677 /* GFX12 and later: */ 678 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 679 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 680 /* These are DCC recompression settings for memory management: */ 681 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 682 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ 683 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 684 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ 685 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 686 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 687 /* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata 688 * to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */ 689 #define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14 690 #define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1 691 /* bit gap */ 692 #define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63 693 #define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1 694 695 /* Set/Get helpers for tiling flags. */ 696 #define AMDGPU_TILING_SET(field, value) \ 697 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 698 #define AMDGPU_TILING_GET(value, field) \ 699 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 700 701 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 702 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 703 704 /** The same structure is shared for input/output */ 705 struct drm_amdgpu_gem_metadata { 706 /** GEM Object handle */ 707 __u32 handle; 708 /** Do we want get or set metadata */ 709 __u32 op; 710 struct { 711 /** For future use, no flags defined so far */ 712 __u64 flags; 713 /** family specific tiling info */ 714 __u64 tiling_info; 715 __u32 data_size_bytes; 716 __u32 data[64]; 717 } data; 718 }; 719 720 struct drm_amdgpu_gem_mmap_in { 721 /** the GEM object handle */ 722 __u32 handle; 723 __u32 _pad; 724 }; 725 726 struct drm_amdgpu_gem_mmap_out { 727 /** mmap offset from the vma offset manager */ 728 __u64 addr_ptr; 729 }; 730 731 union drm_amdgpu_gem_mmap { 732 struct drm_amdgpu_gem_mmap_in in; 733 struct drm_amdgpu_gem_mmap_out out; 734 }; 735 736 struct drm_amdgpu_gem_wait_idle_in { 737 /** GEM object handle */ 738 __u32 handle; 739 /** For future use, no flags defined so far */ 740 __u32 flags; 741 /** Absolute timeout to wait */ 742 __u64 timeout; 743 }; 744 745 struct drm_amdgpu_gem_wait_idle_out { 746 /** BO status: 0 - BO is idle, 1 - BO is busy */ 747 __u32 status; 748 /** Returned current memory domain */ 749 __u32 domain; 750 }; 751 752 union drm_amdgpu_gem_wait_idle { 753 struct drm_amdgpu_gem_wait_idle_in in; 754 struct drm_amdgpu_gem_wait_idle_out out; 755 }; 756 757 struct drm_amdgpu_wait_cs_in { 758 /* Command submission handle 759 * handle equals 0 means none to wait for 760 * handle equals ~0ull means wait for the latest sequence number 761 */ 762 __u64 handle; 763 /** Absolute timeout to wait */ 764 __u64 timeout; 765 __u32 ip_type; 766 __u32 ip_instance; 767 __u32 ring; 768 __u32 ctx_id; 769 }; 770 771 struct drm_amdgpu_wait_cs_out { 772 /** CS status: 0 - CS completed, 1 - CS still busy */ 773 __u64 status; 774 }; 775 776 union drm_amdgpu_wait_cs { 777 struct drm_amdgpu_wait_cs_in in; 778 struct drm_amdgpu_wait_cs_out out; 779 }; 780 781 struct drm_amdgpu_fence { 782 __u32 ctx_id; 783 __u32 ip_type; 784 __u32 ip_instance; 785 __u32 ring; 786 __u64 seq_no; 787 }; 788 789 struct drm_amdgpu_wait_fences_in { 790 /** This points to uint64_t * which points to fences */ 791 __u64 fences; 792 __u32 fence_count; 793 __u32 wait_all; 794 __u64 timeout_ns; 795 }; 796 797 struct drm_amdgpu_wait_fences_out { 798 __u32 status; 799 __u32 first_signaled; 800 }; 801 802 union drm_amdgpu_wait_fences { 803 struct drm_amdgpu_wait_fences_in in; 804 struct drm_amdgpu_wait_fences_out out; 805 }; 806 807 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 808 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 809 #define AMDGPU_GEM_OP_GET_MAPPING_INFO 2 810 811 struct drm_amdgpu_gem_vm_entry { 812 /* Start of mapping (in bytes) */ 813 __u64 addr; 814 815 /* Size of mapping (in bytes) */ 816 __u64 size; 817 818 /* Mapping offset */ 819 __u64 offset; 820 821 /* flags needed to recreate mapping */ 822 __u64 flags; 823 }; 824 825 /* Sets or returns a value associated with a buffer. */ 826 struct drm_amdgpu_gem_op { 827 /** GEM object handle */ 828 __u32 handle; 829 /** AMDGPU_GEM_OP_* */ 830 __u32 op; 831 /** Input or return value. For MAPPING_INFO op: pointer to array of struct drm_amdgpu_gem_vm_entry */ 832 __u64 value; 833 /** For MAPPING_INFO op: number of mappings (in/out) */ 834 __u32 num_entries; 835 836 __u32 padding; 837 }; 838 839 #define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT (1 << 0) 840 841 struct drm_amdgpu_gem_list_handles { 842 /* User pointer to array of drm_amdgpu_gem_bo_info_entry */ 843 __u64 entries; 844 845 /* Size of entries buffer / Number of handles in process (if larger than size of buffer, must retry) */ 846 __u32 num_entries; 847 848 __u32 padding; 849 }; 850 851 struct drm_amdgpu_gem_list_handles_entry { 852 /* gem handle of buffer object */ 853 __u32 gem_handle; 854 855 /* Currently just one flag: IS_IMPORT */ 856 __u32 flags; 857 858 /* Size of bo */ 859 __u64 size; 860 861 /* Preferred domains for GEM_CREATE */ 862 __u64 preferred_domains; 863 864 /* GEM_CREATE flags for re-creation of buffer */ 865 __u64 alloc_flags; 866 867 /* physical start_addr alignment in bytes for some HW requirements */ 868 __u64 alignment; 869 }; 870 871 #define AMDGPU_VA_OP_MAP 1 872 #define AMDGPU_VA_OP_UNMAP 2 873 #define AMDGPU_VA_OP_CLEAR 3 874 #define AMDGPU_VA_OP_REPLACE 4 875 876 /* Delay the page table update till the next CS */ 877 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 878 879 /* Mapping flags */ 880 /* readable mapping */ 881 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 882 /* writable mapping */ 883 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 884 /* executable mapping, new for VI */ 885 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 886 /* partially resident texture */ 887 #define AMDGPU_VM_PAGE_PRT (1 << 4) 888 /* MTYPE flags use bit 5 to 8 */ 889 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 890 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 891 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 892 /* Use Non Coherent MTYPE instead of default MTYPE */ 893 #define AMDGPU_VM_MTYPE_NC (1 << 5) 894 /* Use Write Combine MTYPE instead of default MTYPE */ 895 #define AMDGPU_VM_MTYPE_WC (2 << 5) 896 /* Use Cache Coherent MTYPE instead of default MTYPE */ 897 #define AMDGPU_VM_MTYPE_CC (3 << 5) 898 /* Use UnCached MTYPE instead of default MTYPE */ 899 #define AMDGPU_VM_MTYPE_UC (4 << 5) 900 /* Use Read Write MTYPE instead of default MTYPE */ 901 #define AMDGPU_VM_MTYPE_RW (5 << 5) 902 /* don't allocate MALL */ 903 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 904 905 struct drm_amdgpu_gem_va { 906 /** GEM object handle */ 907 __u32 handle; 908 __u32 _pad; 909 /** AMDGPU_VA_OP_* */ 910 __u32 operation; 911 /** AMDGPU_VM_PAGE_* */ 912 __u32 flags; 913 /** va address to assign . Must be correctly aligned.*/ 914 __u64 va_address; 915 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 916 __u64 offset_in_bo; 917 /** Specify mapping size. Must be correctly aligned. */ 918 __u64 map_size; 919 /** 920 * vm_timeline_point is a sequence number used to add new timeline point. 921 */ 922 __u64 vm_timeline_point; 923 /** 924 * The vm page table update fence is installed in given vm_timeline_syncobj_out 925 * at vm_timeline_point. 926 */ 927 __u32 vm_timeline_syncobj_out; 928 /** the number of syncobj handles in @input_fence_syncobj_handles */ 929 __u32 num_syncobj_handles; 930 /** Array of sync object handle to wait for given input fences */ 931 __u64 input_fence_syncobj_handles; 932 }; 933 934 #define AMDGPU_HW_IP_GFX 0 935 #define AMDGPU_HW_IP_COMPUTE 1 936 #define AMDGPU_HW_IP_DMA 2 937 #define AMDGPU_HW_IP_UVD 3 938 #define AMDGPU_HW_IP_VCE 4 939 #define AMDGPU_HW_IP_UVD_ENC 5 940 #define AMDGPU_HW_IP_VCN_DEC 6 941 /* 942 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 943 * both encoding and decoding jobs. 944 */ 945 #define AMDGPU_HW_IP_VCN_ENC 7 946 #define AMDGPU_HW_IP_VCN_JPEG 8 947 #define AMDGPU_HW_IP_VPE 9 948 #define AMDGPU_HW_IP_NUM 10 949 950 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 951 952 #define AMDGPU_CHUNK_ID_IB 0x01 953 #define AMDGPU_CHUNK_ID_FENCE 0x02 954 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 955 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 956 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 957 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 958 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 959 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 960 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 961 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 962 963 struct drm_amdgpu_cs_chunk { 964 __u32 chunk_id; 965 __u32 length_dw; 966 __u64 chunk_data; 967 }; 968 969 struct drm_amdgpu_cs_in { 970 /** Rendering context id */ 971 __u32 ctx_id; 972 /** Handle of resource list associated with CS */ 973 __u32 bo_list_handle; 974 __u32 num_chunks; 975 __u32 flags; 976 /** this points to __u64 * which point to cs chunks */ 977 __u64 chunks; 978 }; 979 980 struct drm_amdgpu_cs_out { 981 __u64 handle; 982 }; 983 984 union drm_amdgpu_cs { 985 struct drm_amdgpu_cs_in in; 986 struct drm_amdgpu_cs_out out; 987 }; 988 989 /* Specify flags to be used for IB */ 990 991 /* This IB should be submitted to CE */ 992 #define AMDGPU_IB_FLAG_CE (1<<0) 993 994 /* Preamble flag, which means the IB could be dropped if no context switch */ 995 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 996 997 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 998 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 999 1000 /* The IB fence should do the L2 writeback but not invalidate any shader 1001 * caches (L2/vL1/sL1/I$). */ 1002 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 1003 1004 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 1005 * This will reset wave ID counters for the IB. 1006 */ 1007 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 1008 1009 /* Flag the IB as secure (TMZ) 1010 */ 1011 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 1012 1013 /* Tell KMD to flush and invalidate caches 1014 */ 1015 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 1016 1017 struct drm_amdgpu_cs_chunk_ib { 1018 __u32 _pad; 1019 /** AMDGPU_IB_FLAG_* */ 1020 __u32 flags; 1021 /** Virtual address to begin IB execution */ 1022 __u64 va_start; 1023 /** Size of submission */ 1024 __u32 ib_bytes; 1025 /** HW IP to submit to */ 1026 __u32 ip_type; 1027 /** HW IP index of the same type to submit to */ 1028 __u32 ip_instance; 1029 /** Ring index to submit to */ 1030 __u32 ring; 1031 }; 1032 1033 struct drm_amdgpu_cs_chunk_dep { 1034 __u32 ip_type; 1035 __u32 ip_instance; 1036 __u32 ring; 1037 __u32 ctx_id; 1038 __u64 handle; 1039 }; 1040 1041 struct drm_amdgpu_cs_chunk_fence { 1042 __u32 handle; 1043 __u32 offset; 1044 }; 1045 1046 struct drm_amdgpu_cs_chunk_sem { 1047 __u32 handle; 1048 }; 1049 1050 struct drm_amdgpu_cs_chunk_syncobj { 1051 __u32 handle; 1052 __u32 flags; 1053 __u64 point; 1054 }; 1055 1056 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 1057 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 1058 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 1059 1060 union drm_amdgpu_fence_to_handle { 1061 struct { 1062 struct drm_amdgpu_fence fence; 1063 __u32 what; 1064 __u32 pad; 1065 } in; 1066 struct { 1067 __u32 handle; 1068 } out; 1069 }; 1070 1071 struct drm_amdgpu_cs_chunk_data { 1072 union { 1073 struct drm_amdgpu_cs_chunk_ib ib_data; 1074 struct drm_amdgpu_cs_chunk_fence fence_data; 1075 }; 1076 }; 1077 1078 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 1079 1080 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 1081 __u64 shadow_va; 1082 __u64 csa_va; 1083 __u64 gds_va; 1084 __u64 flags; 1085 }; 1086 1087 /* 1088 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 1089 * 1090 */ 1091 #define AMDGPU_IDS_FLAGS_FUSION 0x1 1092 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 1093 #define AMDGPU_IDS_FLAGS_TMZ 0x4 1094 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 1095 1096 /* 1097 * Query h/w info: Flag identifying VF/PF/PT mode 1098 * 1099 */ 1100 #define AMDGPU_IDS_FLAGS_MODE_MASK 0x300 1101 #define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8 1102 #define AMDGPU_IDS_FLAGS_MODE_PF 0x0 1103 #define AMDGPU_IDS_FLAGS_MODE_VF 0x1 1104 #define AMDGPU_IDS_FLAGS_MODE_PT 0x2 1105 1106 /* indicate if acceleration can be working */ 1107 #define AMDGPU_INFO_ACCEL_WORKING 0x00 1108 /* get the crtc_id from the mode object id? */ 1109 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 1110 /* query hw IP info */ 1111 #define AMDGPU_INFO_HW_IP_INFO 0x02 1112 /* query hw IP instance count for the specified type */ 1113 #define AMDGPU_INFO_HW_IP_COUNT 0x03 1114 /* timestamp for GL_ARB_timer_query */ 1115 #define AMDGPU_INFO_TIMESTAMP 0x05 1116 /* Query the firmware version */ 1117 #define AMDGPU_INFO_FW_VERSION 0x0e 1118 /* Subquery id: Query VCE firmware version */ 1119 #define AMDGPU_INFO_FW_VCE 0x1 1120 /* Subquery id: Query UVD firmware version */ 1121 #define AMDGPU_INFO_FW_UVD 0x2 1122 /* Subquery id: Query GMC firmware version */ 1123 #define AMDGPU_INFO_FW_GMC 0x03 1124 /* Subquery id: Query GFX ME firmware version */ 1125 #define AMDGPU_INFO_FW_GFX_ME 0x04 1126 /* Subquery id: Query GFX PFP firmware version */ 1127 #define AMDGPU_INFO_FW_GFX_PFP 0x05 1128 /* Subquery id: Query GFX CE firmware version */ 1129 #define AMDGPU_INFO_FW_GFX_CE 0x06 1130 /* Subquery id: Query GFX RLC firmware version */ 1131 #define AMDGPU_INFO_FW_GFX_RLC 0x07 1132 /* Subquery id: Query GFX MEC firmware version */ 1133 #define AMDGPU_INFO_FW_GFX_MEC 0x08 1134 /* Subquery id: Query SMC firmware version */ 1135 #define AMDGPU_INFO_FW_SMC 0x0a 1136 /* Subquery id: Query SDMA firmware version */ 1137 #define AMDGPU_INFO_FW_SDMA 0x0b 1138 /* Subquery id: Query PSP SOS firmware version */ 1139 #define AMDGPU_INFO_FW_SOS 0x0c 1140 /* Subquery id: Query PSP ASD firmware version */ 1141 #define AMDGPU_INFO_FW_ASD 0x0d 1142 /* Subquery id: Query VCN firmware version */ 1143 #define AMDGPU_INFO_FW_VCN 0x0e 1144 /* Subquery id: Query GFX RLC SRLC firmware version */ 1145 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 1146 /* Subquery id: Query GFX RLC SRLG firmware version */ 1147 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 1148 /* Subquery id: Query GFX RLC SRLS firmware version */ 1149 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 1150 /* Subquery id: Query DMCU firmware version */ 1151 #define AMDGPU_INFO_FW_DMCU 0x12 1152 #define AMDGPU_INFO_FW_TA 0x13 1153 /* Subquery id: Query DMCUB firmware version */ 1154 #define AMDGPU_INFO_FW_DMCUB 0x14 1155 /* Subquery id: Query TOC firmware version */ 1156 #define AMDGPU_INFO_FW_TOC 0x15 1157 /* Subquery id: Query CAP firmware version */ 1158 #define AMDGPU_INFO_FW_CAP 0x16 1159 /* Subquery id: Query GFX RLCP firmware version */ 1160 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 1161 /* Subquery id: Query GFX RLCV firmware version */ 1162 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 1163 /* Subquery id: Query MES_KIQ firmware version */ 1164 #define AMDGPU_INFO_FW_MES_KIQ 0x19 1165 /* Subquery id: Query MES firmware version */ 1166 #define AMDGPU_INFO_FW_MES 0x1a 1167 /* Subquery id: Query IMU firmware version */ 1168 #define AMDGPU_INFO_FW_IMU 0x1b 1169 /* Subquery id: Query VPE firmware version */ 1170 #define AMDGPU_INFO_FW_VPE 0x1c 1171 1172 /* number of bytes moved for TTM migration */ 1173 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 1174 /* the used VRAM size */ 1175 #define AMDGPU_INFO_VRAM_USAGE 0x10 1176 /* the used GTT size */ 1177 #define AMDGPU_INFO_GTT_USAGE 0x11 1178 /* Information about GDS, etc. resource configuration */ 1179 #define AMDGPU_INFO_GDS_CONFIG 0x13 1180 /* Query information about VRAM and GTT domains */ 1181 #define AMDGPU_INFO_VRAM_GTT 0x14 1182 /* Query information about register in MMR address space*/ 1183 #define AMDGPU_INFO_READ_MMR_REG 0x15 1184 /* Query information about device: rev id, family, etc. */ 1185 #define AMDGPU_INFO_DEV_INFO 0x16 1186 /* visible vram usage */ 1187 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 1188 /* number of TTM buffer evictions */ 1189 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 1190 /* Query memory about VRAM and GTT domains */ 1191 #define AMDGPU_INFO_MEMORY 0x19 1192 /* Query vce clock table */ 1193 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 1194 /* Query vbios related information */ 1195 #define AMDGPU_INFO_VBIOS 0x1B 1196 /* Subquery id: Query vbios size */ 1197 #define AMDGPU_INFO_VBIOS_SIZE 0x1 1198 /* Subquery id: Query vbios image */ 1199 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 1200 /* Subquery id: Query vbios info */ 1201 #define AMDGPU_INFO_VBIOS_INFO 0x3 1202 /* Query UVD handles */ 1203 #define AMDGPU_INFO_NUM_HANDLES 0x1C 1204 /* Query sensor related information */ 1205 #define AMDGPU_INFO_SENSOR 0x1D 1206 /* Subquery id: Query GPU shader clock */ 1207 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 1208 /* Subquery id: Query GPU memory clock */ 1209 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 1210 /* Subquery id: Query GPU temperature */ 1211 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 1212 /* Subquery id: Query GPU load */ 1213 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 1214 /* Subquery id: Query average GPU power */ 1215 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 1216 /* Subquery id: Query northbridge voltage */ 1217 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 1218 /* Subquery id: Query graphics voltage */ 1219 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 1220 /* Subquery id: Query GPU stable pstate shader clock */ 1221 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 1222 /* Subquery id: Query GPU stable pstate memory clock */ 1223 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 1224 /* Subquery id: Query GPU peak pstate shader clock */ 1225 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 1226 /* Subquery id: Query GPU peak pstate memory clock */ 1227 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 1228 /* Subquery id: Query input GPU power */ 1229 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 1230 /* Number of VRAM page faults on CPU access. */ 1231 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 1232 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 1233 /* query ras mask of enabled features*/ 1234 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 1235 /* RAS MASK: UMC (VRAM) */ 1236 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 1237 /* RAS MASK: SDMA */ 1238 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 1239 /* RAS MASK: GFX */ 1240 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 1241 /* RAS MASK: MMHUB */ 1242 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 1243 /* RAS MASK: ATHUB */ 1244 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 1245 /* RAS MASK: PCIE */ 1246 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 1247 /* RAS MASK: HDP */ 1248 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 1249 /* RAS MASK: XGMI */ 1250 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 1251 /* RAS MASK: DF */ 1252 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 1253 /* RAS MASK: SMN */ 1254 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 1255 /* RAS MASK: SEM */ 1256 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 1257 /* RAS MASK: MP0 */ 1258 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 1259 /* RAS MASK: MP1 */ 1260 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 1261 /* RAS MASK: FUSE */ 1262 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 1263 /* query video encode/decode caps */ 1264 #define AMDGPU_INFO_VIDEO_CAPS 0x21 1265 /* Subquery id: Decode */ 1266 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 1267 /* Subquery id: Encode */ 1268 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 1269 /* Query the max number of IBs per gang per submission */ 1270 #define AMDGPU_INFO_MAX_IBS 0x22 1271 /* query last page fault info */ 1272 #define AMDGPU_INFO_GPUVM_FAULT 0x23 1273 /* query FW object size and alignment */ 1274 #define AMDGPU_INFO_UQ_FW_AREAS 0x24 1275 1276 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 1277 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 1278 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 1279 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 1280 1281 struct drm_amdgpu_query_fw { 1282 /** AMDGPU_INFO_FW_* */ 1283 __u32 fw_type; 1284 /** 1285 * Index of the IP if there are more IPs of 1286 * the same type. 1287 */ 1288 __u32 ip_instance; 1289 /** 1290 * Index of the engine. Whether this is used depends 1291 * on the firmware type. (e.g. MEC, SDMA) 1292 */ 1293 __u32 index; 1294 __u32 _pad; 1295 }; 1296 1297 /* Input structure for the INFO ioctl */ 1298 struct drm_amdgpu_info { 1299 /* Where the return value will be stored */ 1300 __u64 return_pointer; 1301 /* The size of the return value. Just like "size" in "snprintf", 1302 * it limits how many bytes the kernel can write. */ 1303 __u32 return_size; 1304 /* The query request id. */ 1305 __u32 query; 1306 1307 union { 1308 struct { 1309 __u32 id; 1310 __u32 _pad; 1311 } mode_crtc; 1312 1313 struct { 1314 /** AMDGPU_HW_IP_* */ 1315 __u32 type; 1316 /** 1317 * Index of the IP if there are more IPs of the same 1318 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 1319 */ 1320 __u32 ip_instance; 1321 } query_hw_ip; 1322 1323 struct { 1324 __u32 dword_offset; 1325 /** number of registers to read */ 1326 __u32 count; 1327 __u32 instance; 1328 /** For future use, no flags defined so far */ 1329 __u32 flags; 1330 } read_mmr_reg; 1331 1332 struct drm_amdgpu_query_fw query_fw; 1333 1334 struct { 1335 __u32 type; 1336 __u32 offset; 1337 } vbios_info; 1338 1339 struct { 1340 __u32 type; 1341 } sensor_info; 1342 1343 struct { 1344 __u32 type; 1345 } video_cap; 1346 }; 1347 }; 1348 1349 struct drm_amdgpu_info_gds { 1350 /** GDS GFX partition size */ 1351 __u32 gds_gfx_partition_size; 1352 /** GDS compute partition size */ 1353 __u32 compute_partition_size; 1354 /** total GDS memory size */ 1355 __u32 gds_total_size; 1356 /** GWS size per GFX partition */ 1357 __u32 gws_per_gfx_partition; 1358 /** GSW size per compute partition */ 1359 __u32 gws_per_compute_partition; 1360 /** OA size per GFX partition */ 1361 __u32 oa_per_gfx_partition; 1362 /** OA size per compute partition */ 1363 __u32 oa_per_compute_partition; 1364 __u32 _pad; 1365 }; 1366 1367 struct drm_amdgpu_info_vram_gtt { 1368 __u64 vram_size; 1369 __u64 vram_cpu_accessible_size; 1370 __u64 gtt_size; 1371 }; 1372 1373 struct drm_amdgpu_heap_info { 1374 /** max. physical memory */ 1375 __u64 total_heap_size; 1376 1377 /** Theoretical max. available memory in the given heap */ 1378 __u64 usable_heap_size; 1379 1380 /** 1381 * Number of bytes allocated in the heap. This includes all processes 1382 * and private allocations in the kernel. It changes when new buffers 1383 * are allocated, freed, and moved. It cannot be larger than 1384 * heap_size. 1385 */ 1386 __u64 heap_usage; 1387 1388 /** 1389 * Theoretical possible max. size of buffer which 1390 * could be allocated in the given heap 1391 */ 1392 __u64 max_allocation; 1393 }; 1394 1395 struct drm_amdgpu_memory_info { 1396 struct drm_amdgpu_heap_info vram; 1397 struct drm_amdgpu_heap_info cpu_accessible_vram; 1398 struct drm_amdgpu_heap_info gtt; 1399 }; 1400 1401 struct drm_amdgpu_info_firmware { 1402 __u32 ver; 1403 __u32 feature; 1404 }; 1405 1406 struct drm_amdgpu_info_vbios { 1407 __u8 name[64]; 1408 __u8 vbios_pn[64]; 1409 __u32 version; 1410 __u32 pad; 1411 __u8 vbios_ver_str[32]; 1412 __u8 date[32]; 1413 }; 1414 1415 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 1416 #define AMDGPU_VRAM_TYPE_GDDR1 1 1417 #define AMDGPU_VRAM_TYPE_DDR2 2 1418 #define AMDGPU_VRAM_TYPE_GDDR3 3 1419 #define AMDGPU_VRAM_TYPE_GDDR4 4 1420 #define AMDGPU_VRAM_TYPE_GDDR5 5 1421 #define AMDGPU_VRAM_TYPE_HBM 6 1422 #define AMDGPU_VRAM_TYPE_DDR3 7 1423 #define AMDGPU_VRAM_TYPE_DDR4 8 1424 #define AMDGPU_VRAM_TYPE_GDDR6 9 1425 #define AMDGPU_VRAM_TYPE_DDR5 10 1426 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1427 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1428 #define AMDGPU_VRAM_TYPE_HBM3E 13 1429 1430 struct drm_amdgpu_info_device { 1431 /** PCI Device ID */ 1432 __u32 device_id; 1433 /** Internal chip revision: A0, A1, etc.) */ 1434 __u32 chip_rev; 1435 __u32 external_rev; 1436 /** Revision id in PCI Config space */ 1437 __u32 pci_rev; 1438 __u32 family; 1439 __u32 num_shader_engines; 1440 __u32 num_shader_arrays_per_engine; 1441 /* in KHz */ 1442 __u32 gpu_counter_freq; 1443 __u64 max_engine_clock; 1444 __u64 max_memory_clock; 1445 /* cu information */ 1446 __u32 cu_active_number; 1447 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1448 __u32 cu_ao_mask; 1449 __u32 cu_bitmap[4][4]; 1450 /** Render backend pipe mask. One render backend is CB+DB. */ 1451 __u32 enabled_rb_pipes_mask; 1452 __u32 num_rb_pipes; 1453 __u32 num_hw_gfx_contexts; 1454 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1455 __u32 pcie_gen; 1456 __u64 ids_flags; 1457 /** Starting virtual address for UMDs. */ 1458 __u64 virtual_address_offset; 1459 /** The maximum virtual address */ 1460 __u64 virtual_address_max; 1461 /** Required alignment of virtual addresses. */ 1462 __u32 virtual_address_alignment; 1463 /** Page table entry - fragment size */ 1464 __u32 pte_fragment_size; 1465 __u32 gart_page_size; 1466 /** constant engine ram size*/ 1467 __u32 ce_ram_size; 1468 /** video memory type info*/ 1469 __u32 vram_type; 1470 /** video memory bit width*/ 1471 __u32 vram_bit_width; 1472 /* vce harvesting instance */ 1473 __u32 vce_harvest_config; 1474 /* gfx double offchip LDS buffers */ 1475 __u32 gc_double_offchip_lds_buf; 1476 /* NGG Primitive Buffer */ 1477 __u64 prim_buf_gpu_addr; 1478 /* NGG Position Buffer */ 1479 __u64 pos_buf_gpu_addr; 1480 /* NGG Control Sideband */ 1481 __u64 cntl_sb_buf_gpu_addr; 1482 /* NGG Parameter Cache */ 1483 __u64 param_buf_gpu_addr; 1484 __u32 prim_buf_size; 1485 __u32 pos_buf_size; 1486 __u32 cntl_sb_buf_size; 1487 __u32 param_buf_size; 1488 /* wavefront size*/ 1489 __u32 wave_front_size; 1490 /* shader visible vgprs*/ 1491 __u32 num_shader_visible_vgprs; 1492 /* CU per shader array*/ 1493 __u32 num_cu_per_sh; 1494 /* number of tcc blocks*/ 1495 __u32 num_tcc_blocks; 1496 /* gs vgt table depth*/ 1497 __u32 gs_vgt_table_depth; 1498 /* gs primitive buffer depth*/ 1499 __u32 gs_prim_buffer_depth; 1500 /* max gs wavefront per vgt*/ 1501 __u32 max_gs_waves_per_vgt; 1502 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1503 __u32 pcie_num_lanes; 1504 /* always on cu bitmap */ 1505 __u32 cu_ao_bitmap[4][4]; 1506 /** Starting high virtual address for UMDs. */ 1507 __u64 high_va_offset; 1508 /** The maximum high virtual address */ 1509 __u64 high_va_max; 1510 /* gfx10 pa_sc_tile_steering_override */ 1511 __u32 pa_sc_tile_steering_override; 1512 /* disabled TCCs */ 1513 __u64 tcc_disabled_mask; 1514 __u64 min_engine_clock; 1515 __u64 min_memory_clock; 1516 /* The following fields are only set on gfx11+, older chips set 0. */ 1517 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1518 __u32 num_sqc_per_wgp; 1519 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1520 __u32 sqc_inst_cache_size; 1521 __u32 gl1c_cache_size; 1522 __u32 gl2c_cache_size; 1523 __u64 mall_size; /* AKA infinity cache */ 1524 /* high 32 bits of the rb pipes mask */ 1525 __u32 enabled_rb_pipes_mask_hi; 1526 /* shadow area size for gfx11 */ 1527 __u32 shadow_size; 1528 /* shadow area base virtual alignment for gfx11 */ 1529 __u32 shadow_alignment; 1530 /* context save area size for gfx11 */ 1531 __u32 csa_size; 1532 /* context save area base virtual alignment for gfx11 */ 1533 __u32 csa_alignment; 1534 /* Userq IP mask (1 << AMDGPU_HW_IP_*) */ 1535 __u32 userq_ip_mask; 1536 __u32 pad; 1537 }; 1538 1539 struct drm_amdgpu_info_hw_ip { 1540 /** Version of h/w IP */ 1541 __u32 hw_ip_version_major; 1542 __u32 hw_ip_version_minor; 1543 /** Capabilities */ 1544 __u64 capabilities_flags; 1545 /** command buffer address start alignment*/ 1546 __u32 ib_start_alignment; 1547 /** command buffer size alignment*/ 1548 __u32 ib_size_alignment; 1549 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1550 __u32 available_rings; 1551 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1552 __u32 ip_discovery_version; 1553 /* Userq available slots */ 1554 __u32 userq_num_slots; 1555 }; 1556 1557 /* GFX metadata BO sizes and alignment info (in bytes) */ 1558 struct drm_amdgpu_info_uq_fw_areas_gfx { 1559 /* shadow area size */ 1560 __u32 shadow_size; 1561 /* shadow area base virtual mem alignment */ 1562 __u32 shadow_alignment; 1563 /* context save area size */ 1564 __u32 csa_size; 1565 /* context save area base virtual mem alignment */ 1566 __u32 csa_alignment; 1567 }; 1568 1569 /* IP specific fw related information used in the 1570 * subquery AMDGPU_INFO_UQ_FW_AREAS 1571 */ 1572 struct drm_amdgpu_info_uq_fw_areas { 1573 union { 1574 struct drm_amdgpu_info_uq_fw_areas_gfx gfx; 1575 }; 1576 }; 1577 1578 struct drm_amdgpu_info_num_handles { 1579 /** Max handles as supported by firmware for UVD */ 1580 __u32 uvd_max_handles; 1581 /** Handles currently in use for UVD */ 1582 __u32 uvd_used_handles; 1583 }; 1584 1585 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1586 1587 struct drm_amdgpu_info_vce_clock_table_entry { 1588 /** System clock */ 1589 __u32 sclk; 1590 /** Memory clock */ 1591 __u32 mclk; 1592 /** VCE clock */ 1593 __u32 eclk; 1594 __u32 pad; 1595 }; 1596 1597 struct drm_amdgpu_info_vce_clock_table { 1598 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1599 __u32 num_valid_entries; 1600 __u32 pad; 1601 }; 1602 1603 /* query video encode/decode caps */ 1604 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1605 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1606 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1607 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1608 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1609 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1610 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1611 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1612 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1613 1614 struct drm_amdgpu_info_video_codec_info { 1615 __u32 valid; 1616 __u32 max_width; 1617 __u32 max_height; 1618 __u32 max_pixels_per_frame; 1619 __u32 max_level; 1620 __u32 pad; 1621 }; 1622 1623 struct drm_amdgpu_info_video_caps { 1624 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1625 }; 1626 1627 #define AMDGPU_VMHUB_TYPE_MASK 0xff 1628 #define AMDGPU_VMHUB_TYPE_SHIFT 0 1629 #define AMDGPU_VMHUB_TYPE_GFX 0 1630 #define AMDGPU_VMHUB_TYPE_MM0 1 1631 #define AMDGPU_VMHUB_TYPE_MM1 2 1632 #define AMDGPU_VMHUB_IDX_MASK 0xff00 1633 #define AMDGPU_VMHUB_IDX_SHIFT 8 1634 1635 struct drm_amdgpu_info_gpuvm_fault { 1636 __u64 addr; 1637 __u32 status; 1638 __u32 vmhub; 1639 }; 1640 1641 struct drm_amdgpu_info_uq_metadata_gfx { 1642 /* shadow area size for gfx11 */ 1643 __u32 shadow_size; 1644 /* shadow area base virtual alignment for gfx11 */ 1645 __u32 shadow_alignment; 1646 /* context save area size for gfx11 */ 1647 __u32 csa_size; 1648 /* context save area base virtual alignment for gfx11 */ 1649 __u32 csa_alignment; 1650 }; 1651 1652 struct drm_amdgpu_info_uq_metadata { 1653 union { 1654 struct drm_amdgpu_info_uq_metadata_gfx gfx; 1655 }; 1656 }; 1657 1658 /* 1659 * Supported GPU families 1660 */ 1661 #define AMDGPU_FAMILY_UNKNOWN 0 1662 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1663 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1664 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1665 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1666 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1667 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1668 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1669 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1670 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1671 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1672 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1673 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1674 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1675 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1676 #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ 1677 #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ 1678 1679 /* FIXME wrong namespace! */ 1680 struct drm_color_ctm_3x4 { 1681 /* 1682 * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude 1683 * (not two's complement!) format. 1684 */ 1685 __u64 matrix[12]; 1686 }; 1687 1688 #if defined(__cplusplus) 1689 } 1690 #endif 1691 1692 #endif 1693