1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 #define DRM_AMDGPU_USERQ 0x16 58 #define DRM_AMDGPU_USERQ_SIGNAL 0x17 59 #define DRM_AMDGPU_USERQ_WAIT 0x18 60 #define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 61 #define DRM_AMDGPU_PROC_OPTIONS 0x1A 62 63 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 64 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 65 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 66 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 67 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 68 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 69 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 70 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 71 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 72 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 73 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 74 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 75 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 76 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 77 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 78 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 79 #define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) 80 #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) 81 #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) 82 #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles) 83 #define DRM_IOCTL_AMDGPU_PROC_OPTIONS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options) 84 85 /** 86 * DOC: memory domains 87 * 88 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 89 * Memory in this pool could be swapped out to disk if there is pressure. 90 * 91 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 92 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 93 * pages of system memory, allows GPU access system memory in a linearized 94 * fashion. 95 * 96 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 97 * carved out by the BIOS. 98 * 99 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 100 * across shader threads. 101 * 102 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 103 * execution of all the waves on a device. 104 * 105 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 106 * for appending data. 107 * 108 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 109 * signalling user mode queues. 110 */ 111 #define AMDGPU_GEM_DOMAIN_CPU 0x1 112 #define AMDGPU_GEM_DOMAIN_GTT 0x2 113 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 114 #define AMDGPU_GEM_DOMAIN_GDS 0x8 115 #define AMDGPU_GEM_DOMAIN_GWS 0x10 116 #define AMDGPU_GEM_DOMAIN_OA 0x20 117 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 118 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 119 AMDGPU_GEM_DOMAIN_GTT | \ 120 AMDGPU_GEM_DOMAIN_VRAM | \ 121 AMDGPU_GEM_DOMAIN_GDS | \ 122 AMDGPU_GEM_DOMAIN_GWS | \ 123 AMDGPU_GEM_DOMAIN_OA | \ 124 AMDGPU_GEM_DOMAIN_DOORBELL) 125 126 /* Flag that CPU access will be required for the case of VRAM domain */ 127 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 128 /* Flag that CPU access will not work, this VRAM domain is invisible */ 129 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 130 /* Flag that USWC attributes should be used for GTT */ 131 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 132 /* Flag that the memory should be in VRAM and cleared */ 133 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 134 /* Flag that allocating the BO should use linear VRAM */ 135 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 136 /* Flag that BO is always valid in this VM */ 137 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 138 /* Flag that BO sharing will be explicitly synchronized */ 139 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 140 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 141 * for the second page onward should be set to NC. It should never 142 * be used by user space applications. 143 */ 144 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 145 /* Flag that BO may contain sensitive data that must be wiped before 146 * releasing the memory 147 */ 148 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 149 /* Flag that BO will be encrypted and that the TMZ bit should be 150 * set in the PTEs when mapping this buffer via GPUVM or 151 * accessing it with various hw blocks 152 */ 153 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 154 /* Flag that BO will be used only in preemptible context, which does 155 * not require GTT memory accounting 156 */ 157 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 158 /* Flag that BO can be discarded under memory pressure without keeping the 159 * content. 160 */ 161 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 162 /* Flag that BO is shared coherently between multiple devices or CPU threads. 163 * May depend on GPU instructions to flush caches to system scope explicitly. 164 * 165 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 166 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 167 */ 168 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 169 /* Flag that BO should not be cached by GPU. Coherent without having to flush 170 * GPU caches explicitly 171 * 172 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 173 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 174 */ 175 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 176 /* Flag that BO should be coherent across devices when using device-level 177 * atomics. May depend on GPU instructions to flush caches to device scope 178 * explicitly, promoting them to system scope automatically. 179 * 180 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 181 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 182 */ 183 #define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 184 /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */ 185 #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) 186 187 struct drm_amdgpu_gem_create_in { 188 /** the requested memory size */ 189 __u64 bo_size; 190 /** physical start_addr alignment in bytes for some HW requirements */ 191 __u64 alignment; 192 /** the requested memory domains */ 193 __u64 domains; 194 /** allocation flags */ 195 __u64 domain_flags; 196 }; 197 198 struct drm_amdgpu_gem_create_out { 199 /** returned GEM object handle */ 200 __u32 handle; 201 __u32 _pad; 202 }; 203 204 union drm_amdgpu_gem_create { 205 struct drm_amdgpu_gem_create_in in; 206 struct drm_amdgpu_gem_create_out out; 207 }; 208 209 /** Opcode to create new residency list. */ 210 #define AMDGPU_BO_LIST_OP_CREATE 0 211 /** Opcode to destroy previously created residency list */ 212 #define AMDGPU_BO_LIST_OP_DESTROY 1 213 /** Opcode to update resource information in the list */ 214 #define AMDGPU_BO_LIST_OP_UPDATE 2 215 216 struct drm_amdgpu_bo_list_in { 217 /** Type of operation */ 218 __u32 operation; 219 /** Handle of list or 0 if we want to create one */ 220 __u32 list_handle; 221 /** Number of BOs in list */ 222 __u32 bo_number; 223 /** Size of each element describing BO */ 224 __u32 bo_info_size; 225 /** Pointer to array describing BOs */ 226 __u64 bo_info_ptr; 227 }; 228 229 struct drm_amdgpu_bo_list_entry { 230 /** Handle of BO */ 231 __u32 bo_handle; 232 /** New (if specified) BO priority to be used during migration */ 233 __u32 bo_priority; 234 }; 235 236 struct drm_amdgpu_bo_list_out { 237 /** Handle of resource list */ 238 __u32 list_handle; 239 __u32 _pad; 240 }; 241 242 union drm_amdgpu_bo_list { 243 struct drm_amdgpu_bo_list_in in; 244 struct drm_amdgpu_bo_list_out out; 245 }; 246 247 /* context related */ 248 #define AMDGPU_CTX_OP_ALLOC_CTX 1 249 #define AMDGPU_CTX_OP_FREE_CTX 2 250 #define AMDGPU_CTX_OP_QUERY_STATE 3 251 #define AMDGPU_CTX_OP_QUERY_STATE2 4 252 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 253 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 254 255 /* GPU reset status */ 256 #define AMDGPU_CTX_NO_RESET 0 257 /* this the context caused it */ 258 #define AMDGPU_CTX_GUILTY_RESET 1 259 /* some other context caused it */ 260 #define AMDGPU_CTX_INNOCENT_RESET 2 261 /* unknown cause */ 262 #define AMDGPU_CTX_UNKNOWN_RESET 3 263 264 /* indicate gpu reset occurred after ctx created */ 265 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 266 /* indicate vram lost occurred after ctx created */ 267 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 268 /* indicate some job from this context once cause gpu hang */ 269 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 270 /* indicate some errors are detected by RAS */ 271 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 272 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 273 /* indicate that the reset hasn't completed yet */ 274 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 275 276 /* Context priority level */ 277 #define AMDGPU_CTX_PRIORITY_UNSET -2048 278 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 279 #define AMDGPU_CTX_PRIORITY_LOW -512 280 #define AMDGPU_CTX_PRIORITY_NORMAL 0 281 /* 282 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 283 * CAP_SYS_NICE or DRM_MASTER 284 */ 285 #define AMDGPU_CTX_PRIORITY_HIGH 512 286 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 287 288 /* select a stable profiling pstate for perfmon tools */ 289 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 290 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 291 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 292 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 293 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 294 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 295 296 struct drm_amdgpu_ctx_in { 297 /** AMDGPU_CTX_OP_* */ 298 __u32 op; 299 /** Flags */ 300 __u32 flags; 301 __u32 ctx_id; 302 /** AMDGPU_CTX_PRIORITY_* */ 303 __s32 priority; 304 }; 305 306 union drm_amdgpu_ctx_out { 307 struct { 308 __u32 ctx_id; 309 __u32 _pad; 310 } alloc; 311 312 struct { 313 /** For future use, no flags defined so far */ 314 __u64 flags; 315 /** Number of resets caused by this context so far. */ 316 __u32 hangs; 317 /** Reset status since the last call of the ioctl. */ 318 __u32 reset_status; 319 } state; 320 321 struct { 322 __u32 flags; 323 __u32 _pad; 324 } pstate; 325 }; 326 327 union drm_amdgpu_ctx { 328 struct drm_amdgpu_ctx_in in; 329 union drm_amdgpu_ctx_out out; 330 }; 331 332 /* user queue IOCTL operations */ 333 #define AMDGPU_USERQ_OP_CREATE 1 334 #define AMDGPU_USERQ_OP_FREE 2 335 336 /* queue priority levels */ 337 /* low < normal low < normal high < high */ 338 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3 339 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0 340 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0 341 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1 342 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2 343 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */ 344 /* for queues that need access to protected content */ 345 #define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2) 346 347 /* 348 * This structure is a container to pass input configuration 349 * info for all supported userqueue related operations. 350 * For operation AMDGPU_USERQ_OP_CREATE: user is expected 351 * to set all fields, excep the parameter 'queue_id'. 352 * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected 353 * to be set is 'queue_id', eveything else is ignored. 354 */ 355 struct drm_amdgpu_userq_in { 356 /** AMDGPU_USERQ_OP_* */ 357 __u32 op; 358 /** Queue id passed for operation USERQ_OP_FREE */ 359 __u32 queue_id; 360 /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */ 361 __u32 ip_type; 362 /** 363 * @doorbell_handle: the handle of doorbell GEM object 364 * associated with this userqueue client. 365 */ 366 __u32 doorbell_handle; 367 /** 368 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo. 369 * Kernel will generate absolute doorbell offset using doorbell_handle 370 * and doorbell_offset in the doorbell bo. 371 */ 372 __u32 doorbell_offset; 373 /** 374 * @flags: flags used for queue parameters 375 */ 376 __u32 flags; 377 /** 378 * @queue_va: Virtual address of the GPU memory which holds the queue 379 * object. The queue holds the workload packets. 380 */ 381 __u64 queue_va; 382 /** 383 * @queue_size: Size of the queue in bytes, this needs to be 256-byte 384 * aligned. 385 */ 386 __u64 queue_size; 387 /** 388 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR. 389 * This object must be at least 8 byte in size and aligned to 8-byte offset. 390 */ 391 __u64 rptr_va; 392 /** 393 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR. 394 * This object must be at least 8 byte in size and aligned to 8-byte offset. 395 * 396 * Queue, RPTR and WPTR can come from the same object, as long as the size 397 * and alignment related requirements are met. 398 */ 399 __u64 wptr_va; 400 /** 401 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow 402 * the GPU to uniquely define and identify a usermode queue. 403 * 404 * MQD data can be of different size for different GPU IP/engine and 405 * their respective versions/revisions, so this points to a __u64 * 406 * which holds IP specific MQD of this usermode queue. 407 */ 408 __u64 mqd; 409 /** 410 * @size: size of MQD data in bytes, it must match the MQD structure 411 * size of the respective engine/revision defined in UAPI for ex, for 412 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11). 413 */ 414 __u64 mqd_size; 415 }; 416 417 /* The structure to carry output of userqueue ops */ 418 struct drm_amdgpu_userq_out { 419 /** 420 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique 421 * queue ID to represent the newly created userqueue in the system, otherwise 422 * it should be ignored. 423 */ 424 __u32 queue_id; 425 __u32 _pad; 426 }; 427 428 union drm_amdgpu_userq { 429 struct drm_amdgpu_userq_in in; 430 struct drm_amdgpu_userq_out out; 431 }; 432 433 /* GFX V11 IP specific MQD parameters */ 434 struct drm_amdgpu_userq_mqd_gfx11 { 435 /** 436 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer. 437 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 438 */ 439 __u64 shadow_va; 440 /** 441 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 442 * Use AMDGPU_INFO_IOCTL to find the exact size of the object. 443 */ 444 __u64 csa_va; 445 }; 446 447 /* GFX V11 SDMA IP specific MQD parameters */ 448 struct drm_amdgpu_userq_mqd_sdma_gfx11 { 449 /** 450 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. 451 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 452 * to get the size. 453 */ 454 __u64 csa_va; 455 }; 456 457 /* GFX V11 Compute IP specific MQD parameters */ 458 struct drm_amdgpu_userq_mqd_compute_gfx11 { 459 /** 460 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer. 461 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL 462 * to get the size. 463 */ 464 __u64 eop_va; 465 }; 466 467 /* userq signal/wait ioctl */ 468 struct drm_amdgpu_userq_signal { 469 /** 470 * @queue_id: Queue handle used by the userq fence creation function 471 * to retrieve the WPTR. 472 */ 473 __u32 queue_id; 474 __u32 pad; 475 /** 476 * @syncobj_handles: The list of syncobj handles submitted by the user queue 477 * job to be signaled. 478 */ 479 __u64 syncobj_handles; 480 /** 481 * @num_syncobj_handles: A count that represents the number of syncobj handles in 482 * @syncobj_handles. 483 */ 484 __u16 num_syncobj_handles; 485 __u16 pad0; 486 __u32 pad1; 487 /** 488 * @bo_read_handles: The list of BO handles that the submitted user queue job 489 * is using for read only. This will update BO fences in the kernel. 490 */ 491 __u64 bo_read_handles; 492 /** 493 * @bo_write_handles: The list of BO handles that the submitted user queue job 494 * is using for write only. This will update BO fences in the kernel. 495 */ 496 __u64 bo_write_handles; 497 /** 498 * @num_bo_read_handles: A count that represents the number of read BO handles in 499 * @bo_read_handles. 500 */ 501 __u32 num_bo_read_handles; 502 /** 503 * @num_bo_write_handles: A count that represents the number of write BO handles in 504 * @bo_write_handles. 505 */ 506 __u32 num_bo_write_handles; 507 }; 508 509 struct drm_amdgpu_userq_fence_info { 510 /** 511 * @va: A gpu address allocated for each queue which stores the 512 * read pointer (RPTR) value. 513 */ 514 __u64 va; 515 /** 516 * @value: A 64 bit value represents the write pointer (WPTR) of the 517 * queue commands which compared with the RPTR value to signal the 518 * fences. 519 */ 520 __u64 value; 521 }; 522 523 struct drm_amdgpu_userq_wait { 524 /** 525 * @waitq_id: Queue handle used by the userq wait IOCTL to retrieve the 526 * wait queue and maintain the fence driver references in it. 527 */ 528 __u32 waitq_id; 529 __u32 pad; 530 /** 531 * @syncobj_handles: The list of syncobj handles submitted by the user queue 532 * job to get the va/value pairs. 533 */ 534 __u64 syncobj_handles; 535 /** 536 * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by 537 * the user queue job to get the va/value pairs at given @syncobj_timeline_points. 538 */ 539 __u64 syncobj_timeline_handles; 540 /** 541 * @syncobj_timeline_points: The list of timeline syncobj points submitted by the 542 * user queue job for the corresponding @syncobj_timeline_handles. 543 */ 544 __u64 syncobj_timeline_points; 545 /** 546 * @bo_read_handles: The list of read BO handles submitted by the user queue 547 * job to get the va/value pairs. 548 */ 549 __u64 bo_read_handles; 550 /** 551 * @bo_write_handles: The list of write BO handles submitted by the user queue 552 * job to get the va/value pairs. 553 */ 554 __u64 bo_write_handles; 555 /** 556 * @num_syncobj_timeline_handles: A count that represents the number of timeline 557 * syncobj handles in @syncobj_timeline_handles. 558 */ 559 __u16 num_syncobj_timeline_handles; 560 /** 561 * @num_fences: This field can be used both as input and output. As input it defines 562 * the maximum number of fences that can be returned and as output it will specify 563 * how many fences were actually returned from the ioctl. 564 */ 565 __u16 num_fences; 566 /** 567 * @num_syncobj_handles: A count that represents the number of syncobj handles in 568 * @syncobj_handles. 569 */ 570 __u16 num_syncobj_handles; 571 __u16 pad0; 572 /** 573 * @num_bo_read_handles: A count that represents the number of read BO handles in 574 * @bo_read_handles. 575 */ 576 __u32 num_bo_read_handles; 577 /** 578 * @num_bo_write_handles: A count that represents the number of write BO handles in 579 * @bo_write_handles. 580 */ 581 __u32 num_bo_write_handles; 582 /** 583 * @out_fences: The field is a return value from the ioctl containing the list of 584 * address/value pairs to wait for. 585 */ 586 __u64 out_fences; 587 }; 588 589 /* vm ioctl */ 590 #define AMDGPU_VM_OP_RESERVE_VMID 1 591 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 592 593 struct drm_amdgpu_vm_in { 594 /** AMDGPU_VM_OP_* */ 595 __u32 op; 596 __u32 flags; 597 }; 598 599 struct drm_amdgpu_vm_out { 600 /** For future use, no flags defined so far */ 601 __u64 flags; 602 }; 603 604 union drm_amdgpu_vm { 605 struct drm_amdgpu_vm_in in; 606 struct drm_amdgpu_vm_out out; 607 }; 608 609 /* sched ioctl */ 610 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 611 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 612 613 struct drm_amdgpu_sched_in { 614 /* AMDGPU_SCHED_OP_* */ 615 __u32 op; 616 __u32 fd; 617 /** AMDGPU_CTX_PRIORITY_* */ 618 __s32 priority; 619 __u32 ctx_id; 620 }; 621 622 union drm_amdgpu_sched { 623 struct drm_amdgpu_sched_in in; 624 }; 625 626 /* 627 * This is not a reliable API and you should expect it to fail for any 628 * number of reasons and have fallback path that do not use userptr to 629 * perform any operation. 630 */ 631 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 632 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 633 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 634 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 635 636 struct drm_amdgpu_gem_userptr { 637 __u64 addr; 638 __u64 size; 639 /* AMDGPU_GEM_USERPTR_* */ 640 __u32 flags; 641 /* Resulting GEM handle */ 642 __u32 handle; 643 }; 644 645 /* SI-CI-VI: */ 646 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 647 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 648 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 649 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 650 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 651 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 652 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 653 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 654 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 655 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 656 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 657 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 658 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 659 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 660 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 661 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 662 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 663 664 /* GFX9 - GFX11: */ 665 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 666 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 667 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 668 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 669 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 670 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 671 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 672 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 673 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 674 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 675 #define AMDGPU_TILING_SCANOUT_SHIFT 63 676 #define AMDGPU_TILING_SCANOUT_MASK 0x1 677 678 /* GFX12 and later: */ 679 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 680 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 681 /* These are DCC recompression settings for memory management: */ 682 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 683 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ 684 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 685 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ 686 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 687 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 688 /* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata 689 * to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */ 690 #define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14 691 #define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1 692 /* bit gap */ 693 #define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63 694 #define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1 695 696 /* Set/Get helpers for tiling flags. */ 697 #define AMDGPU_TILING_SET(field, value) \ 698 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 699 #define AMDGPU_TILING_GET(value, field) \ 700 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 701 702 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 703 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 704 705 /** The same structure is shared for input/output */ 706 struct drm_amdgpu_gem_metadata { 707 /** GEM Object handle */ 708 __u32 handle; 709 /** Do we want get or set metadata */ 710 __u32 op; 711 struct { 712 /** For future use, no flags defined so far */ 713 __u64 flags; 714 /** family specific tiling info */ 715 __u64 tiling_info; 716 __u32 data_size_bytes; 717 __u32 data[64]; 718 } data; 719 }; 720 721 struct drm_amdgpu_gem_mmap_in { 722 /** the GEM object handle */ 723 __u32 handle; 724 __u32 _pad; 725 }; 726 727 struct drm_amdgpu_gem_mmap_out { 728 /** mmap offset from the vma offset manager */ 729 __u64 addr_ptr; 730 }; 731 732 union drm_amdgpu_gem_mmap { 733 struct drm_amdgpu_gem_mmap_in in; 734 struct drm_amdgpu_gem_mmap_out out; 735 }; 736 737 struct drm_amdgpu_gem_wait_idle_in { 738 /** GEM object handle */ 739 __u32 handle; 740 /** For future use, no flags defined so far */ 741 __u32 flags; 742 /** Absolute timeout to wait */ 743 __u64 timeout; 744 }; 745 746 struct drm_amdgpu_gem_wait_idle_out { 747 /** BO status: 0 - BO is idle, 1 - BO is busy */ 748 __u32 status; 749 /** Returned current memory domain */ 750 __u32 domain; 751 }; 752 753 union drm_amdgpu_gem_wait_idle { 754 struct drm_amdgpu_gem_wait_idle_in in; 755 struct drm_amdgpu_gem_wait_idle_out out; 756 }; 757 758 struct drm_amdgpu_wait_cs_in { 759 /* Command submission handle 760 * handle equals 0 means none to wait for 761 * handle equals ~0ull means wait for the latest sequence number 762 */ 763 __u64 handle; 764 /** Absolute timeout to wait */ 765 __u64 timeout; 766 __u32 ip_type; 767 __u32 ip_instance; 768 __u32 ring; 769 __u32 ctx_id; 770 }; 771 772 struct drm_amdgpu_wait_cs_out { 773 /** CS status: 0 - CS completed, 1 - CS still busy */ 774 __u64 status; 775 }; 776 777 union drm_amdgpu_wait_cs { 778 struct drm_amdgpu_wait_cs_in in; 779 struct drm_amdgpu_wait_cs_out out; 780 }; 781 782 struct drm_amdgpu_fence { 783 __u32 ctx_id; 784 __u32 ip_type; 785 __u32 ip_instance; 786 __u32 ring; 787 __u64 seq_no; 788 }; 789 790 struct drm_amdgpu_wait_fences_in { 791 /** This points to uint64_t * which points to fences */ 792 __u64 fences; 793 __u32 fence_count; 794 __u32 wait_all; 795 __u64 timeout_ns; 796 }; 797 798 struct drm_amdgpu_wait_fences_out { 799 __u32 status; 800 __u32 first_signaled; 801 }; 802 803 union drm_amdgpu_wait_fences { 804 struct drm_amdgpu_wait_fences_in in; 805 struct drm_amdgpu_wait_fences_out out; 806 }; 807 808 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 809 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 810 #define AMDGPU_GEM_OP_GET_MAPPING_INFO 2 811 812 struct drm_amdgpu_gem_vm_entry { 813 /* Start of mapping (in bytes) */ 814 __u64 addr; 815 816 /* Size of mapping (in bytes) */ 817 __u64 size; 818 819 /* Mapping offset */ 820 __u64 offset; 821 822 /* flags needed to recreate mapping */ 823 __u64 flags; 824 }; 825 826 /* Sets or returns a value associated with a buffer. */ 827 struct drm_amdgpu_gem_op { 828 /** GEM object handle */ 829 __u32 handle; 830 /** AMDGPU_GEM_OP_* */ 831 __u32 op; 832 /** Input or return value. For MAPPING_INFO op: pointer to array of struct drm_amdgpu_gem_vm_entry */ 833 __u64 value; 834 /** For MAPPING_INFO op: number of mappings (in/out) */ 835 __u32 num_entries; 836 837 __u32 padding; 838 }; 839 840 #define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT (1 << 0) 841 842 struct drm_amdgpu_gem_list_handles { 843 /* User pointer to array of drm_amdgpu_gem_bo_info_entry */ 844 __u64 entries; 845 846 /* Size of entries buffer / Number of handles in process (if larger than size of buffer, must retry) */ 847 __u32 num_entries; 848 849 __u32 padding; 850 }; 851 852 struct drm_amdgpu_gem_list_handles_entry { 853 /* gem handle of buffer object */ 854 __u32 gem_handle; 855 856 /* Currently just one flag: IS_IMPORT */ 857 __u32 flags; 858 859 /* Size of bo */ 860 __u64 size; 861 862 /* Preferred domains for GEM_CREATE */ 863 __u64 preferred_domains; 864 865 /* GEM_CREATE flags for re-creation of buffer */ 866 __u64 alloc_flags; 867 868 /* physical start_addr alignment in bytes for some HW requirements */ 869 __u64 alignment; 870 }; 871 872 #define AMDGPU_VA_OP_MAP 1 873 #define AMDGPU_VA_OP_UNMAP 2 874 #define AMDGPU_VA_OP_CLEAR 3 875 #define AMDGPU_VA_OP_REPLACE 4 876 877 /* Delay the page table update till the next CS */ 878 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 879 880 /* Mapping flags */ 881 /* readable mapping */ 882 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 883 /* writable mapping */ 884 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 885 /* executable mapping, new for VI */ 886 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 887 /* unmapped page of partially resident textures */ 888 #define AMDGPU_VM_PAGE_PRT (1 << 4) 889 /* MTYPE flags use bit 5 to 8 */ 890 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 891 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 892 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 893 /* Use Non Coherent MTYPE instead of default MTYPE */ 894 #define AMDGPU_VM_MTYPE_NC (1 << 5) 895 /* Use Write Combine MTYPE instead of default MTYPE */ 896 #define AMDGPU_VM_MTYPE_WC (2 << 5) 897 /* Use Cache Coherent MTYPE instead of default MTYPE */ 898 #define AMDGPU_VM_MTYPE_CC (3 << 5) 899 /* Use UnCached MTYPE instead of default MTYPE */ 900 #define AMDGPU_VM_MTYPE_UC (4 << 5) 901 /* Use Read Write MTYPE instead of default MTYPE */ 902 #define AMDGPU_VM_MTYPE_RW (5 << 5) 903 /* don't allocate MALL */ 904 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 905 906 struct drm_amdgpu_gem_va { 907 /** GEM object handle */ 908 __u32 handle; 909 __u32 _pad; 910 /** AMDGPU_VA_OP_* */ 911 __u32 operation; 912 /** AMDGPU_VM_PAGE_* */ 913 __u32 flags; 914 /** va address to assign . Must be correctly aligned.*/ 915 __u64 va_address; 916 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 917 __u64 offset_in_bo; 918 /** Specify mapping size. Must be correctly aligned. */ 919 __u64 map_size; 920 /** 921 * vm_timeline_point is a sequence number used to add new timeline point. 922 */ 923 __u64 vm_timeline_point; 924 /** 925 * The vm page table update fence is installed in given vm_timeline_syncobj_out 926 * at vm_timeline_point. 927 */ 928 __u32 vm_timeline_syncobj_out; 929 /** the number of syncobj handles in @input_fence_syncobj_handles */ 930 __u32 num_syncobj_handles; 931 /** Array of sync object handle to wait for given input fences */ 932 __u64 input_fence_syncobj_handles; 933 }; 934 935 #define AMDGPU_HW_IP_GFX 0 936 #define AMDGPU_HW_IP_COMPUTE 1 937 #define AMDGPU_HW_IP_DMA 2 938 #define AMDGPU_HW_IP_UVD 3 939 #define AMDGPU_HW_IP_VCE 4 940 #define AMDGPU_HW_IP_UVD_ENC 5 941 #define AMDGPU_HW_IP_VCN_DEC 6 942 /* 943 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 944 * both encoding and decoding jobs. 945 */ 946 #define AMDGPU_HW_IP_VCN_ENC 7 947 #define AMDGPU_HW_IP_VCN_JPEG 8 948 #define AMDGPU_HW_IP_VPE 9 949 #define AMDGPU_HW_IP_NUM 10 950 951 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 952 953 #define AMDGPU_CHUNK_ID_IB 0x01 954 #define AMDGPU_CHUNK_ID_FENCE 0x02 955 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 956 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 957 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 958 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 959 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 960 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 961 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 962 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 963 964 struct drm_amdgpu_cs_chunk { 965 __u32 chunk_id; 966 __u32 length_dw; 967 __u64 chunk_data; 968 }; 969 970 struct drm_amdgpu_cs_in { 971 /** Rendering context id */ 972 __u32 ctx_id; 973 /** Handle of resource list associated with CS */ 974 __u32 bo_list_handle; 975 __u32 num_chunks; 976 __u32 flags; 977 /** this points to __u64 * which point to cs chunks */ 978 __u64 chunks; 979 }; 980 981 struct drm_amdgpu_cs_out { 982 __u64 handle; 983 }; 984 985 union drm_amdgpu_cs { 986 struct drm_amdgpu_cs_in in; 987 struct drm_amdgpu_cs_out out; 988 }; 989 990 /* Specify flags to be used for IB */ 991 992 /* This IB should be submitted to CE */ 993 #define AMDGPU_IB_FLAG_CE (1<<0) 994 995 /* Preamble flag, which means the IB could be dropped if no context switch */ 996 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 997 998 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 999 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 1000 1001 /* The IB fence should do the L2 writeback but not invalidate any shader 1002 * caches (L2/vL1/sL1/I$). */ 1003 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 1004 1005 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 1006 * This will reset wave ID counters for the IB. 1007 */ 1008 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 1009 1010 /* Flag the IB as secure (TMZ) 1011 */ 1012 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 1013 1014 /* Tell KMD to flush and invalidate caches 1015 */ 1016 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 1017 1018 struct drm_amdgpu_cs_chunk_ib { 1019 __u32 _pad; 1020 /** AMDGPU_IB_FLAG_* */ 1021 __u32 flags; 1022 /** Virtual address to begin IB execution */ 1023 __u64 va_start; 1024 /** Size of submission */ 1025 __u32 ib_bytes; 1026 /** HW IP to submit to */ 1027 __u32 ip_type; 1028 /** HW IP index of the same type to submit to */ 1029 __u32 ip_instance; 1030 /** Ring index to submit to */ 1031 __u32 ring; 1032 }; 1033 1034 struct drm_amdgpu_cs_chunk_dep { 1035 __u32 ip_type; 1036 __u32 ip_instance; 1037 __u32 ring; 1038 __u32 ctx_id; 1039 __u64 handle; 1040 }; 1041 1042 struct drm_amdgpu_cs_chunk_fence { 1043 __u32 handle; 1044 __u32 offset; 1045 }; 1046 1047 struct drm_amdgpu_cs_chunk_sem { 1048 __u32 handle; 1049 }; 1050 1051 struct drm_amdgpu_cs_chunk_syncobj { 1052 __u32 handle; 1053 __u32 flags; 1054 __u64 point; 1055 }; 1056 1057 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 1058 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 1059 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 1060 1061 union drm_amdgpu_fence_to_handle { 1062 struct { 1063 struct drm_amdgpu_fence fence; 1064 __u32 what; 1065 __u32 pad; 1066 } in; 1067 struct { 1068 __u32 handle; 1069 } out; 1070 }; 1071 1072 struct drm_amdgpu_cs_chunk_data { 1073 union { 1074 struct drm_amdgpu_cs_chunk_ib ib_data; 1075 struct drm_amdgpu_cs_chunk_fence fence_data; 1076 }; 1077 }; 1078 1079 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 1080 1081 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 1082 __u64 shadow_va; 1083 __u64 csa_va; 1084 __u64 gds_va; 1085 __u64 flags; 1086 }; 1087 1088 /* 1089 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 1090 * 1091 */ 1092 #define AMDGPU_IDS_FLAGS_FUSION 0x01 1093 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x02 1094 #define AMDGPU_IDS_FLAGS_TMZ 0x04 1095 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x08 1096 #define AMDGPU_IDS_FLAGS_GANG_SUBMIT 0x10 1097 1098 /* 1099 * Query h/w info: Flag identifying VF/PF/PT mode 1100 * 1101 */ 1102 #define AMDGPU_IDS_FLAGS_MODE_MASK 0x300 1103 #define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8 1104 #define AMDGPU_IDS_FLAGS_MODE_PF 0x0 1105 #define AMDGPU_IDS_FLAGS_MODE_VF 0x1 1106 #define AMDGPU_IDS_FLAGS_MODE_PT 0x2 1107 1108 /* indicate if acceleration can be working */ 1109 #define AMDGPU_INFO_ACCEL_WORKING 0x00 1110 /* get the crtc_id from the mode object id? */ 1111 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 1112 /* query hw IP info */ 1113 #define AMDGPU_INFO_HW_IP_INFO 0x02 1114 /* query hw IP instance count for the specified type */ 1115 #define AMDGPU_INFO_HW_IP_COUNT 0x03 1116 /* timestamp for GL_ARB_timer_query */ 1117 #define AMDGPU_INFO_TIMESTAMP 0x05 1118 /* Query the firmware version */ 1119 #define AMDGPU_INFO_FW_VERSION 0x0e 1120 /* Subquery id: Query VCE firmware version */ 1121 #define AMDGPU_INFO_FW_VCE 0x1 1122 /* Subquery id: Query UVD firmware version */ 1123 #define AMDGPU_INFO_FW_UVD 0x2 1124 /* Subquery id: Query GMC firmware version */ 1125 #define AMDGPU_INFO_FW_GMC 0x03 1126 /* Subquery id: Query GFX ME firmware version */ 1127 #define AMDGPU_INFO_FW_GFX_ME 0x04 1128 /* Subquery id: Query GFX PFP firmware version */ 1129 #define AMDGPU_INFO_FW_GFX_PFP 0x05 1130 /* Subquery id: Query GFX CE firmware version */ 1131 #define AMDGPU_INFO_FW_GFX_CE 0x06 1132 /* Subquery id: Query GFX RLC firmware version */ 1133 #define AMDGPU_INFO_FW_GFX_RLC 0x07 1134 /* Subquery id: Query GFX MEC firmware version */ 1135 #define AMDGPU_INFO_FW_GFX_MEC 0x08 1136 /* Subquery id: Query SMC firmware version */ 1137 #define AMDGPU_INFO_FW_SMC 0x0a 1138 /* Subquery id: Query SDMA firmware version */ 1139 #define AMDGPU_INFO_FW_SDMA 0x0b 1140 /* Subquery id: Query PSP SOS firmware version */ 1141 #define AMDGPU_INFO_FW_SOS 0x0c 1142 /* Subquery id: Query PSP ASD firmware version */ 1143 #define AMDGPU_INFO_FW_ASD 0x0d 1144 /* Subquery id: Query VCN firmware version */ 1145 #define AMDGPU_INFO_FW_VCN 0x0e 1146 /* Subquery id: Query GFX RLC SRLC firmware version */ 1147 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 1148 /* Subquery id: Query GFX RLC SRLG firmware version */ 1149 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 1150 /* Subquery id: Query GFX RLC SRLS firmware version */ 1151 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 1152 /* Subquery id: Query DMCU firmware version */ 1153 #define AMDGPU_INFO_FW_DMCU 0x12 1154 #define AMDGPU_INFO_FW_TA 0x13 1155 /* Subquery id: Query DMCUB firmware version */ 1156 #define AMDGPU_INFO_FW_DMCUB 0x14 1157 /* Subquery id: Query TOC firmware version */ 1158 #define AMDGPU_INFO_FW_TOC 0x15 1159 /* Subquery id: Query CAP firmware version */ 1160 #define AMDGPU_INFO_FW_CAP 0x16 1161 /* Subquery id: Query GFX RLCP firmware version */ 1162 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 1163 /* Subquery id: Query GFX RLCV firmware version */ 1164 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 1165 /* Subquery id: Query MES_KIQ firmware version */ 1166 #define AMDGPU_INFO_FW_MES_KIQ 0x19 1167 /* Subquery id: Query MES firmware version */ 1168 #define AMDGPU_INFO_FW_MES 0x1a 1169 /* Subquery id: Query IMU firmware version */ 1170 #define AMDGPU_INFO_FW_IMU 0x1b 1171 /* Subquery id: Query VPE firmware version */ 1172 #define AMDGPU_INFO_FW_VPE 0x1c 1173 1174 /* number of bytes moved for TTM migration */ 1175 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 1176 /* the used VRAM size */ 1177 #define AMDGPU_INFO_VRAM_USAGE 0x10 1178 /* the used GTT size */ 1179 #define AMDGPU_INFO_GTT_USAGE 0x11 1180 /* Information about GDS, etc. resource configuration */ 1181 #define AMDGPU_INFO_GDS_CONFIG 0x13 1182 /* Query information about VRAM and GTT domains */ 1183 #define AMDGPU_INFO_VRAM_GTT 0x14 1184 /* Query information about register in MMR address space*/ 1185 #define AMDGPU_INFO_READ_MMR_REG 0x15 1186 /* Query information about device: rev id, family, etc. */ 1187 #define AMDGPU_INFO_DEV_INFO 0x16 1188 /* visible vram usage */ 1189 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 1190 /* number of TTM buffer evictions */ 1191 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 1192 /* Query memory about VRAM and GTT domains */ 1193 #define AMDGPU_INFO_MEMORY 0x19 1194 /* Query vce clock table */ 1195 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 1196 /* Query vbios related information */ 1197 #define AMDGPU_INFO_VBIOS 0x1B 1198 /* Subquery id: Query vbios size */ 1199 #define AMDGPU_INFO_VBIOS_SIZE 0x1 1200 /* Subquery id: Query vbios image */ 1201 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 1202 /* Subquery id: Query vbios info */ 1203 #define AMDGPU_INFO_VBIOS_INFO 0x3 1204 /* Query UVD handles */ 1205 #define AMDGPU_INFO_NUM_HANDLES 0x1C 1206 /* Query sensor related information */ 1207 #define AMDGPU_INFO_SENSOR 0x1D 1208 /* Subquery id: Query GPU shader clock */ 1209 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 1210 /* Subquery id: Query GPU memory clock */ 1211 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 1212 /* Subquery id: Query GPU temperature */ 1213 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 1214 /* Subquery id: Query GPU load */ 1215 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 1216 /* Subquery id: Query average GPU power */ 1217 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 1218 /* Subquery id: Query northbridge voltage */ 1219 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 1220 /* Subquery id: Query graphics voltage */ 1221 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 1222 /* Subquery id: Query GPU stable pstate shader clock */ 1223 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 1224 /* Subquery id: Query GPU stable pstate memory clock */ 1225 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 1226 /* Subquery id: Query GPU peak pstate shader clock */ 1227 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 1228 /* Subquery id: Query GPU peak pstate memory clock */ 1229 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 1230 /* Subquery id: Query input GPU power */ 1231 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 1232 /* Number of VRAM page faults on CPU access. */ 1233 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 1234 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 1235 /* query ras mask of enabled features*/ 1236 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 1237 /* RAS MASK: UMC (VRAM) */ 1238 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 1239 /* RAS MASK: SDMA */ 1240 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 1241 /* RAS MASK: GFX */ 1242 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 1243 /* RAS MASK: MMHUB */ 1244 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 1245 /* RAS MASK: ATHUB */ 1246 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 1247 /* RAS MASK: PCIE */ 1248 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 1249 /* RAS MASK: HDP */ 1250 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 1251 /* RAS MASK: XGMI */ 1252 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 1253 /* RAS MASK: DF */ 1254 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 1255 /* RAS MASK: SMN */ 1256 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 1257 /* RAS MASK: SEM */ 1258 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 1259 /* RAS MASK: MP0 */ 1260 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 1261 /* RAS MASK: MP1 */ 1262 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 1263 /* RAS MASK: FUSE */ 1264 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 1265 /* query video encode/decode caps */ 1266 #define AMDGPU_INFO_VIDEO_CAPS 0x21 1267 /* Subquery id: Decode */ 1268 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 1269 /* Subquery id: Encode */ 1270 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 1271 /* Query the max number of IBs per gang per submission */ 1272 #define AMDGPU_INFO_MAX_IBS 0x22 1273 /* query last page fault info */ 1274 #define AMDGPU_INFO_GPUVM_FAULT 0x23 1275 /* query FW object size and alignment */ 1276 #define AMDGPU_INFO_UQ_FW_AREAS 0x24 1277 1278 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 1279 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 1280 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 1281 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 1282 1283 struct drm_amdgpu_query_fw { 1284 /** AMDGPU_INFO_FW_* */ 1285 __u32 fw_type; 1286 /** 1287 * Index of the IP if there are more IPs of 1288 * the same type. 1289 */ 1290 __u32 ip_instance; 1291 /** 1292 * Index of the engine. Whether this is used depends 1293 * on the firmware type. (e.g. MEC, SDMA) 1294 */ 1295 __u32 index; 1296 __u32 _pad; 1297 }; 1298 1299 /* Input structure for the INFO ioctl */ 1300 struct drm_amdgpu_info { 1301 /* Where the return value will be stored */ 1302 __u64 return_pointer; 1303 /* The size of the return value. Just like "size" in "snprintf", 1304 * it limits how many bytes the kernel can write. */ 1305 __u32 return_size; 1306 /* The query request id. */ 1307 __u32 query; 1308 1309 union { 1310 struct { 1311 __u32 id; 1312 __u32 _pad; 1313 } mode_crtc; 1314 1315 struct { 1316 /** AMDGPU_HW_IP_* */ 1317 __u32 type; 1318 /** 1319 * Index of the IP if there are more IPs of the same 1320 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 1321 */ 1322 __u32 ip_instance; 1323 } query_hw_ip; 1324 1325 struct { 1326 __u32 dword_offset; 1327 /** number of registers to read */ 1328 __u32 count; 1329 __u32 instance; 1330 /** For future use, no flags defined so far */ 1331 __u32 flags; 1332 } read_mmr_reg; 1333 1334 struct drm_amdgpu_query_fw query_fw; 1335 1336 struct { 1337 __u32 type; 1338 __u32 offset; 1339 } vbios_info; 1340 1341 struct { 1342 __u32 type; 1343 } sensor_info; 1344 1345 struct { 1346 __u32 type; 1347 } video_cap; 1348 }; 1349 }; 1350 1351 struct drm_amdgpu_info_gds { 1352 /** GDS GFX partition size */ 1353 __u32 gds_gfx_partition_size; 1354 /** GDS compute partition size */ 1355 __u32 compute_partition_size; 1356 /** total GDS memory size */ 1357 __u32 gds_total_size; 1358 /** GWS size per GFX partition */ 1359 __u32 gws_per_gfx_partition; 1360 /** GSW size per compute partition */ 1361 __u32 gws_per_compute_partition; 1362 /** OA size per GFX partition */ 1363 __u32 oa_per_gfx_partition; 1364 /** OA size per compute partition */ 1365 __u32 oa_per_compute_partition; 1366 __u32 _pad; 1367 }; 1368 1369 struct drm_amdgpu_info_vram_gtt { 1370 __u64 vram_size; 1371 __u64 vram_cpu_accessible_size; 1372 __u64 gtt_size; 1373 }; 1374 1375 struct drm_amdgpu_heap_info { 1376 /** max. physical memory */ 1377 __u64 total_heap_size; 1378 1379 /** Theoretical max. available memory in the given heap */ 1380 __u64 usable_heap_size; 1381 1382 /** 1383 * Number of bytes allocated in the heap. This includes all processes 1384 * and private allocations in the kernel. It changes when new buffers 1385 * are allocated, freed, and moved. It cannot be larger than 1386 * heap_size. 1387 */ 1388 __u64 heap_usage; 1389 1390 /** 1391 * Theoretical possible max. size of buffer which 1392 * could be allocated in the given heap 1393 */ 1394 __u64 max_allocation; 1395 }; 1396 1397 struct drm_amdgpu_memory_info { 1398 struct drm_amdgpu_heap_info vram; 1399 struct drm_amdgpu_heap_info cpu_accessible_vram; 1400 struct drm_amdgpu_heap_info gtt; 1401 }; 1402 1403 struct drm_amdgpu_info_firmware { 1404 __u32 ver; 1405 __u32 feature; 1406 }; 1407 1408 struct drm_amdgpu_info_vbios { 1409 __u8 name[64]; 1410 __u8 vbios_pn[64]; 1411 __u32 version; 1412 __u32 pad; 1413 __u8 vbios_ver_str[32]; 1414 __u8 date[32]; 1415 }; 1416 1417 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 1418 #define AMDGPU_VRAM_TYPE_GDDR1 1 1419 #define AMDGPU_VRAM_TYPE_DDR2 2 1420 #define AMDGPU_VRAM_TYPE_GDDR3 3 1421 #define AMDGPU_VRAM_TYPE_GDDR4 4 1422 #define AMDGPU_VRAM_TYPE_GDDR5 5 1423 #define AMDGPU_VRAM_TYPE_HBM 6 1424 #define AMDGPU_VRAM_TYPE_DDR3 7 1425 #define AMDGPU_VRAM_TYPE_DDR4 8 1426 #define AMDGPU_VRAM_TYPE_GDDR6 9 1427 #define AMDGPU_VRAM_TYPE_DDR5 10 1428 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1429 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1430 #define AMDGPU_VRAM_TYPE_HBM3E 13 1431 #define AMDGPU_VRAM_TYPE_HBM4 14 1432 1433 struct drm_amdgpu_info_device { 1434 /** PCI Device ID */ 1435 __u32 device_id; 1436 /** Internal chip revision: A0, A1, etc.) */ 1437 __u32 chip_rev; 1438 __u32 external_rev; 1439 /** Revision id in PCI Config space */ 1440 __u32 pci_rev; 1441 __u32 family; 1442 __u32 num_shader_engines; 1443 __u32 num_shader_arrays_per_engine; 1444 /* in KHz */ 1445 __u32 gpu_counter_freq; 1446 __u64 max_engine_clock; 1447 __u64 max_memory_clock; 1448 /* cu information */ 1449 __u32 cu_active_number; 1450 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1451 __u32 cu_ao_mask; 1452 __u32 cu_bitmap[4][4]; 1453 /** Render backend pipe mask. One render backend is CB+DB. */ 1454 __u32 enabled_rb_pipes_mask; 1455 __u32 num_rb_pipes; 1456 __u32 num_hw_gfx_contexts; 1457 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1458 __u32 pcie_gen; 1459 __u64 ids_flags; 1460 /** Starting virtual address for UMDs. */ 1461 __u64 virtual_address_offset; 1462 /** The maximum virtual address */ 1463 __u64 virtual_address_max; 1464 /** Required alignment of virtual addresses. */ 1465 __u32 virtual_address_alignment; 1466 /** Page table entry - fragment size */ 1467 __u32 pte_fragment_size; 1468 __u32 gart_page_size; 1469 /** constant engine ram size*/ 1470 __u32 ce_ram_size; 1471 /** video memory type info*/ 1472 __u32 vram_type; 1473 /** video memory bit width*/ 1474 __u32 vram_bit_width; 1475 /* vce harvesting instance */ 1476 __u32 vce_harvest_config; 1477 /* gfx double offchip LDS buffers */ 1478 __u32 gc_double_offchip_lds_buf; 1479 /* NGG Primitive Buffer */ 1480 __u64 prim_buf_gpu_addr; 1481 /* NGG Position Buffer */ 1482 __u64 pos_buf_gpu_addr; 1483 /* NGG Control Sideband */ 1484 __u64 cntl_sb_buf_gpu_addr; 1485 /* NGG Parameter Cache */ 1486 __u64 param_buf_gpu_addr; 1487 __u32 prim_buf_size; 1488 __u32 pos_buf_size; 1489 __u32 cntl_sb_buf_size; 1490 __u32 param_buf_size; 1491 /* wavefront size*/ 1492 __u32 wave_front_size; 1493 /* shader visible vgprs*/ 1494 __u32 num_shader_visible_vgprs; 1495 /* CU per shader array*/ 1496 __u32 num_cu_per_sh; 1497 /* number of tcc blocks*/ 1498 __u32 num_tcc_blocks; 1499 /* gs vgt table depth*/ 1500 __u32 gs_vgt_table_depth; 1501 /* gs primitive buffer depth*/ 1502 __u32 gs_prim_buffer_depth; 1503 /* max gs wavefront per vgt*/ 1504 __u32 max_gs_waves_per_vgt; 1505 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1506 __u32 pcie_num_lanes; 1507 /* always on cu bitmap */ 1508 __u32 cu_ao_bitmap[4][4]; 1509 /** Starting high virtual address for UMDs. */ 1510 __u64 high_va_offset; 1511 /** The maximum high virtual address */ 1512 __u64 high_va_max; 1513 /* gfx10 pa_sc_tile_steering_override */ 1514 __u32 pa_sc_tile_steering_override; 1515 /* disabled TCCs */ 1516 __u64 tcc_disabled_mask; 1517 __u64 min_engine_clock; 1518 __u64 min_memory_clock; 1519 /* The following fields are only set on gfx11+, older chips set 0. */ 1520 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1521 __u32 num_sqc_per_wgp; 1522 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1523 __u32 sqc_inst_cache_size; 1524 __u32 gl1c_cache_size; 1525 __u32 gl2c_cache_size; 1526 __u64 mall_size; /* AKA infinity cache */ 1527 /* high 32 bits of the rb pipes mask */ 1528 __u32 enabled_rb_pipes_mask_hi; 1529 /* shadow area size for gfx11 */ 1530 __u32 shadow_size; 1531 /* shadow area base virtual alignment for gfx11 */ 1532 __u32 shadow_alignment; 1533 /* context save area size for gfx11 */ 1534 __u32 csa_size; 1535 /* context save area base virtual alignment for gfx11 */ 1536 __u32 csa_alignment; 1537 /* Userq IP mask (1 << AMDGPU_HW_IP_*) */ 1538 __u32 userq_ip_mask; 1539 __u32 pad; 1540 }; 1541 1542 struct drm_amdgpu_info_hw_ip { 1543 /** Version of h/w IP */ 1544 __u32 hw_ip_version_major; 1545 __u32 hw_ip_version_minor; 1546 /** Capabilities */ 1547 __u64 capabilities_flags; 1548 /** command buffer address start alignment*/ 1549 __u32 ib_start_alignment; 1550 /** command buffer size alignment*/ 1551 __u32 ib_size_alignment; 1552 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1553 __u32 available_rings; 1554 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1555 __u32 ip_discovery_version; 1556 /* Userq available slots */ 1557 __u32 userq_num_slots; 1558 }; 1559 1560 struct drm_amdgpu_info_num_handles { 1561 /** Max handles as supported by firmware for UVD */ 1562 __u32 uvd_max_handles; 1563 /** Handles currently in use for UVD */ 1564 __u32 uvd_used_handles; 1565 }; 1566 1567 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1568 1569 struct drm_amdgpu_info_vce_clock_table_entry { 1570 /** System clock */ 1571 __u32 sclk; 1572 /** Memory clock */ 1573 __u32 mclk; 1574 /** VCE clock */ 1575 __u32 eclk; 1576 __u32 pad; 1577 }; 1578 1579 struct drm_amdgpu_info_vce_clock_table { 1580 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1581 __u32 num_valid_entries; 1582 __u32 pad; 1583 }; 1584 1585 /* query video encode/decode caps */ 1586 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1587 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1588 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1589 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1590 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1591 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1592 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1593 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1594 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1595 1596 struct drm_amdgpu_info_video_codec_info { 1597 __u32 valid; 1598 __u32 max_width; 1599 __u32 max_height; 1600 __u32 max_pixels_per_frame; 1601 __u32 max_level; 1602 __u32 pad; 1603 }; 1604 1605 struct drm_amdgpu_info_video_caps { 1606 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1607 }; 1608 1609 #define AMDGPU_VMHUB_TYPE_MASK 0xff 1610 #define AMDGPU_VMHUB_TYPE_SHIFT 0 1611 #define AMDGPU_VMHUB_TYPE_GFX 0 1612 #define AMDGPU_VMHUB_TYPE_MM0 1 1613 #define AMDGPU_VMHUB_TYPE_MM1 2 1614 #define AMDGPU_VMHUB_IDX_MASK 0xff00 1615 #define AMDGPU_VMHUB_IDX_SHIFT 8 1616 1617 struct drm_amdgpu_info_gpuvm_fault { 1618 __u64 addr; 1619 __u32 status; 1620 __u32 vmhub; 1621 }; 1622 1623 struct drm_amdgpu_info_uq_metadata_gfx { 1624 /* shadow area size for gfx11 */ 1625 __u32 shadow_size; 1626 /* shadow area base virtual alignment for gfx11 */ 1627 __u32 shadow_alignment; 1628 /* context save area size for gfx11 */ 1629 __u32 csa_size; 1630 /* context save area base virtual alignment for gfx11 */ 1631 __u32 csa_alignment; 1632 }; 1633 1634 struct drm_amdgpu_info_uq_metadata_compute { 1635 /* EOP size for gfx11 */ 1636 __u32 eop_size; 1637 /* EOP base virtual alignment for gfx11 */ 1638 __u32 eop_alignment; 1639 }; 1640 1641 struct drm_amdgpu_info_uq_metadata_sdma { 1642 /* context save area size for sdma6 */ 1643 __u32 csa_size; 1644 /* context save area base virtual alignment for sdma6 */ 1645 __u32 csa_alignment; 1646 }; 1647 1648 struct drm_amdgpu_info_uq_metadata { 1649 union { 1650 struct drm_amdgpu_info_uq_metadata_gfx gfx; 1651 struct drm_amdgpu_info_uq_metadata_compute compute; 1652 struct drm_amdgpu_info_uq_metadata_sdma sdma; 1653 }; 1654 }; 1655 1656 /* 1657 * Supported GPU families 1658 */ 1659 #define AMDGPU_FAMILY_UNKNOWN 0 1660 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1661 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1662 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1663 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1664 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1665 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1666 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1667 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1668 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1669 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1670 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1671 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1672 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1673 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1674 #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ 1675 #define AMDGPU_FAMILY_GC_11_5_4 154 /* GC 11.5.4 */ 1676 #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ 1677 1678 /* 1679 * Definition of user options 1680 * 1681 * option: AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY 1682 * 0: Disable sigbus delay - SIGBUS will be raised immediately 1683 * 0xFFFFFFFF: SIGBUS will not be raised 1684 * other: Set the sigbus delay in milliseconds 1685 */ 1686 #define AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY 0 1687 1688 #define AMDGPU_PROC_OPTIONS_KFD_SIGBUS_DELAY_DISABLED 0xFFFFFFFFu 1689 1690 struct drm_amdgpu_proc_options { 1691 __u32 op; 1692 struct { 1693 __u32 value; 1694 } kfd_sigbus_delay; 1695 }; 1696 1697 #if defined(__cplusplus) 1698 } 1699 #endif 1700 1701 #endif 1702