1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linearized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 * 98 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 99 * signalling user mode queues. 100 */ 101 #define AMDGPU_GEM_DOMAIN_CPU 0x1 102 #define AMDGPU_GEM_DOMAIN_GTT 0x2 103 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 104 #define AMDGPU_GEM_DOMAIN_GDS 0x8 105 #define AMDGPU_GEM_DOMAIN_GWS 0x10 106 #define AMDGPU_GEM_DOMAIN_OA 0x20 107 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 108 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 109 AMDGPU_GEM_DOMAIN_GTT | \ 110 AMDGPU_GEM_DOMAIN_VRAM | \ 111 AMDGPU_GEM_DOMAIN_GDS | \ 112 AMDGPU_GEM_DOMAIN_GWS | \ 113 AMDGPU_GEM_DOMAIN_OA | \ 114 AMDGPU_GEM_DOMAIN_DOORBELL) 115 116 /* Flag that CPU access will be required for the case of VRAM domain */ 117 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 118 /* Flag that CPU access will not work, this VRAM domain is invisible */ 119 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 120 /* Flag that USWC attributes should be used for GTT */ 121 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 122 /* Flag that the memory should be in VRAM and cleared */ 123 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 124 /* Flag that allocating the BO should use linear VRAM */ 125 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 126 /* Flag that BO is always valid in this VM */ 127 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 128 /* Flag that BO sharing will be explicitly synchronized */ 129 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 130 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 131 * for the second page onward should be set to NC. It should never 132 * be used by user space applications. 133 */ 134 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 135 /* Flag that BO may contain sensitive data that must be wiped before 136 * releasing the memory 137 */ 138 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 139 /* Flag that BO will be encrypted and that the TMZ bit should be 140 * set in the PTEs when mapping this buffer via GPUVM or 141 * accessing it with various hw blocks 142 */ 143 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 144 /* Flag that BO will be used only in preemptible context, which does 145 * not require GTT memory accounting 146 */ 147 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 148 /* Flag that BO can be discarded under memory pressure without keeping the 149 * content. 150 */ 151 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 152 /* Flag that BO is shared coherently between multiple devices or CPU threads. 153 * May depend on GPU instructions to flush caches to system scope explicitly. 154 * 155 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 156 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 157 */ 158 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 159 /* Flag that BO should not be cached by GPU. Coherent without having to flush 160 * GPU caches explicitly 161 * 162 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 163 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 164 */ 165 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 166 /* Flag that BO should be coherent across devices when using device-level 167 * atomics. May depend on GPU instructions to flush caches to device scope 168 * explicitly, promoting them to system scope automatically. 169 * 170 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 171 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 172 */ 173 #define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 174 175 struct drm_amdgpu_gem_create_in { 176 /** the requested memory size */ 177 __u64 bo_size; 178 /** physical start_addr alignment in bytes for some HW requirements */ 179 __u64 alignment; 180 /** the requested memory domains */ 181 __u64 domains; 182 /** allocation flags */ 183 __u64 domain_flags; 184 }; 185 186 struct drm_amdgpu_gem_create_out { 187 /** returned GEM object handle */ 188 __u32 handle; 189 __u32 _pad; 190 }; 191 192 union drm_amdgpu_gem_create { 193 struct drm_amdgpu_gem_create_in in; 194 struct drm_amdgpu_gem_create_out out; 195 }; 196 197 /** Opcode to create new residency list. */ 198 #define AMDGPU_BO_LIST_OP_CREATE 0 199 /** Opcode to destroy previously created residency list */ 200 #define AMDGPU_BO_LIST_OP_DESTROY 1 201 /** Opcode to update resource information in the list */ 202 #define AMDGPU_BO_LIST_OP_UPDATE 2 203 204 struct drm_amdgpu_bo_list_in { 205 /** Type of operation */ 206 __u32 operation; 207 /** Handle of list or 0 if we want to create one */ 208 __u32 list_handle; 209 /** Number of BOs in list */ 210 __u32 bo_number; 211 /** Size of each element describing BO */ 212 __u32 bo_info_size; 213 /** Pointer to array describing BOs */ 214 __u64 bo_info_ptr; 215 }; 216 217 struct drm_amdgpu_bo_list_entry { 218 /** Handle of BO */ 219 __u32 bo_handle; 220 /** New (if specified) BO priority to be used during migration */ 221 __u32 bo_priority; 222 }; 223 224 struct drm_amdgpu_bo_list_out { 225 /** Handle of resource list */ 226 __u32 list_handle; 227 __u32 _pad; 228 }; 229 230 union drm_amdgpu_bo_list { 231 struct drm_amdgpu_bo_list_in in; 232 struct drm_amdgpu_bo_list_out out; 233 }; 234 235 /* context related */ 236 #define AMDGPU_CTX_OP_ALLOC_CTX 1 237 #define AMDGPU_CTX_OP_FREE_CTX 2 238 #define AMDGPU_CTX_OP_QUERY_STATE 3 239 #define AMDGPU_CTX_OP_QUERY_STATE2 4 240 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 241 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 242 243 /* GPU reset status */ 244 #define AMDGPU_CTX_NO_RESET 0 245 /* this the context caused it */ 246 #define AMDGPU_CTX_GUILTY_RESET 1 247 /* some other context caused it */ 248 #define AMDGPU_CTX_INNOCENT_RESET 2 249 /* unknown cause */ 250 #define AMDGPU_CTX_UNKNOWN_RESET 3 251 252 /* indicate gpu reset occurred after ctx created */ 253 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 254 /* indicate vram lost occurred after ctx created */ 255 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 256 /* indicate some job from this context once cause gpu hang */ 257 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 258 /* indicate some errors are detected by RAS */ 259 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 260 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 261 /* indicate that the reset hasn't completed yet */ 262 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 263 264 /* Context priority level */ 265 #define AMDGPU_CTX_PRIORITY_UNSET -2048 266 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 267 #define AMDGPU_CTX_PRIORITY_LOW -512 268 #define AMDGPU_CTX_PRIORITY_NORMAL 0 269 /* 270 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 271 * CAP_SYS_NICE or DRM_MASTER 272 */ 273 #define AMDGPU_CTX_PRIORITY_HIGH 512 274 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 275 276 /* select a stable profiling pstate for perfmon tools */ 277 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 278 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 279 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 280 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 281 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 282 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 283 284 struct drm_amdgpu_ctx_in { 285 /** AMDGPU_CTX_OP_* */ 286 __u32 op; 287 /** Flags */ 288 __u32 flags; 289 __u32 ctx_id; 290 /** AMDGPU_CTX_PRIORITY_* */ 291 __s32 priority; 292 }; 293 294 union drm_amdgpu_ctx_out { 295 struct { 296 __u32 ctx_id; 297 __u32 _pad; 298 } alloc; 299 300 struct { 301 /** For future use, no flags defined so far */ 302 __u64 flags; 303 /** Number of resets caused by this context so far. */ 304 __u32 hangs; 305 /** Reset status since the last call of the ioctl. */ 306 __u32 reset_status; 307 } state; 308 309 struct { 310 __u32 flags; 311 __u32 _pad; 312 } pstate; 313 }; 314 315 union drm_amdgpu_ctx { 316 struct drm_amdgpu_ctx_in in; 317 union drm_amdgpu_ctx_out out; 318 }; 319 320 /* vm ioctl */ 321 #define AMDGPU_VM_OP_RESERVE_VMID 1 322 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 323 324 struct drm_amdgpu_vm_in { 325 /** AMDGPU_VM_OP_* */ 326 __u32 op; 327 __u32 flags; 328 }; 329 330 struct drm_amdgpu_vm_out { 331 /** For future use, no flags defined so far */ 332 __u64 flags; 333 }; 334 335 union drm_amdgpu_vm { 336 struct drm_amdgpu_vm_in in; 337 struct drm_amdgpu_vm_out out; 338 }; 339 340 /* sched ioctl */ 341 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 342 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 343 344 struct drm_amdgpu_sched_in { 345 /* AMDGPU_SCHED_OP_* */ 346 __u32 op; 347 __u32 fd; 348 /** AMDGPU_CTX_PRIORITY_* */ 349 __s32 priority; 350 __u32 ctx_id; 351 }; 352 353 union drm_amdgpu_sched { 354 struct drm_amdgpu_sched_in in; 355 }; 356 357 /* 358 * This is not a reliable API and you should expect it to fail for any 359 * number of reasons and have fallback path that do not use userptr to 360 * perform any operation. 361 */ 362 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 363 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 364 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 365 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 366 367 struct drm_amdgpu_gem_userptr { 368 __u64 addr; 369 __u64 size; 370 /* AMDGPU_GEM_USERPTR_* */ 371 __u32 flags; 372 /* Resulting GEM handle */ 373 __u32 handle; 374 }; 375 376 /* SI-CI-VI: */ 377 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 378 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 379 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 380 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 381 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 382 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 383 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 384 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 385 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 386 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 387 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 388 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 389 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 390 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 391 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 392 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 393 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 394 395 /* GFX9 - GFX11: */ 396 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 397 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 398 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 399 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 400 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 401 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 402 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 403 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 404 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 405 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 406 #define AMDGPU_TILING_SCANOUT_SHIFT 63 407 #define AMDGPU_TILING_SCANOUT_MASK 0x1 408 409 /* GFX12 and later: */ 410 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 411 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 412 /* These are DCC recompression setting for memory management: */ 413 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 414 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ 415 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 416 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ 417 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 418 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 419 420 /* Set/Get helpers for tiling flags. */ 421 #define AMDGPU_TILING_SET(field, value) \ 422 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 423 #define AMDGPU_TILING_GET(value, field) \ 424 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 425 426 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 427 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 428 429 /** The same structure is shared for input/output */ 430 struct drm_amdgpu_gem_metadata { 431 /** GEM Object handle */ 432 __u32 handle; 433 /** Do we want get or set metadata */ 434 __u32 op; 435 struct { 436 /** For future use, no flags defined so far */ 437 __u64 flags; 438 /** family specific tiling info */ 439 __u64 tiling_info; 440 __u32 data_size_bytes; 441 __u32 data[64]; 442 } data; 443 }; 444 445 struct drm_amdgpu_gem_mmap_in { 446 /** the GEM object handle */ 447 __u32 handle; 448 __u32 _pad; 449 }; 450 451 struct drm_amdgpu_gem_mmap_out { 452 /** mmap offset from the vma offset manager */ 453 __u64 addr_ptr; 454 }; 455 456 union drm_amdgpu_gem_mmap { 457 struct drm_amdgpu_gem_mmap_in in; 458 struct drm_amdgpu_gem_mmap_out out; 459 }; 460 461 struct drm_amdgpu_gem_wait_idle_in { 462 /** GEM object handle */ 463 __u32 handle; 464 /** For future use, no flags defined so far */ 465 __u32 flags; 466 /** Absolute timeout to wait */ 467 __u64 timeout; 468 }; 469 470 struct drm_amdgpu_gem_wait_idle_out { 471 /** BO status: 0 - BO is idle, 1 - BO is busy */ 472 __u32 status; 473 /** Returned current memory domain */ 474 __u32 domain; 475 }; 476 477 union drm_amdgpu_gem_wait_idle { 478 struct drm_amdgpu_gem_wait_idle_in in; 479 struct drm_amdgpu_gem_wait_idle_out out; 480 }; 481 482 struct drm_amdgpu_wait_cs_in { 483 /* Command submission handle 484 * handle equals 0 means none to wait for 485 * handle equals ~0ull means wait for the latest sequence number 486 */ 487 __u64 handle; 488 /** Absolute timeout to wait */ 489 __u64 timeout; 490 __u32 ip_type; 491 __u32 ip_instance; 492 __u32 ring; 493 __u32 ctx_id; 494 }; 495 496 struct drm_amdgpu_wait_cs_out { 497 /** CS status: 0 - CS completed, 1 - CS still busy */ 498 __u64 status; 499 }; 500 501 union drm_amdgpu_wait_cs { 502 struct drm_amdgpu_wait_cs_in in; 503 struct drm_amdgpu_wait_cs_out out; 504 }; 505 506 struct drm_amdgpu_fence { 507 __u32 ctx_id; 508 __u32 ip_type; 509 __u32 ip_instance; 510 __u32 ring; 511 __u64 seq_no; 512 }; 513 514 struct drm_amdgpu_wait_fences_in { 515 /** This points to uint64_t * which points to fences */ 516 __u64 fences; 517 __u32 fence_count; 518 __u32 wait_all; 519 __u64 timeout_ns; 520 }; 521 522 struct drm_amdgpu_wait_fences_out { 523 __u32 status; 524 __u32 first_signaled; 525 }; 526 527 union drm_amdgpu_wait_fences { 528 struct drm_amdgpu_wait_fences_in in; 529 struct drm_amdgpu_wait_fences_out out; 530 }; 531 532 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 533 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 534 535 /* Sets or returns a value associated with a buffer. */ 536 struct drm_amdgpu_gem_op { 537 /** GEM object handle */ 538 __u32 handle; 539 /** AMDGPU_GEM_OP_* */ 540 __u32 op; 541 /** Input or return value */ 542 __u64 value; 543 }; 544 545 #define AMDGPU_VA_OP_MAP 1 546 #define AMDGPU_VA_OP_UNMAP 2 547 #define AMDGPU_VA_OP_CLEAR 3 548 #define AMDGPU_VA_OP_REPLACE 4 549 550 /* Delay the page table update till the next CS */ 551 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 552 553 /* Mapping flags */ 554 /* readable mapping */ 555 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 556 /* writable mapping */ 557 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 558 /* executable mapping, new for VI */ 559 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 560 /* partially resident texture */ 561 #define AMDGPU_VM_PAGE_PRT (1 << 4) 562 /* MTYPE flags use bit 5 to 8 */ 563 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 564 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 565 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 566 /* Use Non Coherent MTYPE instead of default MTYPE */ 567 #define AMDGPU_VM_MTYPE_NC (1 << 5) 568 /* Use Write Combine MTYPE instead of default MTYPE */ 569 #define AMDGPU_VM_MTYPE_WC (2 << 5) 570 /* Use Cache Coherent MTYPE instead of default MTYPE */ 571 #define AMDGPU_VM_MTYPE_CC (3 << 5) 572 /* Use UnCached MTYPE instead of default MTYPE */ 573 #define AMDGPU_VM_MTYPE_UC (4 << 5) 574 /* Use Read Write MTYPE instead of default MTYPE */ 575 #define AMDGPU_VM_MTYPE_RW (5 << 5) 576 /* don't allocate MALL */ 577 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 578 579 struct drm_amdgpu_gem_va { 580 /** GEM object handle */ 581 __u32 handle; 582 __u32 _pad; 583 /** AMDGPU_VA_OP_* */ 584 __u32 operation; 585 /** AMDGPU_VM_PAGE_* */ 586 __u32 flags; 587 /** va address to assign . Must be correctly aligned.*/ 588 __u64 va_address; 589 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 590 __u64 offset_in_bo; 591 /** Specify mapping size. Must be correctly aligned. */ 592 __u64 map_size; 593 }; 594 595 #define AMDGPU_HW_IP_GFX 0 596 #define AMDGPU_HW_IP_COMPUTE 1 597 #define AMDGPU_HW_IP_DMA 2 598 #define AMDGPU_HW_IP_UVD 3 599 #define AMDGPU_HW_IP_VCE 4 600 #define AMDGPU_HW_IP_UVD_ENC 5 601 #define AMDGPU_HW_IP_VCN_DEC 6 602 /* 603 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 604 * both encoding and decoding jobs. 605 */ 606 #define AMDGPU_HW_IP_VCN_ENC 7 607 #define AMDGPU_HW_IP_VCN_JPEG 8 608 #define AMDGPU_HW_IP_VPE 9 609 #define AMDGPU_HW_IP_NUM 10 610 611 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 612 613 #define AMDGPU_CHUNK_ID_IB 0x01 614 #define AMDGPU_CHUNK_ID_FENCE 0x02 615 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 616 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 617 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 618 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 619 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 620 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 621 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 622 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 623 624 struct drm_amdgpu_cs_chunk { 625 __u32 chunk_id; 626 __u32 length_dw; 627 __u64 chunk_data; 628 }; 629 630 struct drm_amdgpu_cs_in { 631 /** Rendering context id */ 632 __u32 ctx_id; 633 /** Handle of resource list associated with CS */ 634 __u32 bo_list_handle; 635 __u32 num_chunks; 636 __u32 flags; 637 /** this points to __u64 * which point to cs chunks */ 638 __u64 chunks; 639 }; 640 641 struct drm_amdgpu_cs_out { 642 __u64 handle; 643 }; 644 645 union drm_amdgpu_cs { 646 struct drm_amdgpu_cs_in in; 647 struct drm_amdgpu_cs_out out; 648 }; 649 650 /* Specify flags to be used for IB */ 651 652 /* This IB should be submitted to CE */ 653 #define AMDGPU_IB_FLAG_CE (1<<0) 654 655 /* Preamble flag, which means the IB could be dropped if no context switch */ 656 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 657 658 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 659 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 660 661 /* The IB fence should do the L2 writeback but not invalidate any shader 662 * caches (L2/vL1/sL1/I$). */ 663 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 664 665 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 666 * This will reset wave ID counters for the IB. 667 */ 668 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 669 670 /* Flag the IB as secure (TMZ) 671 */ 672 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 673 674 /* Tell KMD to flush and invalidate caches 675 */ 676 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 677 678 struct drm_amdgpu_cs_chunk_ib { 679 __u32 _pad; 680 /** AMDGPU_IB_FLAG_* */ 681 __u32 flags; 682 /** Virtual address to begin IB execution */ 683 __u64 va_start; 684 /** Size of submission */ 685 __u32 ib_bytes; 686 /** HW IP to submit to */ 687 __u32 ip_type; 688 /** HW IP index of the same type to submit to */ 689 __u32 ip_instance; 690 /** Ring index to submit to */ 691 __u32 ring; 692 }; 693 694 struct drm_amdgpu_cs_chunk_dep { 695 __u32 ip_type; 696 __u32 ip_instance; 697 __u32 ring; 698 __u32 ctx_id; 699 __u64 handle; 700 }; 701 702 struct drm_amdgpu_cs_chunk_fence { 703 __u32 handle; 704 __u32 offset; 705 }; 706 707 struct drm_amdgpu_cs_chunk_sem { 708 __u32 handle; 709 }; 710 711 struct drm_amdgpu_cs_chunk_syncobj { 712 __u32 handle; 713 __u32 flags; 714 __u64 point; 715 }; 716 717 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 718 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 719 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 720 721 union drm_amdgpu_fence_to_handle { 722 struct { 723 struct drm_amdgpu_fence fence; 724 __u32 what; 725 __u32 pad; 726 } in; 727 struct { 728 __u32 handle; 729 } out; 730 }; 731 732 struct drm_amdgpu_cs_chunk_data { 733 union { 734 struct drm_amdgpu_cs_chunk_ib ib_data; 735 struct drm_amdgpu_cs_chunk_fence fence_data; 736 }; 737 }; 738 739 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 740 741 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 742 __u64 shadow_va; 743 __u64 csa_va; 744 __u64 gds_va; 745 __u64 flags; 746 }; 747 748 /* 749 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 750 * 751 */ 752 #define AMDGPU_IDS_FLAGS_FUSION 0x1 753 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 754 #define AMDGPU_IDS_FLAGS_TMZ 0x4 755 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 756 757 /* indicate if acceleration can be working */ 758 #define AMDGPU_INFO_ACCEL_WORKING 0x00 759 /* get the crtc_id from the mode object id? */ 760 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 761 /* query hw IP info */ 762 #define AMDGPU_INFO_HW_IP_INFO 0x02 763 /* query hw IP instance count for the specified type */ 764 #define AMDGPU_INFO_HW_IP_COUNT 0x03 765 /* timestamp for GL_ARB_timer_query */ 766 #define AMDGPU_INFO_TIMESTAMP 0x05 767 /* Query the firmware version */ 768 #define AMDGPU_INFO_FW_VERSION 0x0e 769 /* Subquery id: Query VCE firmware version */ 770 #define AMDGPU_INFO_FW_VCE 0x1 771 /* Subquery id: Query UVD firmware version */ 772 #define AMDGPU_INFO_FW_UVD 0x2 773 /* Subquery id: Query GMC firmware version */ 774 #define AMDGPU_INFO_FW_GMC 0x03 775 /* Subquery id: Query GFX ME firmware version */ 776 #define AMDGPU_INFO_FW_GFX_ME 0x04 777 /* Subquery id: Query GFX PFP firmware version */ 778 #define AMDGPU_INFO_FW_GFX_PFP 0x05 779 /* Subquery id: Query GFX CE firmware version */ 780 #define AMDGPU_INFO_FW_GFX_CE 0x06 781 /* Subquery id: Query GFX RLC firmware version */ 782 #define AMDGPU_INFO_FW_GFX_RLC 0x07 783 /* Subquery id: Query GFX MEC firmware version */ 784 #define AMDGPU_INFO_FW_GFX_MEC 0x08 785 /* Subquery id: Query SMC firmware version */ 786 #define AMDGPU_INFO_FW_SMC 0x0a 787 /* Subquery id: Query SDMA firmware version */ 788 #define AMDGPU_INFO_FW_SDMA 0x0b 789 /* Subquery id: Query PSP SOS firmware version */ 790 #define AMDGPU_INFO_FW_SOS 0x0c 791 /* Subquery id: Query PSP ASD firmware version */ 792 #define AMDGPU_INFO_FW_ASD 0x0d 793 /* Subquery id: Query VCN firmware version */ 794 #define AMDGPU_INFO_FW_VCN 0x0e 795 /* Subquery id: Query GFX RLC SRLC firmware version */ 796 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 797 /* Subquery id: Query GFX RLC SRLG firmware version */ 798 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 799 /* Subquery id: Query GFX RLC SRLS firmware version */ 800 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 801 /* Subquery id: Query DMCU firmware version */ 802 #define AMDGPU_INFO_FW_DMCU 0x12 803 #define AMDGPU_INFO_FW_TA 0x13 804 /* Subquery id: Query DMCUB firmware version */ 805 #define AMDGPU_INFO_FW_DMCUB 0x14 806 /* Subquery id: Query TOC firmware version */ 807 #define AMDGPU_INFO_FW_TOC 0x15 808 /* Subquery id: Query CAP firmware version */ 809 #define AMDGPU_INFO_FW_CAP 0x16 810 /* Subquery id: Query GFX RLCP firmware version */ 811 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 812 /* Subquery id: Query GFX RLCV firmware version */ 813 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 814 /* Subquery id: Query MES_KIQ firmware version */ 815 #define AMDGPU_INFO_FW_MES_KIQ 0x19 816 /* Subquery id: Query MES firmware version */ 817 #define AMDGPU_INFO_FW_MES 0x1a 818 /* Subquery id: Query IMU firmware version */ 819 #define AMDGPU_INFO_FW_IMU 0x1b 820 /* Subquery id: Query VPE firmware version */ 821 #define AMDGPU_INFO_FW_VPE 0x1c 822 823 /* number of bytes moved for TTM migration */ 824 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 825 /* the used VRAM size */ 826 #define AMDGPU_INFO_VRAM_USAGE 0x10 827 /* the used GTT size */ 828 #define AMDGPU_INFO_GTT_USAGE 0x11 829 /* Information about GDS, etc. resource configuration */ 830 #define AMDGPU_INFO_GDS_CONFIG 0x13 831 /* Query information about VRAM and GTT domains */ 832 #define AMDGPU_INFO_VRAM_GTT 0x14 833 /* Query information about register in MMR address space*/ 834 #define AMDGPU_INFO_READ_MMR_REG 0x15 835 /* Query information about device: rev id, family, etc. */ 836 #define AMDGPU_INFO_DEV_INFO 0x16 837 /* visible vram usage */ 838 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 839 /* number of TTM buffer evictions */ 840 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 841 /* Query memory about VRAM and GTT domains */ 842 #define AMDGPU_INFO_MEMORY 0x19 843 /* Query vce clock table */ 844 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 845 /* Query vbios related information */ 846 #define AMDGPU_INFO_VBIOS 0x1B 847 /* Subquery id: Query vbios size */ 848 #define AMDGPU_INFO_VBIOS_SIZE 0x1 849 /* Subquery id: Query vbios image */ 850 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 851 /* Subquery id: Query vbios info */ 852 #define AMDGPU_INFO_VBIOS_INFO 0x3 853 /* Query UVD handles */ 854 #define AMDGPU_INFO_NUM_HANDLES 0x1C 855 /* Query sensor related information */ 856 #define AMDGPU_INFO_SENSOR 0x1D 857 /* Subquery id: Query GPU shader clock */ 858 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 859 /* Subquery id: Query GPU memory clock */ 860 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 861 /* Subquery id: Query GPU temperature */ 862 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 863 /* Subquery id: Query GPU load */ 864 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 865 /* Subquery id: Query average GPU power */ 866 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 867 /* Subquery id: Query northbridge voltage */ 868 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 869 /* Subquery id: Query graphics voltage */ 870 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 871 /* Subquery id: Query GPU stable pstate shader clock */ 872 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 873 /* Subquery id: Query GPU stable pstate memory clock */ 874 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 875 /* Subquery id: Query GPU peak pstate shader clock */ 876 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 877 /* Subquery id: Query GPU peak pstate memory clock */ 878 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 879 /* Subquery id: Query input GPU power */ 880 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 881 /* Number of VRAM page faults on CPU access. */ 882 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 883 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 884 /* query ras mask of enabled features*/ 885 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 886 /* RAS MASK: UMC (VRAM) */ 887 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 888 /* RAS MASK: SDMA */ 889 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 890 /* RAS MASK: GFX */ 891 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 892 /* RAS MASK: MMHUB */ 893 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 894 /* RAS MASK: ATHUB */ 895 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 896 /* RAS MASK: PCIE */ 897 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 898 /* RAS MASK: HDP */ 899 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 900 /* RAS MASK: XGMI */ 901 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 902 /* RAS MASK: DF */ 903 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 904 /* RAS MASK: SMN */ 905 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 906 /* RAS MASK: SEM */ 907 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 908 /* RAS MASK: MP0 */ 909 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 910 /* RAS MASK: MP1 */ 911 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 912 /* RAS MASK: FUSE */ 913 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 914 /* query video encode/decode caps */ 915 #define AMDGPU_INFO_VIDEO_CAPS 0x21 916 /* Subquery id: Decode */ 917 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 918 /* Subquery id: Encode */ 919 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 920 /* Query the max number of IBs per gang per submission */ 921 #define AMDGPU_INFO_MAX_IBS 0x22 922 /* query last page fault info */ 923 #define AMDGPU_INFO_GPUVM_FAULT 0x23 924 925 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 926 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 927 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 928 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 929 930 struct drm_amdgpu_query_fw { 931 /** AMDGPU_INFO_FW_* */ 932 __u32 fw_type; 933 /** 934 * Index of the IP if there are more IPs of 935 * the same type. 936 */ 937 __u32 ip_instance; 938 /** 939 * Index of the engine. Whether this is used depends 940 * on the firmware type. (e.g. MEC, SDMA) 941 */ 942 __u32 index; 943 __u32 _pad; 944 }; 945 946 /* Input structure for the INFO ioctl */ 947 struct drm_amdgpu_info { 948 /* Where the return value will be stored */ 949 __u64 return_pointer; 950 /* The size of the return value. Just like "size" in "snprintf", 951 * it limits how many bytes the kernel can write. */ 952 __u32 return_size; 953 /* The query request id. */ 954 __u32 query; 955 956 union { 957 struct { 958 __u32 id; 959 __u32 _pad; 960 } mode_crtc; 961 962 struct { 963 /** AMDGPU_HW_IP_* */ 964 __u32 type; 965 /** 966 * Index of the IP if there are more IPs of the same 967 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 968 */ 969 __u32 ip_instance; 970 } query_hw_ip; 971 972 struct { 973 __u32 dword_offset; 974 /** number of registers to read */ 975 __u32 count; 976 __u32 instance; 977 /** For future use, no flags defined so far */ 978 __u32 flags; 979 } read_mmr_reg; 980 981 struct drm_amdgpu_query_fw query_fw; 982 983 struct { 984 __u32 type; 985 __u32 offset; 986 } vbios_info; 987 988 struct { 989 __u32 type; 990 } sensor_info; 991 992 struct { 993 __u32 type; 994 } video_cap; 995 }; 996 }; 997 998 struct drm_amdgpu_info_gds { 999 /** GDS GFX partition size */ 1000 __u32 gds_gfx_partition_size; 1001 /** GDS compute partition size */ 1002 __u32 compute_partition_size; 1003 /** total GDS memory size */ 1004 __u32 gds_total_size; 1005 /** GWS size per GFX partition */ 1006 __u32 gws_per_gfx_partition; 1007 /** GSW size per compute partition */ 1008 __u32 gws_per_compute_partition; 1009 /** OA size per GFX partition */ 1010 __u32 oa_per_gfx_partition; 1011 /** OA size per compute partition */ 1012 __u32 oa_per_compute_partition; 1013 __u32 _pad; 1014 }; 1015 1016 struct drm_amdgpu_info_vram_gtt { 1017 __u64 vram_size; 1018 __u64 vram_cpu_accessible_size; 1019 __u64 gtt_size; 1020 }; 1021 1022 struct drm_amdgpu_heap_info { 1023 /** max. physical memory */ 1024 __u64 total_heap_size; 1025 1026 /** Theoretical max. available memory in the given heap */ 1027 __u64 usable_heap_size; 1028 1029 /** 1030 * Number of bytes allocated in the heap. This includes all processes 1031 * and private allocations in the kernel. It changes when new buffers 1032 * are allocated, freed, and moved. It cannot be larger than 1033 * heap_size. 1034 */ 1035 __u64 heap_usage; 1036 1037 /** 1038 * Theoretical possible max. size of buffer which 1039 * could be allocated in the given heap 1040 */ 1041 __u64 max_allocation; 1042 }; 1043 1044 struct drm_amdgpu_memory_info { 1045 struct drm_amdgpu_heap_info vram; 1046 struct drm_amdgpu_heap_info cpu_accessible_vram; 1047 struct drm_amdgpu_heap_info gtt; 1048 }; 1049 1050 struct drm_amdgpu_info_firmware { 1051 __u32 ver; 1052 __u32 feature; 1053 }; 1054 1055 struct drm_amdgpu_info_vbios { 1056 __u8 name[64]; 1057 __u8 vbios_pn[64]; 1058 __u32 version; 1059 __u32 pad; 1060 __u8 vbios_ver_str[32]; 1061 __u8 date[32]; 1062 }; 1063 1064 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 1065 #define AMDGPU_VRAM_TYPE_GDDR1 1 1066 #define AMDGPU_VRAM_TYPE_DDR2 2 1067 #define AMDGPU_VRAM_TYPE_GDDR3 3 1068 #define AMDGPU_VRAM_TYPE_GDDR4 4 1069 #define AMDGPU_VRAM_TYPE_GDDR5 5 1070 #define AMDGPU_VRAM_TYPE_HBM 6 1071 #define AMDGPU_VRAM_TYPE_DDR3 7 1072 #define AMDGPU_VRAM_TYPE_DDR4 8 1073 #define AMDGPU_VRAM_TYPE_GDDR6 9 1074 #define AMDGPU_VRAM_TYPE_DDR5 10 1075 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1076 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1077 1078 struct drm_amdgpu_info_device { 1079 /** PCI Device ID */ 1080 __u32 device_id; 1081 /** Internal chip revision: A0, A1, etc.) */ 1082 __u32 chip_rev; 1083 __u32 external_rev; 1084 /** Revision id in PCI Config space */ 1085 __u32 pci_rev; 1086 __u32 family; 1087 __u32 num_shader_engines; 1088 __u32 num_shader_arrays_per_engine; 1089 /* in KHz */ 1090 __u32 gpu_counter_freq; 1091 __u64 max_engine_clock; 1092 __u64 max_memory_clock; 1093 /* cu information */ 1094 __u32 cu_active_number; 1095 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1096 __u32 cu_ao_mask; 1097 __u32 cu_bitmap[4][4]; 1098 /** Render backend pipe mask. One render backend is CB+DB. */ 1099 __u32 enabled_rb_pipes_mask; 1100 __u32 num_rb_pipes; 1101 __u32 num_hw_gfx_contexts; 1102 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1103 __u32 pcie_gen; 1104 __u64 ids_flags; 1105 /** Starting virtual address for UMDs. */ 1106 __u64 virtual_address_offset; 1107 /** The maximum virtual address */ 1108 __u64 virtual_address_max; 1109 /** Required alignment of virtual addresses. */ 1110 __u32 virtual_address_alignment; 1111 /** Page table entry - fragment size */ 1112 __u32 pte_fragment_size; 1113 __u32 gart_page_size; 1114 /** constant engine ram size*/ 1115 __u32 ce_ram_size; 1116 /** video memory type info*/ 1117 __u32 vram_type; 1118 /** video memory bit width*/ 1119 __u32 vram_bit_width; 1120 /* vce harvesting instance */ 1121 __u32 vce_harvest_config; 1122 /* gfx double offchip LDS buffers */ 1123 __u32 gc_double_offchip_lds_buf; 1124 /* NGG Primitive Buffer */ 1125 __u64 prim_buf_gpu_addr; 1126 /* NGG Position Buffer */ 1127 __u64 pos_buf_gpu_addr; 1128 /* NGG Control Sideband */ 1129 __u64 cntl_sb_buf_gpu_addr; 1130 /* NGG Parameter Cache */ 1131 __u64 param_buf_gpu_addr; 1132 __u32 prim_buf_size; 1133 __u32 pos_buf_size; 1134 __u32 cntl_sb_buf_size; 1135 __u32 param_buf_size; 1136 /* wavefront size*/ 1137 __u32 wave_front_size; 1138 /* shader visible vgprs*/ 1139 __u32 num_shader_visible_vgprs; 1140 /* CU per shader array*/ 1141 __u32 num_cu_per_sh; 1142 /* number of tcc blocks*/ 1143 __u32 num_tcc_blocks; 1144 /* gs vgt table depth*/ 1145 __u32 gs_vgt_table_depth; 1146 /* gs primitive buffer depth*/ 1147 __u32 gs_prim_buffer_depth; 1148 /* max gs wavefront per vgt*/ 1149 __u32 max_gs_waves_per_vgt; 1150 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1151 __u32 pcie_num_lanes; 1152 /* always on cu bitmap */ 1153 __u32 cu_ao_bitmap[4][4]; 1154 /** Starting high virtual address for UMDs. */ 1155 __u64 high_va_offset; 1156 /** The maximum high virtual address */ 1157 __u64 high_va_max; 1158 /* gfx10 pa_sc_tile_steering_override */ 1159 __u32 pa_sc_tile_steering_override; 1160 /* disabled TCCs */ 1161 __u64 tcc_disabled_mask; 1162 __u64 min_engine_clock; 1163 __u64 min_memory_clock; 1164 /* The following fields are only set on gfx11+, older chips set 0. */ 1165 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1166 __u32 num_sqc_per_wgp; 1167 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1168 __u32 sqc_inst_cache_size; 1169 __u32 gl1c_cache_size; 1170 __u32 gl2c_cache_size; 1171 __u64 mall_size; /* AKA infinity cache */ 1172 /* high 32 bits of the rb pipes mask */ 1173 __u32 enabled_rb_pipes_mask_hi; 1174 /* shadow area size for gfx11 */ 1175 __u32 shadow_size; 1176 /* shadow area base virtual alignment for gfx11 */ 1177 __u32 shadow_alignment; 1178 /* context save area size for gfx11 */ 1179 __u32 csa_size; 1180 /* context save area base virtual alignment for gfx11 */ 1181 __u32 csa_alignment; 1182 }; 1183 1184 struct drm_amdgpu_info_hw_ip { 1185 /** Version of h/w IP */ 1186 __u32 hw_ip_version_major; 1187 __u32 hw_ip_version_minor; 1188 /** Capabilities */ 1189 __u64 capabilities_flags; 1190 /** command buffer address start alignment*/ 1191 __u32 ib_start_alignment; 1192 /** command buffer size alignment*/ 1193 __u32 ib_size_alignment; 1194 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1195 __u32 available_rings; 1196 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1197 __u32 ip_discovery_version; 1198 }; 1199 1200 struct drm_amdgpu_info_num_handles { 1201 /** Max handles as supported by firmware for UVD */ 1202 __u32 uvd_max_handles; 1203 /** Handles currently in use for UVD */ 1204 __u32 uvd_used_handles; 1205 }; 1206 1207 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1208 1209 struct drm_amdgpu_info_vce_clock_table_entry { 1210 /** System clock */ 1211 __u32 sclk; 1212 /** Memory clock */ 1213 __u32 mclk; 1214 /** VCE clock */ 1215 __u32 eclk; 1216 __u32 pad; 1217 }; 1218 1219 struct drm_amdgpu_info_vce_clock_table { 1220 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1221 __u32 num_valid_entries; 1222 __u32 pad; 1223 }; 1224 1225 /* query video encode/decode caps */ 1226 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1227 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1228 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1229 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1230 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1231 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1232 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1233 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1234 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1235 1236 struct drm_amdgpu_info_video_codec_info { 1237 __u32 valid; 1238 __u32 max_width; 1239 __u32 max_height; 1240 __u32 max_pixels_per_frame; 1241 __u32 max_level; 1242 __u32 pad; 1243 }; 1244 1245 struct drm_amdgpu_info_video_caps { 1246 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1247 }; 1248 1249 #define AMDGPU_VMHUB_TYPE_MASK 0xff 1250 #define AMDGPU_VMHUB_TYPE_SHIFT 0 1251 #define AMDGPU_VMHUB_TYPE_GFX 0 1252 #define AMDGPU_VMHUB_TYPE_MM0 1 1253 #define AMDGPU_VMHUB_TYPE_MM1 2 1254 #define AMDGPU_VMHUB_IDX_MASK 0xff00 1255 #define AMDGPU_VMHUB_IDX_SHIFT 8 1256 1257 struct drm_amdgpu_info_gpuvm_fault { 1258 __u64 addr; 1259 __u32 status; 1260 __u32 vmhub; 1261 }; 1262 1263 /* 1264 * Supported GPU families 1265 */ 1266 #define AMDGPU_FAMILY_UNKNOWN 0 1267 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1268 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1269 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1270 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1271 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1272 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1273 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1274 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1275 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1276 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1277 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1278 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1279 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1280 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1281 #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ 1282 #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ 1283 1284 #if defined(__cplusplus) 1285 } 1286 #endif 1287 1288 #endif 1289