1 #ifndef __SOUND_EMU10K1_H 2 #define __SOUND_EMU10K1_H 3 4 /* 5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>, 6 * Creative Labs, Inc. 7 * Definitions for EMU10K1 (SB Live!) chips 8 * 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26 #ifdef __KERNEL__ 27 28 #include <sound/pcm.h> 29 #include <sound/rawmidi.h> 30 #include <sound/hwdep.h> 31 #include <sound/ac97_codec.h> 32 #include <sound/util_mem.h> 33 #include <sound/pcm-indirect.h> 34 #include <sound/timer.h> 35 #include <linux/interrupt.h> 36 #include <asm/io.h> 37 38 /* ------------------- DEFINES -------------------- */ 39 40 #define EMUPAGESIZE 4096 41 #define MAXREQVOICES 8 42 #define MAXPAGES 8192 43 #define RESERVED 0 44 #define NUM_MIDI 16 45 #define NUM_G 64 /* use all channels */ 46 #define NUM_FXSENDS 4 47 #define NUM_EFX_PLAYBACK 16 48 49 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */ 50 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */ 51 #define AUDIGY_DMA_MASK 0x7fffffffUL /* 31bit FIXME - 32 should work? */ 52 /* See ALSA bug #1276 - rlrevell */ 53 54 #define TMEMSIZE 256*1024 55 #define TMEMSIZEREG 4 56 57 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL)) 58 59 // Audigy specify registers are prefixed with 'A_' 60 61 /************************************************************************************************/ 62 /* PCI function 0 registers, address = <val> + PCIBASE0 */ 63 /************************************************************************************************/ 64 65 #define PTR 0x00 /* Indexed register set pointer register */ 66 /* NOTE: The CHANNELNUM and ADDRESS words can */ 67 /* be modified independently of each other. */ 68 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */ 69 /* channel number of the register to be */ 70 /* accessed. For non per-channel registers the */ 71 /* value should be set to zero. */ 72 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */ 73 #define A_PTR_ADDRESS_MASK 0x0fff0000 74 75 #define DATA 0x04 /* Indexed register set data register */ 76 77 #define IPR 0x08 /* Global interrupt pending register */ 78 /* Clear pending interrupts by writing a 1 to */ 79 /* the relevant bits and zero to the other bits */ 80 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes 81 to interrupt */ 82 #define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure 83 which INTE bits enable it) */ 84 85 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ 86 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */ 87 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */ 88 89 #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */ 90 #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */ 91 92 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */ 93 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */ 94 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */ 95 #define IPR_PCIERROR 0x00200000 /* PCI bus error */ 96 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */ 97 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */ 98 #define IPR_MUTE 0x00040000 /* Mute button pressed */ 99 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */ 100 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */ 101 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */ 102 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */ 103 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */ 104 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */ 105 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */ 106 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */ 107 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */ 108 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */ 109 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */ 110 #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */ 111 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */ 112 /* highest set channel in CLIPL, CLIPH, HLIPL, */ 113 /* or HLIPH. When IP is written with CL set, */ 114 /* the bit in H/CLIPL or H/CLIPH corresponding */ 115 /* to the CIN value written will be cleared. */ 116 117 #define INTE 0x0c /* Interrupt enable register */ 118 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */ 119 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */ 120 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */ 121 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */ 122 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */ 123 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */ 124 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */ 125 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */ 126 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */ 127 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */ 128 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */ 129 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */ 130 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */ 131 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */ 132 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */ 133 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */ 134 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */ 135 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */ 136 137 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */ 138 /* NOTE: There is no reason to use this under */ 139 /* Linux, and it will cause odd hardware */ 140 /* behavior and possibly random segfaults and */ 141 /* lockups if enabled. */ 142 143 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ 144 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */ 145 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */ 146 147 148 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */ 149 /* NOTE: This bit must always be enabled */ 150 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */ 151 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */ 152 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */ 153 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */ 154 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */ 155 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */ 156 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */ 157 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */ 158 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */ 159 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */ 160 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */ 161 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */ 162 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */ 163 164 #define WC 0x10 /* Wall Clock register */ 165 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */ 166 #define WC_SAMPLECOUNTER 0x14060010 167 #define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */ 168 /* NOTE: Each channel takes 1/64th of a sample */ 169 /* period to be serviced. */ 170 171 #define HCFG 0x14 /* Hardware config register */ 172 /* NOTE: There is no reason to use the legacy */ 173 /* SoundBlaster emulation stuff described below */ 174 /* under Linux, and all kinds of weird hardware */ 175 /* behavior can result if you try. Don't. */ 176 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */ 177 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */ 178 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */ 179 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */ 180 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */ 181 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */ 182 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */ 183 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */ 184 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */ 185 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */ 186 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */ 187 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */ 188 /* NOTE: The rest of the bits in this register */ 189 /* _are_ relevant under Linux. */ 190 #define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */ 191 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */ 192 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */ 193 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */ 194 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */ 195 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */ 196 #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */ 197 #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */ 198 #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */ 199 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */ 200 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */ 201 /* 1 = Force all 3 async digital inputs to use */ 202 /* the same async sample rate tracker (ZVIDEO) */ 203 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */ 204 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */ 205 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */ 206 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */ 207 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */ 208 /* will automatically mute their output when */ 209 /* they are not rate-locked to the external */ 210 /* async audio source */ 211 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */ 212 /* NOTE: This should generally never be used. */ 213 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */ 214 /* NOTE: This should generally never be used. */ 215 #define HCFG_LOCKTANKCACHE 0x01020014 216 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */ 217 /* NOTE: This is a 'cheap' way to implement a */ 218 /* master mute function on the mute button, and */ 219 /* in general should not be used unless a more */ 220 /* sophisticated master mute function has not */ 221 /* been written. */ 222 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */ 223 /* Should be set to 1 when the EMU10K1 is */ 224 /* completely initialized. */ 225 226 //For Audigy, MPU port move to 0x70-0x74 ptr register 227 228 #define MUDATA 0x18 /* MPU401 data register (8 bits) */ 229 230 #define MUCMD 0x19 /* MPU401 command register (8 bits) */ 231 #define MUCMD_RESET 0xff /* RESET command */ 232 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */ 233 /* NOTE: All other commands are ignored */ 234 235 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */ 236 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */ 237 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */ 238 239 #define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */ 240 #define A_GPINPUT_MASK 0xff00 241 #define A_GPOUTPUT_MASK 0x00ff 242 243 // Audigy output/GPIO stuff taken from the kX drivers 244 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */ 245 #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */ 246 #define A_IOCFG_ENABLE_DIGITAL 0x0004 247 #define A_IOCFG_UNKNOWN_20 0x0020 248 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */ 249 #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */ 250 #define A_IOCFG_GPOUT2 0x0001 /* IR */ 251 #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */ 252 /* + digital for generic 10k2 */ 253 #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */ 254 #define A_IOCFG_FRONT_JACK 0x4000 255 #define A_IOCFG_REAR_JACK 0x8000 256 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */ 257 258 /* outputs: 259 * for audigy2 platinum: 0xa00 260 * for a2 platinum ex: 0x1c00 261 * for a1 platinum: 0x0 262 */ 263 264 #define TIMER 0x1a /* Timer terminal count register */ 265 /* NOTE: After the rate is changed, a maximum */ 266 /* of 1024 sample periods should be allowed */ 267 /* before the new rate is guaranteed accurate. */ 268 #define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */ 269 /* 0 == 1024 periods, [1..4] are not useful */ 270 #define TIMER_RATE 0x0a00001a 271 272 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */ 273 274 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */ 275 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */ 276 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */ 277 278 /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */ 279 #define PTR2 0x20 /* Indexed register set pointer register */ 280 #define DATA2 0x24 /* Indexed register set data register */ 281 #define IPR2 0x28 /* P16V interrupt pending register */ 282 #define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ 283 #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ 284 #define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ 285 #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */ 286 /* 0x00000100 Playback. Only in once per period. 287 * 0x00110000 Capture. Int on half buffer. 288 */ 289 #define INTE2 0x2c /* P16V Interrupt enable register. */ 290 #define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ 291 #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ 292 #define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */ 293 #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */ 294 #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */ 295 #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */ 296 #define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */ 297 #define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */ 298 #define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ 299 #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */ 300 #define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */ 301 /* 0x00000000 2-channel output. */ 302 /* 0x00000200 8-channel output. */ 303 /* 0x00000004 pauses stream/irq fail. */ 304 /* Rest of bits no nothing to sound output */ 305 /* bit 0: Enable P16V audio. 306 * bit 1: Lock P16V record memory cache. 307 * bit 2: Lock P16V playback memory cache. 308 * bit 3: Dummy record insert zero samples. 309 * bit 8: Record 8-channel in phase. 310 * bit 9: Playback 8-channel in phase. 311 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute. 312 * bit 13: Playback mixer enable. 313 * bit 14: Route SRC48 mixer output to fx engine. 314 * bit 15: Enable IEEE 1394 chip. 315 */ 316 #define IPR3 0x38 /* Cdif interrupt pending register */ 317 #define INTE3 0x3c /* Cdif interrupt enable register. */ 318 /************************************************************************************************/ 319 /* PCI function 1 registers, address = <val> + PCIBASE1 */ 320 /************************************************************************************************/ 321 322 #define JOYSTICK1 0x00 /* Analog joystick port register */ 323 #define JOYSTICK2 0x01 /* Analog joystick port register */ 324 #define JOYSTICK3 0x02 /* Analog joystick port register */ 325 #define JOYSTICK4 0x03 /* Analog joystick port register */ 326 #define JOYSTICK5 0x04 /* Analog joystick port register */ 327 #define JOYSTICK6 0x05 /* Analog joystick port register */ 328 #define JOYSTICK7 0x06 /* Analog joystick port register */ 329 #define JOYSTICK8 0x07 /* Analog joystick port register */ 330 331 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */ 332 /* When reading, use these bitfields: */ 333 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */ 334 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */ 335 336 337 /********************************************************************************************************/ 338 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */ 339 /********************************************************************************************************/ 340 341 #define CPF 0x00 /* Current pitch and fraction register */ 342 #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */ 343 #define CPF_CURRENTPITCH 0x10100000 344 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */ 345 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */ 346 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */ 347 348 #define PTRX 0x01 /* Pitch target and send A/B amounts register */ 349 #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */ 350 #define PTRX_PITCHTARGET 0x10100001 351 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */ 352 #define PTRX_FXSENDAMOUNT_A 0x08080001 353 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */ 354 #define PTRX_FXSENDAMOUNT_B 0x08000001 355 356 #define CVCF 0x02 /* Current volume and filter cutoff register */ 357 #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */ 358 #define CVCF_CURRENTVOL 0x10100002 359 #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */ 360 #define CVCF_CURRENTFILTER 0x10000002 361 362 #define VTFT 0x03 /* Volume target and filter cutoff target register */ 363 #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */ 364 #define VTFT_VOLUMETARGET 0x10100003 365 #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */ 366 #define VTFT_FILTERTARGET 0x10000003 367 368 #define Z1 0x05 /* Filter delay memory 1 register */ 369 370 #define Z2 0x04 /* Filter delay memory 2 register */ 371 372 #define PSST 0x06 /* Send C amount and loop start address register */ 373 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */ 374 375 #define PSST_FXSENDAMOUNT_C 0x08180006 376 377 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */ 378 #define PSST_LOOPSTARTADDR 0x18000006 379 380 #define DSL 0x07 /* Send D amount and loop start address register */ 381 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */ 382 383 #define DSL_FXSENDAMOUNT_D 0x08180007 384 385 #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */ 386 #define DSL_LOOPENDADDR 0x18000007 387 388 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */ 389 #define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */ 390 #define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */ 391 /* 1 == full band, 7 == lowpass */ 392 /* ROM 0 is used when pitch shifting downward or less */ 393 /* then 3 semitones upward. Increasingly higher ROM */ 394 /* numbers are used, typically in steps of 3 semitones, */ 395 /* as upward pitch shifting is performed. */ 396 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */ 397 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */ 398 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */ 399 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */ 400 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */ 401 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */ 402 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */ 403 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */ 404 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */ 405 #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */ 406 #define CCCA_CURRADDR 0x18000008 407 408 #define CCR 0x09 /* Cache control register */ 409 #define CCR_CACHEINVALIDSIZE 0x07190009 410 #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */ 411 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */ 412 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */ 413 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */ 414 #define CCR_READADDRESS 0x06100009 415 #define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */ 416 #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */ 417 /* NOTE: This is valid only if CACHELOOPFLAG is set */ 418 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */ 419 #define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */ 420 421 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */ 422 /* NOTE: This register is normally not used */ 423 #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */ 424 425 #define FXRT 0x0b /* Effects send routing register */ 426 /* NOTE: It is illegal to assign the same routing to */ 427 /* two effects sends. */ 428 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */ 429 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */ 430 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */ 431 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */ 432 433 #define MAPA 0x0c /* Cache map A */ 434 435 #define MAPB 0x0d /* Cache map B */ 436 437 #define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */ 438 #define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */ 439 440 #define ENVVOL 0x10 /* Volume envelope register */ 441 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ 442 /* 0x8000-n == 666*n usec delay */ 443 444 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */ 445 #define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */ 446 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */ 447 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */ 448 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */ 449 450 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */ 451 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */ 452 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ 453 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */ 454 /* this channel and from writing to pitch, filter and */ 455 /* volume targets. */ 456 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */ 457 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ 458 459 #define LFOVAL1 0x13 /* Modulation LFO value */ 460 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */ 461 /* 0x8000-n == 666*n usec delay */ 462 463 #define ENVVAL 0x14 /* Modulation envelope register */ 464 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */ 465 /* 0x8000-n == 666*n usec delay */ 466 467 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */ 468 #define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */ 469 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */ 470 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */ 471 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */ 472 473 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */ 474 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */ 475 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ 476 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */ 477 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ 478 479 #define LFOVAL2 0x17 /* Vibrato LFO register */ 480 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */ 481 /* 0x8000-n == 666*n usec delay */ 482 483 #define IP 0x18 /* Initial pitch register */ 484 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */ 485 /* 4 bits of octave, 12 bits of fractional octave */ 486 #define IP_UNITY 0x0000e000 /* Unity pitch shift */ 487 488 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */ 489 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */ 490 /* 6 most significant bits are semitones */ 491 /* 2 least significant bits are fractions */ 492 #define IFATN_FILTERCUTOFF 0x08080019 493 #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */ 494 #define IFATN_ATTENUATION 0x08000019 495 496 497 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */ 498 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */ 499 /* Signed 2's complement, +/- one octave peak extremes */ 500 #define PEFE_PITCHAMOUNT 0x0808001a 501 #define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */ 502 /* Signed 2's complement, +/- six octaves peak extremes */ 503 #define PEFE_FILTERAMOUNT 0x0800001a 504 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */ 505 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */ 506 /* Signed 2's complement, +/- one octave extremes */ 507 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */ 508 /* Signed 2's complement, +/- three octave extremes */ 509 510 511 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */ 512 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */ 513 /* Signed 2's complement, with +/- 12dB extremes */ 514 515 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */ 516 /* ??Hz steps, maximum of ?? Hz. */ 517 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */ 518 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */ 519 /* Signed 2's complement, +/- one octave extremes */ 520 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */ 521 /* 0.039Hz steps, maximum of 9.85 Hz. */ 522 523 #define TEMPENV 0x1e /* Tempory envelope register */ 524 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */ 525 /* NOTE: All channels contain internal variables; do */ 526 /* not write to these locations. */ 527 528 /* 1f something */ 529 530 #define CD0 0x20 /* Cache data 0 register */ 531 #define CD1 0x21 /* Cache data 1 register */ 532 #define CD2 0x22 /* Cache data 2 register */ 533 #define CD3 0x23 /* Cache data 3 register */ 534 #define CD4 0x24 /* Cache data 4 register */ 535 #define CD5 0x25 /* Cache data 5 register */ 536 #define CD6 0x26 /* Cache data 6 register */ 537 #define CD7 0x27 /* Cache data 7 register */ 538 #define CD8 0x28 /* Cache data 8 register */ 539 #define CD9 0x29 /* Cache data 9 register */ 540 #define CDA 0x2a /* Cache data A register */ 541 #define CDB 0x2b /* Cache data B register */ 542 #define CDC 0x2c /* Cache data C register */ 543 #define CDD 0x2d /* Cache data D register */ 544 #define CDE 0x2e /* Cache data E register */ 545 #define CDF 0x2f /* Cache data F register */ 546 547 /* 0x30-3f seem to be the same as 0x20-2f */ 548 549 #define PTB 0x40 /* Page table base register */ 550 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */ 551 552 #define TCB 0x41 /* Tank cache base register */ 553 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */ 554 555 #define ADCCR 0x42 /* ADC sample rate/stereo control register */ 556 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */ 557 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */ 558 /* NOTE: To guarantee phase coherency, both channels */ 559 /* must be disabled prior to enabling both channels. */ 560 #define A_ADCCR_RCHANENABLE 0x00000020 561 #define A_ADCCR_LCHANENABLE 0x00000010 562 563 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */ 564 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */ 565 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */ 566 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */ 567 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */ 568 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */ 569 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */ 570 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */ 571 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */ 572 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */ 573 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */ 574 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */ 575 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */ 576 577 #define FXWC 0x43 /* FX output write channels register */ 578 /* When set, each bit enables the writing of the */ 579 /* corresponding FX output channel (internal registers */ 580 /* 0x20-0x3f) to host memory. This mode of recording */ 581 /* is 16bit, 48KHz only. All 32 channels can be enabled */ 582 /* simultaneously. */ 583 584 #define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */ 585 #define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */ 586 #define FXWC_DEFAULTROUTE_A (1<<12) 587 #define FXWC_DEFAULTROUTE_D (1<<13) 588 #define FXWC_ADCLEFT (1<<18) 589 #define FXWC_CDROMSPDIFLEFT (1<<18) 590 #define FXWC_ADCRIGHT (1<<19) 591 #define FXWC_CDROMSPDIFRIGHT (1<<19) 592 #define FXWC_MIC (1<<20) 593 #define FXWC_ZOOMLEFT (1<<20) 594 #define FXWC_ZOOMRIGHT (1<<21) 595 #define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */ 596 #define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */ 597 598 #define TCBS 0x44 /* Tank cache buffer size register */ 599 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */ 600 #define TCBS_BUFFSIZE_16K 0x00000000 601 #define TCBS_BUFFSIZE_32K 0x00000001 602 #define TCBS_BUFFSIZE_64K 0x00000002 603 #define TCBS_BUFFSIZE_128K 0x00000003 604 #define TCBS_BUFFSIZE_256K 0x00000004 605 #define TCBS_BUFFSIZE_512K 0x00000005 606 #define TCBS_BUFFSIZE_1024K 0x00000006 607 #define TCBS_BUFFSIZE_2048K 0x00000007 608 609 #define MICBA 0x45 /* AC97 microphone buffer address register */ 610 #define MICBA_MASK 0xfffff000 /* 20 bit base address */ 611 612 #define ADCBA 0x46 /* ADC buffer address register */ 613 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */ 614 615 #define FXBA 0x47 /* FX Buffer Address */ 616 #define FXBA_MASK 0xfffff000 /* 20 bit base address */ 617 618 /* 0x48 something - word access, defaults to 3f */ 619 620 #define MICBS 0x49 /* Microphone buffer size register */ 621 622 #define ADCBS 0x4a /* ADC buffer size register */ 623 624 #define FXBS 0x4b /* FX buffer size register */ 625 626 /* register: 0x4c..4f: ffff-ffff current amounts, per-channel */ 627 628 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */ 629 #define ADCBS_BUFSIZE_NONE 0x00000000 630 #define ADCBS_BUFSIZE_384 0x00000001 631 #define ADCBS_BUFSIZE_448 0x00000002 632 #define ADCBS_BUFSIZE_512 0x00000003 633 #define ADCBS_BUFSIZE_640 0x00000004 634 #define ADCBS_BUFSIZE_768 0x00000005 635 #define ADCBS_BUFSIZE_896 0x00000006 636 #define ADCBS_BUFSIZE_1024 0x00000007 637 #define ADCBS_BUFSIZE_1280 0x00000008 638 #define ADCBS_BUFSIZE_1536 0x00000009 639 #define ADCBS_BUFSIZE_1792 0x0000000a 640 #define ADCBS_BUFSIZE_2048 0x0000000b 641 #define ADCBS_BUFSIZE_2560 0x0000000c 642 #define ADCBS_BUFSIZE_3072 0x0000000d 643 #define ADCBS_BUFSIZE_3584 0x0000000e 644 #define ADCBS_BUFSIZE_4096 0x0000000f 645 #define ADCBS_BUFSIZE_5120 0x00000010 646 #define ADCBS_BUFSIZE_6144 0x00000011 647 #define ADCBS_BUFSIZE_7168 0x00000012 648 #define ADCBS_BUFSIZE_8192 0x00000013 649 #define ADCBS_BUFSIZE_10240 0x00000014 650 #define ADCBS_BUFSIZE_12288 0x00000015 651 #define ADCBS_BUFSIZE_14366 0x00000016 652 #define ADCBS_BUFSIZE_16384 0x00000017 653 #define ADCBS_BUFSIZE_20480 0x00000018 654 #define ADCBS_BUFSIZE_24576 0x00000019 655 #define ADCBS_BUFSIZE_28672 0x0000001a 656 #define ADCBS_BUFSIZE_32768 0x0000001b 657 #define ADCBS_BUFSIZE_40960 0x0000001c 658 #define ADCBS_BUFSIZE_49152 0x0000001d 659 #define ADCBS_BUFSIZE_57344 0x0000001e 660 #define ADCBS_BUFSIZE_65536 0x0000001f 661 662 663 #define CDCS 0x50 /* CD-ROM digital channel status register */ 664 665 #define GPSCS 0x51 /* General Purpose SPDIF channel status register*/ 666 667 #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ 668 669 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ 670 671 #define A_DBG 0x53 672 #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */ 673 #define A_DBG_ZC 0x40000000 /* zero tram counter */ 674 #define A_DBG_STEP_ADDR 0x000003ff 675 #define A_DBG_SATURATION_OCCURED 0x20000000 676 #define A_DBG_SATURATION_ADDR 0x0ffc0000 677 678 // NOTE: 0x54,55,56: 64-bit 679 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */ 680 681 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */ 682 683 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */ 684 685 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */ 686 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */ 687 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */ 688 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */ 689 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */ 690 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */ 691 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */ 692 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */ 693 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */ 694 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */ 695 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */ 696 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */ 697 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */ 698 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */ 699 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */ 700 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */ 701 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */ 702 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */ 703 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */ 704 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */ 705 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */ 706 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */ 707 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */ 708 709 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */ 710 #define CLIEL 0x58 /* Channel loop interrupt enable low register */ 711 712 #define CLIEH 0x59 /* Channel loop interrupt enable high register */ 713 714 #define CLIPL 0x5a /* Channel loop interrupt pending low register */ 715 716 #define CLIPH 0x5b /* Channel loop interrupt pending high register */ 717 718 #define SOLEL 0x5c /* Stop on loop enable low register */ 719 720 #define SOLEH 0x5d /* Stop on loop enable high register */ 721 722 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */ 723 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */ 724 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */ 725 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */ 726 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */ 727 728 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */ 729 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */ 730 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */ 731 #define AC97SLOT_CNTR 0x10 /* Center enable */ 732 #define AC97SLOT_LFE 0x20 /* LFE enable */ 733 734 // NOTE: 0x60,61,62: 64-bit 735 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */ 736 737 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */ 738 739 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */ 740 /* NOTE: This one has no SPDIFLOCKED field */ 741 /* Assumes sample lock */ 742 743 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */ 744 #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */ 745 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */ 746 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */ 747 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */ 748 749 /* Note that these values can vary +/- by a small amount */ 750 #define SRCS_SPDIFRATE_44 0x0003acd9 751 #define SRCS_SPDIFRATE_48 0x00040000 752 #define SRCS_SPDIFRATE_96 0x00080000 753 754 #define MICIDX 0x63 /* Microphone recording buffer index register */ 755 #define MICIDX_MASK 0x0000ffff /* 16-bit value */ 756 #define MICIDX_IDX 0x10000063 757 758 #define ADCIDX 0x64 /* ADC recording buffer index register */ 759 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */ 760 #define ADCIDX_IDX 0x10000064 761 762 #define A_ADCIDX 0x63 763 #define A_ADCIDX_IDX 0x10000063 764 765 #define A_MICIDX 0x64 766 #define A_MICIDX_IDX 0x10000064 767 768 #define FXIDX 0x65 /* FX recording buffer index register */ 769 #define FXIDX_MASK 0x0000ffff /* 16-bit value */ 770 #define FXIDX_IDX 0x10000065 771 772 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */ 773 #define HLIEL 0x66 /* Channel half loop interrupt enable low register */ 774 775 #define HLIEH 0x67 /* Channel half loop interrupt enable high register */ 776 777 #define HLIPL 0x68 /* Channel half loop interrupt pending low register */ 778 779 #define HLIPH 0x69 /* Channel half loop interrupt pending high register */ 780 781 // 0x6a,6b,6c used for some recording 782 // 0x6d unused 783 // 0x6e,6f - tanktable base / offset 784 785 /* This is the MPU port on the card (via the game port) */ 786 #define A_MUDATA1 0x70 787 #define A_MUCMD1 0x71 788 #define A_MUSTAT1 A_MUCMD1 789 790 /* This is the MPU port on the Audigy Drive */ 791 #define A_MUDATA2 0x72 792 #define A_MUCMD2 0x73 793 #define A_MUSTAT2 A_MUCMD2 794 795 /* The next two are the Audigy equivalent of FXWC */ 796 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */ 797 /* Each bit selects a channel for recording */ 798 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */ 799 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */ 800 801 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */ 802 #define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */ 803 #define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */ 804 #define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */ 805 #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */ 806 #define A_SPDIF_48000 0x00000000 807 #define A_SPDIF_192000 0x00000020 808 #define A_SPDIF_96000 0x00000040 809 #define A_SPDIF_44100 0x00000080 810 811 #define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */ 812 #define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */ 813 #define A_I2S_CAPTURE_192000 0x00000200 814 #define A_I2S_CAPTURE_96000 0x00000400 815 #define A_I2S_CAPTURE_44100 0x00000800 816 817 #define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */ 818 #define A_PCM_48000 0x00000000 819 #define A_PCM_192000 0x00002000 820 #define A_PCM_96000 0x00004000 821 #define A_PCM_44100 0x00008000 822 823 /* 0x77,0x78,0x79 "something i2s-related" - default to 0x01080000 on my audigy 2 ZS --rlrevell */ 824 /* 0x7a, 0x7b - lookup tables */ 825 826 #define A_FXRT2 0x7c 827 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */ 828 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */ 829 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */ 830 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */ 831 832 #define A_SENDAMOUNTS 0x7d 833 #define A_FXSENDAMOUNT_E_MASK 0xFF000000 834 #define A_FXSENDAMOUNT_F_MASK 0x00FF0000 835 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00 836 #define A_FXSENDAMOUNT_H_MASK 0x000000FF 837 /* 0x7c, 0x7e "high bit is used for filtering" */ 838 839 /* The send amounts for this one are the same as used with the emu10k1 */ 840 #define A_FXRT1 0x7e 841 #define A_FXRT_CHANNELA 0x0000003f 842 #define A_FXRT_CHANNELB 0x00003f00 843 #define A_FXRT_CHANNELC 0x003f0000 844 #define A_FXRT_CHANNELD 0x3f000000 845 846 847 /* Each FX general purpose register is 32 bits in length, all bits are used */ 848 #define FXGPREGBASE 0x100 /* FX general purpose registers base */ 849 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */ 850 851 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */ 852 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */ 853 854 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */ 855 /* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */ 856 /* locations are for external TRAM. */ 857 #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */ 858 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */ 859 860 /* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */ 861 #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */ 862 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ 863 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ 864 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ 865 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ 866 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ 867 868 #define MICROCODEBASE 0x400 /* Microcode data base address */ 869 870 /* Each DSP microcode instruction is mapped into 2 doublewords */ 871 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */ 872 #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */ 873 #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */ 874 #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */ 875 #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */ 876 #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */ 877 878 879 /* Audigy Soundcard have a different instruction format */ 880 #define A_MICROCODEBASE 0x600 881 #define A_LOWORD_OPY_MASK 0x000007ff 882 #define A_LOWORD_OPX_MASK 0x007ff000 883 #define A_HIWORD_OPCODE_MASK 0x0f000000 884 #define A_HIWORD_RESULT_MASK 0x007ff000 885 #define A_HIWORD_OPA_MASK 0x000007ff 886 887 888 /* ------------------- STRUCTURES -------------------- */ 889 890 enum { 891 EMU10K1_EFX, 892 EMU10K1_PCM, 893 EMU10K1_SYNTH, 894 EMU10K1_MIDI 895 }; 896 897 struct snd_emu10k1; 898 899 struct snd_emu10k1_voice { 900 struct snd_emu10k1 *emu; 901 int number; 902 unsigned int use: 1, 903 pcm: 1, 904 efx: 1, 905 synth: 1, 906 midi: 1; 907 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); 908 909 struct snd_emu10k1_pcm *epcm; 910 }; 911 912 enum { 913 PLAYBACK_EMUVOICE, 914 PLAYBACK_EFX, 915 CAPTURE_AC97ADC, 916 CAPTURE_AC97MIC, 917 CAPTURE_EFX 918 }; 919 920 struct snd_emu10k1_pcm { 921 struct snd_emu10k1 *emu; 922 int type; 923 struct snd_pcm_substream *substream; 924 struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK]; 925 struct snd_emu10k1_voice *extra; 926 unsigned short running; 927 unsigned short first_ptr; 928 struct snd_util_memblk *memblk; 929 unsigned int start_addr; 930 unsigned int ccca_start_addr; 931 unsigned int capture_ipr; /* interrupt acknowledge mask */ 932 unsigned int capture_inte; /* interrupt enable mask */ 933 unsigned int capture_ba_reg; /* buffer address register */ 934 unsigned int capture_bs_reg; /* buffer size register */ 935 unsigned int capture_idx_reg; /* buffer index register */ 936 unsigned int capture_cr_val; /* control value */ 937 unsigned int capture_cr_val2; /* control value2 (for audigy) */ 938 unsigned int capture_bs_val; /* buffer size value */ 939 unsigned int capture_bufsize; /* buffer size in bytes */ 940 }; 941 942 struct snd_emu10k1_pcm_mixer { 943 /* mono, left, right x 8 sends (4 on emu10k1) */ 944 unsigned char send_routing[3][8]; 945 unsigned char send_volume[3][8]; 946 unsigned short attn[3]; 947 struct snd_emu10k1_pcm *epcm; 948 }; 949 950 #define snd_emu10k1_compose_send_routing(route) \ 951 ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16) 952 953 #define snd_emu10k1_compose_audigy_fxrt1(route) \ 954 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24)) 955 956 #define snd_emu10k1_compose_audigy_fxrt2(route) \ 957 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24)) 958 959 struct snd_emu10k1_memblk { 960 struct snd_util_memblk mem; 961 /* private part */ 962 int first_page, last_page, pages, mapped_page; 963 unsigned int map_locked; 964 struct list_head mapped_link; 965 struct list_head mapped_order_link; 966 }; 967 968 #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1))) 969 970 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16 971 972 struct snd_emu10k1_fx8010_ctl { 973 struct list_head list; /* list link container */ 974 unsigned int vcount; 975 unsigned int count; /* count of GPR (1..16) */ 976 unsigned short gpr[32]; /* GPR number(s) */ 977 unsigned int value[32]; 978 unsigned int min; /* minimum range */ 979 unsigned int max; /* maximum range */ 980 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ 981 struct snd_kcontrol *kcontrol; 982 }; 983 984 typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data); 985 986 struct snd_emu10k1_fx8010_irq { 987 struct snd_emu10k1_fx8010_irq *next; 988 snd_fx8010_irq_handler_t *handler; 989 unsigned short gpr_running; 990 void *private_data; 991 }; 992 993 struct snd_emu10k1_fx8010_pcm { 994 unsigned int valid: 1, 995 opened: 1, 996 active: 1; 997 unsigned int channels; /* 16-bit channels count */ 998 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */ 999 unsigned int buffer_size; /* count of buffered samples */ 1000 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */ 1001 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ 1002 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ 1003 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ 1004 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ 1005 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ 1006 unsigned char etram[32]; /* external TRAM address & data */ 1007 struct snd_pcm_indirect pcm_rec; 1008 unsigned int tram_pos; 1009 unsigned int tram_shift; 1010 struct snd_emu10k1_fx8010_irq *irq; 1011 }; 1012 1013 struct snd_emu10k1_fx8010 { 1014 unsigned short fxbus_mask; /* used FX buses (bitmask) */ 1015 unsigned short extin_mask; /* used external inputs (bitmask) */ 1016 unsigned short extout_mask; /* used external outputs (bitmask) */ 1017 unsigned short pad1; 1018 unsigned int itram_size; /* internal TRAM size in samples */ 1019 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */ 1020 unsigned int dbg; /* FX debugger register */ 1021 unsigned char name[128]; 1022 int gpr_size; /* size of allocated GPR controls */ 1023 int gpr_count; /* count of used kcontrols */ 1024 struct list_head gpr_ctl; /* GPR controls */ 1025 struct semaphore lock; 1026 struct snd_emu10k1_fx8010_pcm pcm[8]; 1027 spinlock_t irq_lock; 1028 struct snd_emu10k1_fx8010_irq *irq_handlers; 1029 }; 1030 1031 #define emu10k1_gpr_ctl(n) list_entry(n, struct snd_emu10k1_fx8010_ctl, list) 1032 1033 struct snd_emu10k1_midi { 1034 struct snd_emu10k1 *emu; 1035 struct snd_rawmidi *rmidi; 1036 struct snd_rawmidi_substream *substream_input; 1037 struct snd_rawmidi_substream *substream_output; 1038 unsigned int midi_mode; 1039 spinlock_t input_lock; 1040 spinlock_t output_lock; 1041 spinlock_t open_lock; 1042 int tx_enable, rx_enable; 1043 int port; 1044 int ipr_tx, ipr_rx; 1045 void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1046 }; 1047 1048 struct snd_emu_chip_details { 1049 u32 vendor; 1050 u32 device; 1051 u32 subsystem; 1052 unsigned char revision; 1053 unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */ 1054 unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */ 1055 unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */ 1056 unsigned char ca0108_chip; /* Audigy 2 Value */ 1057 unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */ 1058 unsigned char ca0151_chip; /* P16V */ 1059 unsigned char spk71; /* Has 7.1 speakers */ 1060 unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */ 1061 unsigned char spdif_bug; /* Has Spdif phasing bug */ 1062 unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ 1063 unsigned char ecard; /* APS EEPROM */ 1064 const char *driver; 1065 const char *name; 1066 const char *id; /* for backward compatibility - can be NULL if not needed */ 1067 }; 1068 1069 struct snd_emu10k1 { 1070 int irq; 1071 1072 unsigned long port; /* I/O port number */ 1073 unsigned int tos_link: 1, /* tos link detected */ 1074 rear_ac97: 1; /* rear channels are on AC'97 */ 1075 /* Contains profile of card capabilities */ 1076 const struct snd_emu_chip_details *card_capabilities; 1077 unsigned int audigy; /* is Audigy? */ 1078 unsigned int revision; /* chip revision */ 1079 unsigned int serial; /* serial number */ 1080 unsigned short model; /* subsystem id */ 1081 unsigned int card_type; /* EMU10K1_CARD_* */ 1082 unsigned int ecard_ctrl; /* ecard control bits */ 1083 unsigned long dma_mask; /* PCI DMA mask */ 1084 int max_cache_pages; /* max memory size / PAGE_SIZE */ 1085 struct snd_dma_buffer silent_page; /* silent page */ 1086 struct snd_dma_buffer ptb_pages; /* page table pages */ 1087 struct snd_dma_device p16v_dma_dev; 1088 struct snd_dma_buffer p16v_buffer; 1089 1090 struct snd_util_memhdr *memhdr; /* page allocation list */ 1091 struct snd_emu10k1_memblk *reserved_page; /* reserved page */ 1092 1093 struct list_head mapped_link_head; 1094 struct list_head mapped_order_link_head; 1095 void **page_ptr_table; 1096 unsigned long *page_addr_table; 1097 spinlock_t memblk_lock; 1098 1099 unsigned int spdif_bits[3]; /* s/pdif out setup */ 1100 1101 struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */ 1102 int gpr_base; 1103 1104 struct snd_ac97 *ac97; 1105 1106 struct pci_dev *pci; 1107 struct snd_card *card; 1108 struct snd_pcm *pcm; 1109 struct snd_pcm *pcm_mic; 1110 struct snd_pcm *pcm_efx; 1111 struct snd_pcm *pcm_p16v; 1112 1113 spinlock_t synth_lock; 1114 void *synth; 1115 int (*get_synth_voice)(struct snd_emu10k1 *emu); 1116 1117 spinlock_t reg_lock; 1118 spinlock_t emu_lock; 1119 spinlock_t voice_lock; 1120 struct semaphore ptb_lock; 1121 1122 struct snd_emu10k1_voice voices[NUM_G]; 1123 struct snd_emu10k1_voice p16v_voices[4]; 1124 struct snd_emu10k1_voice p16v_capture_voice; 1125 int p16v_device_offset; 1126 u32 p16v_capture_source; 1127 u32 p16v_capture_channel; 1128 struct snd_emu10k1_pcm_mixer pcm_mixer[32]; 1129 struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK]; 1130 struct snd_kcontrol *ctl_send_routing; 1131 struct snd_kcontrol *ctl_send_volume; 1132 struct snd_kcontrol *ctl_attn; 1133 struct snd_kcontrol *ctl_efx_send_routing; 1134 struct snd_kcontrol *ctl_efx_send_volume; 1135 struct snd_kcontrol *ctl_efx_attn; 1136 1137 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1138 void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1139 void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1140 void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1141 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status); 1142 void (*dsp_interrupt)(struct snd_emu10k1 *emu); 1143 1144 struct snd_pcm_substream *pcm_capture_substream; 1145 struct snd_pcm_substream *pcm_capture_mic_substream; 1146 struct snd_pcm_substream *pcm_capture_efx_substream; 1147 struct snd_pcm_substream *pcm_playback_efx_substream; 1148 1149 struct snd_timer *timer; 1150 1151 struct snd_emu10k1_midi midi; 1152 struct snd_emu10k1_midi midi2; /* for audigy */ 1153 1154 unsigned int efx_voices_mask[2]; 1155 unsigned int next_free_voice; 1156 }; 1157 1158 int snd_emu10k1_create(struct snd_card *card, 1159 struct pci_dev *pci, 1160 unsigned short extin_mask, 1161 unsigned short extout_mask, 1162 long max_cache_bytes, 1163 int enable_ir, 1164 uint subsystem, 1165 struct snd_emu10k1 ** remu); 1166 1167 int snd_emu10k1_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1168 int snd_emu10k1_pcm_mic(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1169 int snd_emu10k1_pcm_efx(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1170 int snd_p16v_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1171 int snd_p16v_free(struct snd_emu10k1 * emu); 1172 int snd_p16v_mixer(struct snd_emu10k1 * emu); 1173 int snd_emu10k1_pcm_multi(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1174 int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm); 1175 int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device); 1176 int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device); 1177 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep); 1178 1179 irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id, struct pt_regs *regs); 1180 1181 /* initialization */ 1182 void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice); 1183 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu); 1184 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu); 1185 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size); 1186 1187 /* I/O functions */ 1188 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); 1189 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); 1190 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); 1191 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); 1192 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc); 1193 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb); 1194 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb); 1195 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); 1196 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); 1197 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); 1198 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); 1199 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); 1200 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); 1201 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); 1202 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); 1203 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait); 1204 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; } 1205 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg); 1206 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data); 1207 unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate); 1208 1209 /* memory allocation */ 1210 struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream); 1211 int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); 1212 struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size); 1213 int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); 1214 int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size); 1215 int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size); 1216 int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk); 1217 1218 /* voice allocation */ 1219 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice); 1220 int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); 1221 1222 /* MIDI uart */ 1223 int snd_emu10k1_midi(struct snd_emu10k1 * emu); 1224 int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu); 1225 1226 /* proc interface */ 1227 int snd_emu10k1_proc_init(struct snd_emu10k1 * emu); 1228 1229 /* fx8010 irq handler */ 1230 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu, 1231 snd_fx8010_irq_handler_t *handler, 1232 unsigned char gpr_running, 1233 void *private_data, 1234 struct snd_emu10k1_fx8010_irq **r_irq); 1235 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, 1236 struct snd_emu10k1_fx8010_irq *irq); 1237 1238 #endif /* __KERNEL__ */ 1239 1240 /* 1241 * ---- FX8010 ---- 1242 */ 1243 1244 #define EMU10K1_CARD_CREATIVE 0x00000000 1245 #define EMU10K1_CARD_EMUAPS 0x00000001 1246 1247 #define EMU10K1_FX8010_PCM_COUNT 8 1248 1249 /* instruction set */ 1250 #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */ 1251 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */ 1252 #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */ 1253 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */ 1254 #define iMACINT0 0x04 /* R = A + X * Y ; saturation */ 1255 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */ 1256 #define iACC3 0x06 /* R = A + X + Y ; saturation */ 1257 #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */ 1258 #define iANDXOR 0x08 /* R = (A & X) ^ Y */ 1259 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */ 1260 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */ 1261 #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */ 1262 #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */ 1263 #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */ 1264 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */ 1265 #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */ 1266 1267 /* GPRs */ 1268 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */ 1269 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */ 1270 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */ 1271 #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */ 1272 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */ 1273 1274 #define C_00000000 0x40 1275 #define C_00000001 0x41 1276 #define C_00000002 0x42 1277 #define C_00000003 0x43 1278 #define C_00000004 0x44 1279 #define C_00000008 0x45 1280 #define C_00000010 0x46 1281 #define C_00000020 0x47 1282 #define C_00000100 0x48 1283 #define C_00010000 0x49 1284 #define C_00080000 0x4a 1285 #define C_10000000 0x4b 1286 #define C_20000000 0x4c 1287 #define C_40000000 0x4d 1288 #define C_80000000 0x4e 1289 #define C_7fffffff 0x4f 1290 #define C_ffffffff 0x50 1291 #define C_fffffffe 0x51 1292 #define C_c0000000 0x52 1293 #define C_4f1bbcdc 0x53 1294 #define C_5a7ef9db 0x54 1295 #define C_00100000 0x55 /* ?? */ 1296 #define GPR_ACCU 0x56 /* ACCUM, accumulator */ 1297 #define GPR_COND 0x57 /* CCR, condition register */ 1298 #define GPR_NOISE0 0x58 /* noise source */ 1299 #define GPR_NOISE1 0x59 /* noise source */ 1300 #define GPR_IRQ 0x5a /* IRQ register */ 1301 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */ 1302 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */ 1303 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ 1304 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ 1305 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ 1306 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ 1307 1308 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 1309 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 1310 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 1311 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 1312 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 1313 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 1314 1315 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */ 1316 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */ 1317 #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */ 1318 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */ 1319 #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */ 1320 #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */ 1321 #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */ 1322 #define A_GPR(x) (A_FXGPREGBASE + (x)) 1323 1324 /* cc_reg constants */ 1325 #define CC_REG_NORMALIZED C_00000001 1326 #define CC_REG_BORROW C_00000002 1327 #define CC_REG_MINUS C_00000004 1328 #define CC_REG_ZERO C_00000008 1329 #define CC_REG_SATURATE C_00000010 1330 #define CC_REG_NONZERO C_00000100 1331 1332 /* FX buses */ 1333 #define FXBUS_PCM_LEFT 0x00 1334 #define FXBUS_PCM_RIGHT 0x01 1335 #define FXBUS_PCM_LEFT_REAR 0x02 1336 #define FXBUS_PCM_RIGHT_REAR 0x03 1337 #define FXBUS_MIDI_LEFT 0x04 1338 #define FXBUS_MIDI_RIGHT 0x05 1339 #define FXBUS_PCM_CENTER 0x06 1340 #define FXBUS_PCM_LFE 0x07 1341 #define FXBUS_PCM_LEFT_FRONT 0x08 1342 #define FXBUS_PCM_RIGHT_FRONT 0x09 1343 #define FXBUS_MIDI_REVERB 0x0c 1344 #define FXBUS_MIDI_CHORUS 0x0d 1345 #define FXBUS_PCM_LEFT_SIDE 0x0e 1346 #define FXBUS_PCM_RIGHT_SIDE 0x0f 1347 #define FXBUS_PT_LEFT 0x14 1348 #define FXBUS_PT_RIGHT 0x15 1349 1350 /* Inputs */ 1351 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ 1352 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ 1353 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */ 1354 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */ 1355 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */ 1356 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */ 1357 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */ 1358 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */ 1359 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */ 1360 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */ 1361 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */ 1362 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */ 1363 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */ 1364 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */ 1365 1366 /* Outputs */ 1367 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */ 1368 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */ 1369 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */ 1370 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */ 1371 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */ 1372 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */ 1373 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */ 1374 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */ 1375 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */ 1376 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */ 1377 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */ 1378 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */ 1379 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */ 1380 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */ 1381 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */ 1382 #define EXTOUT_ACENTER 0x11 /* Analog Center */ 1383 #define EXTOUT_ALFE 0x12 /* Analog LFE */ 1384 1385 /* Audigy Inputs */ 1386 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ 1387 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ 1388 #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */ 1389 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */ 1390 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */ 1391 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */ 1392 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */ 1393 #define A_EXTIN_LINE2_R 0x09 /* right */ 1394 #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */ 1395 #define A_EXTIN_ADC_R 0x0b /* right */ 1396 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */ 1397 #define A_EXTIN_AUX2_R 0x0d /* - right */ 1398 1399 /* Audigiy Outputs */ 1400 #define A_EXTOUT_FRONT_L 0x00 /* digital front left */ 1401 #define A_EXTOUT_FRONT_R 0x01 /* right */ 1402 #define A_EXTOUT_CENTER 0x02 /* digital front center */ 1403 #define A_EXTOUT_LFE 0x03 /* digital front lfe */ 1404 #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */ 1405 #define A_EXTOUT_HEADPHONE_R 0x05 /* right */ 1406 #define A_EXTOUT_REAR_L 0x06 /* digital rear left */ 1407 #define A_EXTOUT_REAR_R 0x07 /* right */ 1408 #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */ 1409 #define A_EXTOUT_AFRONT_R 0x09 /* right */ 1410 #define A_EXTOUT_ACENTER 0x0a /* analog center */ 1411 #define A_EXTOUT_ALFE 0x0b /* analog LFE */ 1412 #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */ 1413 #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */ 1414 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */ 1415 #define A_EXTOUT_AREAR_R 0x0f /* right */ 1416 #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */ 1417 #define A_EXTOUT_AC97_R 0x11 /* right */ 1418 #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */ 1419 #define A_EXTOUT_ADC_CAP_R 0x17 /* right */ 1420 #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */ 1421 1422 /* Audigy constants */ 1423 #define A_C_00000000 0xc0 1424 #define A_C_00000001 0xc1 1425 #define A_C_00000002 0xc2 1426 #define A_C_00000003 0xc3 1427 #define A_C_00000004 0xc4 1428 #define A_C_00000008 0xc5 1429 #define A_C_00000010 0xc6 1430 #define A_C_00000020 0xc7 1431 #define A_C_00000100 0xc8 1432 #define A_C_00010000 0xc9 1433 #define A_C_00000800 0xca 1434 #define A_C_10000000 0xcb 1435 #define A_C_20000000 0xcc 1436 #define A_C_40000000 0xcd 1437 #define A_C_80000000 0xce 1438 #define A_C_7fffffff 0xcf 1439 #define A_C_ffffffff 0xd0 1440 #define A_C_fffffffe 0xd1 1441 #define A_C_c0000000 0xd2 1442 #define A_C_4f1bbcdc 0xd3 1443 #define A_C_5a7ef9db 0xd4 1444 #define A_C_00100000 0xd5 1445 #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */ 1446 #define A_GPR_COND 0xd7 /* CCR, condition register */ 1447 #define A_GPR_NOISE0 0xd8 /* noise source */ 1448 #define A_GPR_NOISE1 0xd9 /* noise source */ 1449 #define A_GPR_IRQ 0xda /* IRQ register */ 1450 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */ 1451 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */ 1452 1453 /* definitions for debug register */ 1454 #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */ 1455 #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */ 1456 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */ 1457 #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */ 1458 #define EMU10K1_DBG_STEP 0x00004000 /* start single step */ 1459 #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */ 1460 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */ 1461 1462 /* tank memory address line */ 1463 #ifndef __KERNEL__ 1464 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ 1465 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ 1466 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ 1467 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ 1468 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ 1469 #endif 1470 1471 struct snd_emu10k1_fx8010_info { 1472 unsigned int internal_tram_size; /* in samples */ 1473 unsigned int external_tram_size; /* in samples */ 1474 char fxbus_names[16][32]; /* names of FXBUSes */ 1475 char extin_names[16][32]; /* names of external inputs */ 1476 char extout_names[32][32]; /* names of external outputs */ 1477 unsigned int gpr_controls; /* count of GPR controls */ 1478 }; 1479 1480 #define EMU10K1_GPR_TRANSLATION_NONE 0 1481 #define EMU10K1_GPR_TRANSLATION_TABLE100 1 1482 #define EMU10K1_GPR_TRANSLATION_BASS 2 1483 #define EMU10K1_GPR_TRANSLATION_TREBLE 3 1484 #define EMU10K1_GPR_TRANSLATION_ONOFF 4 1485 1486 struct snd_emu10k1_fx8010_control_gpr { 1487 struct snd_ctl_elem_id id; /* full control ID definition */ 1488 unsigned int vcount; /* visible count */ 1489 unsigned int count; /* count of GPR (1..16) */ 1490 unsigned short gpr[32]; /* GPR number(s) */ 1491 unsigned int value[32]; /* initial values */ 1492 unsigned int min; /* minimum range */ 1493 unsigned int max; /* maximum range */ 1494 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ 1495 }; 1496 1497 struct snd_emu10k1_fx8010_code { 1498 char name[128]; 1499 1500 DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */ 1501 u_int32_t __user *gpr_map; /* initializers */ 1502 1503 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */ 1504 struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls; /* GPR controls to add/replace */ 1505 1506 unsigned int gpr_del_control_count; /* count of GPR controls to remove */ 1507 struct snd_ctl_elem_id __user *gpr_del_controls; /* IDs of GPR controls to remove */ 1508 1509 unsigned int gpr_list_control_count; /* count of GPR controls to list */ 1510 unsigned int gpr_list_control_total; /* total count of GPR controls */ 1511 struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls; /* listed GPR controls */ 1512 1513 DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */ 1514 u_int32_t __user *tram_data_map; /* data initializers */ 1515 u_int32_t __user *tram_addr_map; /* map initializers */ 1516 1517 DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */ 1518 u_int32_t __user *code; /* one instruction - 64 bits */ 1519 }; 1520 1521 struct snd_emu10k1_fx8010_tram { 1522 unsigned int address; /* 31.bit == 1 -> external TRAM */ 1523 unsigned int size; /* size in samples (4 bytes) */ 1524 unsigned int *samples; /* pointer to samples (20-bit) */ 1525 /* NULL->clear memory */ 1526 }; 1527 1528 struct snd_emu10k1_fx8010_pcm_rec { 1529 unsigned int substream; /* substream number */ 1530 unsigned int res1; /* reserved */ 1531 unsigned int channels; /* 16-bit channels count, zero = remove this substream */ 1532 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */ 1533 unsigned int buffer_size; /* count of buffered samples */ 1534 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */ 1535 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ 1536 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ 1537 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ 1538 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ 1539 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ 1540 unsigned char pad; /* reserved */ 1541 unsigned char etram[32]; /* external TRAM address & data (one per channel) */ 1542 unsigned int res2; /* reserved */ 1543 }; 1544 1545 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info) 1546 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code) 1547 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code) 1548 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int) 1549 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram) 1550 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram) 1551 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec) 1552 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec) 1553 #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80) 1554 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81) 1555 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82) 1556 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int) 1557 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int) 1558 1559 /* typedefs for compatibility to user-space */ 1560 typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t; 1561 typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t; 1562 typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t; 1563 typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t; 1564 typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t; 1565 1566 #endif /* __SOUND_EMU10K1_H */ 1567