1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Common definitions for Cirrus Logic CS35L56 smart amp 4 * 5 * Copyright (C) 2023 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 */ 8 9 #ifndef __CS35L56_H 10 #define __CS35L56_H 11 12 #include <linux/bits.h> 13 #include <linux/debugfs.h> 14 #include <linux/firmware/cirrus/cs_dsp.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/regmap.h> 17 #include <linux/spi/spi.h> 18 #include <sound/cs-amp-lib.h> 19 20 struct snd_ctl_elem_value; 21 22 #define CS35L56_DEVID 0x0000000 23 #define CS35L56_REVID 0x0000004 24 #define CS35L56_RELID 0x000000C 25 #define CS35L56_OTPID 0x0000010 26 #define CS35L56_SFT_RESET 0x0000020 27 #define CS35L56_GLOBAL_ENABLES 0x0002014 28 #define CS35L56_BLOCK_ENABLES 0x0002018 29 #define CS35L56_BLOCK_ENABLES2 0x000201C 30 #define CS35L56_SYNC_GPIO1_CFG 0x0002410 31 #define CS35L56_ASP2_DIO_GPIO13_CFG 0x0002440 32 #define CS35L56_UPDATE_REGS 0x0002A0C 33 #define CS35L56_REFCLK_INPUT 0x0002C04 34 #define CS35L56_GLOBAL_SAMPLE_RATE 0x0002C0C 35 #define CS35L56_OTP_MEM_53 0x00300D4 36 #define CS35L56_OTP_MEM_54 0x00300D8 37 #define CS35L56_OTP_MEM_55 0x00300DC 38 #define CS35L56_ASP1_ENABLES1 0x0004800 39 #define CS35L56_ASP1_CONTROL1 0x0004804 40 #define CS35L56_ASP1_CONTROL2 0x0004808 41 #define CS35L56_ASP1_CONTROL3 0x000480C 42 #define CS35L56_ASP1_FRAME_CONTROL1 0x0004810 43 #define CS35L56_ASP1_FRAME_CONTROL5 0x0004820 44 #define CS35L56_ASP1_DATA_CONTROL1 0x0004830 45 #define CS35L56_ASP1_DATA_CONTROL5 0x0004840 46 #define CS35L56_DACPCM1_INPUT 0x0004C00 47 #define CS35L56_DACPCM2_INPUT 0x0004C08 48 #define CS35L56_ASP1TX1_INPUT 0x0004C20 49 #define CS35L56_ASP1TX2_INPUT 0x0004C24 50 #define CS35L56_ASP1TX3_INPUT 0x0004C28 51 #define CS35L56_ASP1TX4_INPUT 0x0004C2C 52 #define CS35L56_DSP1RX1_INPUT 0x0004C40 53 #define CS35L56_DSP1RX2_INPUT 0x0004C44 54 #define CS35L56_SWIRE_DP3_CH1_INPUT 0x0004C70 55 #define CS35L56_SWIRE_DP3_CH2_INPUT 0x0004C74 56 #define CS35L56_SWIRE_DP3_CH3_INPUT 0x0004C78 57 #define CS35L56_SWIRE_DP3_CH4_INPUT 0x0004C7C 58 #define CS35L56_IRQ1_CFG 0x000E000 59 #define CS35L56_IRQ1_STATUS 0x000E004 60 #define CS35L56_IRQ1_EINT_1 0x000E010 61 #define CS35L56_IRQ1_EINT_2 0x000E014 62 #define CS35L56_IRQ1_EINT_4 0x000E01C 63 #define CS35L56_IRQ1_EINT_8 0x000E02C 64 #define CS35L56_IRQ1_EINT_18 0x000E054 65 #define CS35L56_IRQ1_EINT_20 0x000E05C 66 #define CS35L56_IRQ1_MASK_1 0x000E090 67 #define CS35L56_IRQ1_MASK_2 0x000E094 68 #define CS35L56_IRQ1_MASK_4 0x000E09C 69 #define CS35L56_IRQ1_MASK_8 0x000E0AC 70 #define CS35L56_IRQ1_MASK_18 0x000E0D4 71 #define CS35L56_IRQ1_MASK_20 0x000E0DC 72 #define CS35L56_GPIO_STATUS1 0x000F000 73 #define CS35L56_GPIO1_CTRL1 0x000F008 74 #define CS35L56_GPIO13_CTRL1 0x000F038 75 #define CS35L56_MIXER_NGATE_CH1_CFG 0x0010004 76 #define CS35L56_MIXER_NGATE_CH2_CFG 0x0010008 77 #define CS35L56_DSP_MBOX_1_RAW 0x0011000 78 #define CS35L56_DSP_VIRTUAL1_MBOX_1 0x0011020 79 #define CS35L56_DSP_VIRTUAL1_MBOX_2 0x0011024 80 #define CS35L56_DSP_VIRTUAL1_MBOX_3 0x0011028 81 #define CS35L56_DSP_VIRTUAL1_MBOX_4 0x001102C 82 #define CS35L56_DSP_VIRTUAL1_MBOX_5 0x0011030 83 #define CS35L56_DSP_VIRTUAL1_MBOX_6 0x0011034 84 #define CS35L56_DSP_VIRTUAL1_MBOX_7 0x0011038 85 #define CS35L56_DSP_VIRTUAL1_MBOX_8 0x001103C 86 #define CS35L56_DIE_STS1 0x0017040 87 #define CS35L56_DIE_STS2 0x0017044 88 #define CS35L56_DSP_RESTRICT_STS1 0x00190F0 89 #define CS35L56_DSP1_XMEM_PACKED_0 0x2000000 90 #define CS35L56_DSP1_XMEM_PACKED_6143 0x2005FFC 91 #define CS35L56_DSP1_XMEM_UNPACKED32_0 0x2400000 92 #define CS35L56_DSP1_XMEM_UNPACKED32_4095 0x2403FFC 93 #define CS35L56_DSP1_SYS_INFO_ID 0x25E0000 94 #define CS35L56_DSP1_SYS_INFO_END 0x25E004C 95 #define CS35L56_DSP1_AHBM_WINDOW_DEBUG_0 0x25E2040 96 #define CS35L56_DSP1_AHBM_WINDOW_DEBUG_1 0x25E2044 97 #define CS35L56_DSP1_XMEM_UNPACKED24_0 0x2800000 98 #define CS35L56_DSP1_FW_VER 0x2800010 99 #define CS35L56_DSP1_HALO_STATE 0x28021E0 100 #define CS35L56_B2_DSP1_HALO_STATE 0x2803D20 101 #define CS35L56_DSP1_PM_CUR_STATE 0x2804308 102 #define CS35L56_B2_DSP1_PM_CUR_STATE 0x2804678 103 #define CS35L56_DSP1_XMEM_UNPACKED24_8191 0x2807FFC 104 #define CS35L56_DSP1_CORE_BASE 0x2B80000 105 #define CS35L56_DSP1_SCRATCH1 0x2B805C0 106 #define CS35L56_DSP1_SCRATCH2 0x2B805C8 107 #define CS35L56_DSP1_SCRATCH3 0x2B805D0 108 #define CS35L56_DSP1_SCRATCH4 0x2B805D8 109 #define CS35L56_DSP1_YMEM_PACKED_0 0x2C00000 110 #define CS35L56_DSP1_YMEM_PACKED_4604 0x2C047F0 111 #define CS35L56_DSP1_YMEM_UNPACKED32_0 0x3000000 112 #define CS35L56_DSP1_YMEM_UNPACKED32_3070 0x3002FF8 113 #define CS35L56_DSP1_YMEM_UNPACKED24_0 0x3400000 114 #define CS35L56_MAIN_RENDER_USER_MUTE 0x3400024 115 #define CS35L56_MAIN_RENDER_USER_VOLUME 0x340002C 116 #define CS35L56_MAIN_POSTURE_NUMBER 0x3400094 117 #define CS35L56_PROTECTION_STATUS 0x34000D8 118 #define CS35L56_TRANSDUCER_ACTUAL_PS 0x3400150 119 #define CS35L56_DSP1_YMEM_UNPACKED24_6141 0x3405FF4 120 #define CS35L56_DSP1_PMEM_0 0x3800000 121 #define CS35L56_DSP1_PMEM_5114 0x3804FE8 122 123 #define CS35L63_DSP1_FW_VER CS35L56_DSP1_FW_VER 124 #define CS35L63_DSP1_HALO_STATE 0x2803C04 125 #define CS35L63_DSP1_PM_CUR_STATE 0x2804518 126 #define CS35L63_PROTECTION_STATUS 0x340009C 127 #define CS35L63_TRANSDUCER_ACTUAL_PS 0x34000F4 128 #define CS35L63_MAIN_RENDER_USER_MUTE 0x3400020 129 #define CS35L63_MAIN_RENDER_USER_VOLUME 0x3400028 130 #define CS35L63_MAIN_POSTURE_NUMBER 0x3400068 131 132 /* DEVID */ 133 #define CS35L56_DEVID_MASK 0x00FFFFFF 134 135 /* REVID */ 136 #define CS35L56_AREVID_MASK 0x000000F0 137 #define CS35L56_MTLREVID_MASK 0x0000000F 138 #define CS35L56_REVID_B0 0x000000B0 139 140 /* PAD_INTF */ 141 #define CS35L56_PAD_GPIO_PULL_MASK GENMASK(3, 2) 142 #define CS35L56_PAD_GPIO_IE BIT(0) 143 144 #define CS35L56_PAD_PULL_NONE 0 145 #define CS35L56_PAD_PULL_UP 1 146 #define CS35L56_PAD_PULL_DOWN 2 147 148 /* UPDATE_REGS */ 149 #define CS35L56_UPDT_GPIO_PRES BIT(6) 150 151 /* ASP_ENABLES1 */ 152 #define CS35L56_ASP_RX2_EN_SHIFT 17 153 #define CS35L56_ASP_RX1_EN_SHIFT 16 154 #define CS35L56_ASP_TX4_EN_SHIFT 3 155 #define CS35L56_ASP_TX3_EN_SHIFT 2 156 #define CS35L56_ASP_TX2_EN_SHIFT 1 157 #define CS35L56_ASP_TX1_EN_SHIFT 0 158 159 /* ASP_CONTROL1 */ 160 #define CS35L56_ASP_BCLK_FREQ_MASK 0x0000003F 161 #define CS35L56_ASP_BCLK_FREQ_SHIFT 0 162 163 /* ASP_CONTROL2 */ 164 #define CS35L56_ASP_RX_WIDTH_MASK 0xFF000000 165 #define CS35L56_ASP_RX_WIDTH_SHIFT 24 166 #define CS35L56_ASP_TX_WIDTH_MASK 0x00FF0000 167 #define CS35L56_ASP_TX_WIDTH_SHIFT 16 168 #define CS35L56_ASP_FMT_MASK 0x00000700 169 #define CS35L56_ASP_FMT_SHIFT 8 170 #define CS35L56_ASP_BCLK_INV_MASK 0x00000040 171 #define CS35L56_ASP_FSYNC_INV_MASK 0x00000004 172 173 /* ASP_CONTROL3 */ 174 #define CS35L56_ASP1_DOUT_HIZ_CTRL_MASK 0x00000003 175 176 /* ASP_DATA_CONTROL1 */ 177 #define CS35L56_ASP_TX_WL_MASK 0x0000003F 178 179 /* ASP_DATA_CONTROL5 */ 180 #define CS35L56_ASP_RX_WL_MASK 0x0000003F 181 182 /* ASPTXn_INPUT */ 183 #define CS35L56_ASP_TXn_SRC_MASK 0x0000007F 184 185 /* SWIRETX[1..7]_SRC SDWTXn INPUT */ 186 #define CS35L56_SWIRETXn_SRC_MASK 0x0000007F 187 188 /* IRQ1_STATUS */ 189 #define CS35L56_IRQ1_STS_MASK 0x00000001 190 191 /* IRQ1_EINT_1 */ 192 #define CS35L56_AMP_SHORT_ERR_EINT1_MASK 0x80000000 193 194 /* IRQ1_EINT_2 */ 195 #define CS35L56_DSP_VIRTUAL2_MBOX_WR_EINT1_MASK 0x00200000 196 197 /* IRQ1_EINT_4 */ 198 #define CS35L56_OTP_BOOT_DONE_MASK 0x00000002 199 200 /* IRQ1_EINT_8 */ 201 #define CS35L56_TEMP_ERR_EINT1_MASK 0x80000000 202 203 /* MIXER_NGATE_CHn_CFG */ 204 #define CS35L56_AUX_NGATE_CHn_EN 0x00000001 205 206 /* GPIOn_CTRL1 */ 207 #define CS35L56_GPIO_DIR_MASK BIT(31) 208 #define CS35L56_GPIO_FN_MASK GENMASK(2, 0) 209 210 #define CS35L56_GPIO_FN_GPIO 0x00000001 211 212 /* Mixer input sources */ 213 #define CS35L56_INPUT_SRC_NONE 0x00 214 #define CS35L56_INPUT_SRC_ASP1RX1 0x08 215 #define CS35L56_INPUT_SRC_ASP1RX2 0x09 216 #define CS35L56_INPUT_SRC_VMON 0x18 217 #define CS35L56_INPUT_SRC_IMON 0x19 218 #define CS35L56_INPUT_SRC_ERR_VOL 0x20 219 #define CS35L56_INPUT_SRC_CLASSH 0x21 220 #define CS35L56_INPUT_SRC_VDDBMON 0x28 221 #define CS35L56_INPUT_SRC_VBSTMON 0x29 222 #define CS35L56_INPUT_SRC_DSP1TX1 0x32 223 #define CS35L56_INPUT_SRC_DSP1TX2 0x33 224 #define CS35L56_INPUT_SRC_DSP1TX3 0x34 225 #define CS35L56_INPUT_SRC_DSP1TX4 0x35 226 #define CS35L56_INPUT_SRC_DSP1TX5 0x36 227 #define CS35L56_INPUT_SRC_DSP1TX6 0x37 228 #define CS35L56_INPUT_SRC_DSP1TX7 0x38 229 #define CS35L56_INPUT_SRC_DSP1TX8 0x39 230 #define CS35L56_INPUT_SRC_TEMPMON 0x3A 231 #define CS35L56_INPUT_SRC_INTERPOLATOR 0x40 232 #define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1 0x44 233 #define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2 0x45 234 #define CS35L56_INPUT_MASK 0x7F 235 236 #define CS35L56_NUM_INPUT_SRC 21 237 238 /* ASP formats */ 239 #define CS35L56_ASP_FMT_DSP_A 0 240 #define CS35L56_ASP_FMT_I2S 2 241 242 /* ASP HiZ modes */ 243 #define CS35L56_ASP_UNUSED_HIZ_OFF_HIZ 3 244 245 /* MAIN_RENDER_ACTUAL_PS */ 246 #define CS35L56_PS0 0 247 #define CS35L56_PS3 3 248 249 /* CS35L56_DSP_RESTRICT_STS1 */ 250 #define CS35L56_RESTRICTED_MASK 0x7 251 252 /* CS35L56_MAIN_RENDER_USER_MUTE */ 253 #define CS35L56_MAIN_RENDER_USER_MUTE_MASK 1 254 255 /* CS35L56_MAIN_RENDER_USER_VOLUME */ 256 #define CS35L56_MAIN_RENDER_USER_VOLUME_MIN -400 257 #define CS35L56_MAIN_RENDER_USER_VOLUME_MAX 48 258 #define CS35L56_MAIN_RENDER_USER_VOLUME_MASK 0x0000FFC0 259 #define CS35L56_MAIN_RENDER_USER_VOLUME_SHIFT 6 260 #define CS35L56_MAIN_RENDER_USER_VOLUME_SIGNBIT 9 261 262 /* CS35L56_MAIN_POSTURE_NUMBER */ 263 #define CS35L56_MAIN_POSTURE_MIN 0 264 #define CS35L56_MAIN_POSTURE_MAX 255 265 #define CS35L56_MAIN_POSTURE_MASK CS35L56_MAIN_POSTURE_MAX 266 267 /* CS35L56_PROTECTION_STATUS */ 268 #define CS35L56_FIRMWARE_MISSING BIT(0) 269 270 /* Software Values */ 271 #define CS35L56_HALO_STATE_SHUTDOWN 1 272 #define CS35L56_HALO_STATE_BOOT_DONE 2 273 274 #define CS35L56_MBOX_CMD_PING 0x0A000000 275 #define CS35L56_MBOX_CMD_AUDIO_PLAY 0x0B000001 276 #define CS35L56_MBOX_CMD_AUDIO_PAUSE 0x0B000002 277 #define CS35L56_MBOX_CMD_AUDIO_REINIT 0x0B000003 278 #define CS35L56_MBOX_CMD_AUDIO_CALIBRATION 0x0B000006 279 #define CS35L56_MBOX_CMD_HIBERNATE_NOW 0x02000001 280 #define CS35L56_MBOX_CMD_WAKEUP 0x02000002 281 #define CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE 0x02000003 282 #define CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE 0x02000004 283 #define CS35L56_MBOX_CMD_SHUTDOWN 0x02000005 284 #define CS35L56_MBOX_CMD_SYSTEM_RESET 0x02000007 285 286 #define CS35L56_MBOX_TIMEOUT_US 5000 287 #define CS35L56_MBOX_POLL_US 250 288 289 #define CS35L56_PS0_POLL_US 500 290 #define CS35L56_PS0_TIMEOUT_US 50000 291 #define CS35L56_PS3_POLL_US 500 292 #define CS35L56_PS3_TIMEOUT_US 300000 293 294 #define CS35L56_CAL_STATUS_SUCCESS 1 295 #define CS35L56_CAL_STATUS_OUT_OF_RANGE 3 296 297 #define CS35L56_CAL_SET_STATUS_UNKNOWN 0 298 #define CS35L56_CAL_SET_STATUS_DEFAULT 1 299 #define CS35L56_CAL_SET_STATUS_SET 2 300 301 #define CS35L56_CONTROL_PORT_READY_US 2200 302 #define CS35L56_HALO_STATE_POLL_US 1000 303 #define CS35L56_HALO_STATE_TIMEOUT_US 250000 304 #define CS35L56_RESET_PULSE_MIN_US 1100 305 #define CS35L56_WAKE_HOLD_TIME_US 1000 306 #define CS35L56_PAD_PULL_SETTLE_US 10 307 308 #define CS35L56_CALIBRATION_POLL_US (100 * USEC_PER_MSEC) 309 #define CS35L56_CALIBRATION_TIMEOUT_US (5 * USEC_PER_SEC) 310 311 #define CS35L56_SDW1_PLAYBACK_PORT 1 312 #define CS35L56_SDW1_CAPTURE_PORT 3 313 314 #define CS35L56_NUM_BULK_SUPPLIES 3 315 #define CS35L56_NUM_DSP_REGIONS 5 316 317 #define CS35L56_MAX_GPIO 13 318 #define CS35L63_MAX_GPIO 9 319 320 /* Additional margin for SYSTEM_RESET to control port ready on SPI */ 321 #define CS35L56_SPI_RESET_TO_PORT_READY_US (CS35L56_CONTROL_PORT_READY_US + 2500) 322 323 struct cs35l56_spi_payload { 324 __be32 addr; 325 __be16 pad; 326 __be32 value; 327 } __packed; 328 static_assert(sizeof(struct cs35l56_spi_payload) == 10); 329 330 struct cs35l56_fw_reg { 331 unsigned int fw_ver; 332 unsigned int halo_state; 333 unsigned int pm_cur_stat; 334 unsigned int prot_sts; 335 unsigned int transducer_actual_ps; 336 unsigned int user_mute; 337 unsigned int user_volume; 338 unsigned int posture_number; 339 }; 340 341 struct cs35l56_cal_debugfs_fops { 342 const struct debugfs_short_fops calibrate; 343 const struct debugfs_short_fops cal_temperature; 344 const struct debugfs_short_fops cal_data; 345 }; 346 347 struct cs35l56_base { 348 struct device *dev; 349 struct regmap *regmap; 350 struct cs_dsp *dsp; 351 int irq; 352 struct mutex irq_lock; 353 u8 type; 354 u8 rev; 355 bool init_done; 356 bool fw_patched; 357 bool secured; 358 bool can_hibernate; 359 bool cal_data_valid; 360 s8 cal_index; 361 u8 num_amps; 362 struct cirrus_amp_cal_data cal_data; 363 struct gpio_desc *reset_gpio; 364 struct cs35l56_spi_payload *spi_payload_buf; 365 const struct cs35l56_fw_reg *fw_reg; 366 const struct cirrus_amp_cal_controls *calibration_controls; 367 struct dentry *debugfs; 368 u64 silicon_uid; 369 u8 onchip_spkid_gpios[5]; 370 u8 num_onchip_spkid_gpios; 371 u8 onchip_spkid_pulls[5]; 372 u8 num_onchip_spkid_pulls; 373 }; 374 375 static inline bool cs35l56_is_otp_register(unsigned int reg) 376 { 377 return (reg >> 16) == 3; 378 } 379 380 static inline int cs35l56_init_config_for_spi(struct cs35l56_base *cs35l56, 381 struct spi_device *spi) 382 { 383 cs35l56->spi_payload_buf = devm_kzalloc(&spi->dev, 384 sizeof(*cs35l56->spi_payload_buf), 385 GFP_KERNEL | GFP_DMA); 386 if (!cs35l56->spi_payload_buf) 387 return -ENOMEM; 388 389 return 0; 390 } 391 392 static inline bool cs35l56_is_spi(struct cs35l56_base *cs35l56) 393 { 394 return IS_ENABLED(CONFIG_SPI_MASTER) && !!cs35l56->spi_payload_buf; 395 } 396 397 extern const struct regmap_config cs35l56_regmap_i2c; 398 extern const struct regmap_config cs35l56_regmap_spi; 399 extern const struct regmap_config cs35l56_regmap_sdw; 400 extern const struct regmap_config cs35l63_regmap_i2c; 401 extern const struct regmap_config cs35l63_regmap_sdw; 402 403 extern const struct cirrus_amp_cal_controls cs35l56_calibration_controls; 404 extern const char * const cs35l56_cal_set_status_text[3]; 405 406 extern const char * const cs35l56_tx_input_texts[CS35L56_NUM_INPUT_SRC]; 407 extern const unsigned int cs35l56_tx_input_values[CS35L56_NUM_INPUT_SRC]; 408 409 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base); 410 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command); 411 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base); 412 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base); 413 void cs35l56_wait_control_port_ready(void); 414 void cs35l56_wait_min_reset_pulse(void); 415 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire); 416 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq); 417 irqreturn_t cs35l56_irq(int irq, void *data); 418 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base); 419 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base); 420 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire); 421 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp); 422 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base); 423 int cs35l56_stash_calibration(struct cs35l56_base *cs35l56_base, 424 const struct cirrus_amp_cal_data *data); 425 ssize_t cs35l56_calibrate_debugfs_write(struct cs35l56_base *cs35l56_base, 426 const char __user *from, size_t count, 427 loff_t *ppos); 428 ssize_t cs35l56_cal_ambient_debugfs_write(struct cs35l56_base *cs35l56_base, 429 const char __user *from, size_t count, 430 loff_t *ppos); 431 ssize_t cs35l56_cal_data_debugfs_read(struct cs35l56_base *cs35l56_base, 432 char __user *to, size_t count, 433 loff_t *ppos); 434 ssize_t cs35l56_cal_data_debugfs_write(struct cs35l56_base *cs35l56_base, 435 const char __user *from, size_t count, 436 loff_t *ppos); 437 void cs35l56_create_cal_debugfs(struct cs35l56_base *cs35l56_base, 438 const struct cs35l56_cal_debugfs_fops *fops); 439 void cs35l56_remove_cal_debugfs(struct cs35l56_base *cs35l56_base); 440 int cs35l56_cal_set_status_get(struct cs35l56_base *cs35l56_base, 441 struct snd_ctl_elem_value *uvalue); 442 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 443 bool *fw_missing, unsigned int *fw_version); 444 void cs35l56_warn_if_firmware_missing(struct cs35l56_base *cs35l56_base); 445 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp); 446 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base); 447 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base); 448 int cs35l56_check_and_save_onchip_spkid_gpios(struct cs35l56_base *cs35l56_base, 449 const u32 *gpios, int num_gpios, 450 const u32 *pulls, int num_pulls); 451 int cs35l56_configure_onchip_spkid_pads(struct cs35l56_base *cs35l56_base); 452 int cs35l56_read_onchip_spkid(struct cs35l56_base *cs35l56_base); 453 int cs35l56_get_bclk_freq_id(unsigned int freq); 454 void cs35l56_fill_supply_names(struct regulator_bulk_data *data); 455 456 #endif /* ifndef __CS35L56_H */ 457