1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Common definitions for Cirrus Logic CS35L56 smart amp 4 * 5 * Copyright (C) 2023 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 */ 8 9 #ifndef __CS35L56_H 10 #define __CS35L56_H 11 12 #include <linux/debugfs.h> 13 #include <linux/firmware/cirrus/cs_dsp.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/regmap.h> 16 #include <linux/spi/spi.h> 17 #include <sound/cs-amp-lib.h> 18 19 struct snd_ctl_elem_value; 20 21 #define CS35L56_DEVID 0x0000000 22 #define CS35L56_REVID 0x0000004 23 #define CS35L56_RELID 0x000000C 24 #define CS35L56_OTPID 0x0000010 25 #define CS35L56_SFT_RESET 0x0000020 26 #define CS35L56_GLOBAL_ENABLES 0x0002014 27 #define CS35L56_BLOCK_ENABLES 0x0002018 28 #define CS35L56_BLOCK_ENABLES2 0x000201C 29 #define CS35L56_REFCLK_INPUT 0x0002C04 30 #define CS35L56_GLOBAL_SAMPLE_RATE 0x0002C0C 31 #define CS35L56_OTP_MEM_53 0x00300D4 32 #define CS35L56_OTP_MEM_54 0x00300D8 33 #define CS35L56_OTP_MEM_55 0x00300DC 34 #define CS35L56_ASP1_ENABLES1 0x0004800 35 #define CS35L56_ASP1_CONTROL1 0x0004804 36 #define CS35L56_ASP1_CONTROL2 0x0004808 37 #define CS35L56_ASP1_CONTROL3 0x000480C 38 #define CS35L56_ASP1_FRAME_CONTROL1 0x0004810 39 #define CS35L56_ASP1_FRAME_CONTROL5 0x0004820 40 #define CS35L56_ASP1_DATA_CONTROL1 0x0004830 41 #define CS35L56_ASP1_DATA_CONTROL5 0x0004840 42 #define CS35L56_DACPCM1_INPUT 0x0004C00 43 #define CS35L56_DACPCM2_INPUT 0x0004C08 44 #define CS35L56_ASP1TX1_INPUT 0x0004C20 45 #define CS35L56_ASP1TX2_INPUT 0x0004C24 46 #define CS35L56_ASP1TX3_INPUT 0x0004C28 47 #define CS35L56_ASP1TX4_INPUT 0x0004C2C 48 #define CS35L56_DSP1RX1_INPUT 0x0004C40 49 #define CS35L56_DSP1RX2_INPUT 0x0004C44 50 #define CS35L56_SWIRE_DP3_CH1_INPUT 0x0004C70 51 #define CS35L56_SWIRE_DP3_CH2_INPUT 0x0004C74 52 #define CS35L56_SWIRE_DP3_CH3_INPUT 0x0004C78 53 #define CS35L56_SWIRE_DP3_CH4_INPUT 0x0004C7C 54 #define CS35L56_IRQ1_CFG 0x000E000 55 #define CS35L56_IRQ1_STATUS 0x000E004 56 #define CS35L56_IRQ1_EINT_1 0x000E010 57 #define CS35L56_IRQ1_EINT_2 0x000E014 58 #define CS35L56_IRQ1_EINT_4 0x000E01C 59 #define CS35L56_IRQ1_EINT_8 0x000E02C 60 #define CS35L56_IRQ1_EINT_18 0x000E054 61 #define CS35L56_IRQ1_EINT_20 0x000E05C 62 #define CS35L56_IRQ1_MASK_1 0x000E090 63 #define CS35L56_IRQ1_MASK_2 0x000E094 64 #define CS35L56_IRQ1_MASK_4 0x000E09C 65 #define CS35L56_IRQ1_MASK_8 0x000E0AC 66 #define CS35L56_IRQ1_MASK_18 0x000E0D4 67 #define CS35L56_IRQ1_MASK_20 0x000E0DC 68 #define CS35L56_MIXER_NGATE_CH1_CFG 0x0010004 69 #define CS35L56_MIXER_NGATE_CH2_CFG 0x0010008 70 #define CS35L56_DSP_MBOX_1_RAW 0x0011000 71 #define CS35L56_DSP_VIRTUAL1_MBOX_1 0x0011020 72 #define CS35L56_DSP_VIRTUAL1_MBOX_2 0x0011024 73 #define CS35L56_DSP_VIRTUAL1_MBOX_3 0x0011028 74 #define CS35L56_DSP_VIRTUAL1_MBOX_4 0x001102C 75 #define CS35L56_DSP_VIRTUAL1_MBOX_5 0x0011030 76 #define CS35L56_DSP_VIRTUAL1_MBOX_6 0x0011034 77 #define CS35L56_DSP_VIRTUAL1_MBOX_7 0x0011038 78 #define CS35L56_DSP_VIRTUAL1_MBOX_8 0x001103C 79 #define CS35L56_DIE_STS1 0x0017040 80 #define CS35L56_DIE_STS2 0x0017044 81 #define CS35L56_DSP_RESTRICT_STS1 0x00190F0 82 #define CS35L56_DSP1_XMEM_PACKED_0 0x2000000 83 #define CS35L56_DSP1_XMEM_PACKED_6143 0x2005FFC 84 #define CS35L56_DSP1_XMEM_UNPACKED32_0 0x2400000 85 #define CS35L56_DSP1_XMEM_UNPACKED32_4095 0x2403FFC 86 #define CS35L56_DSP1_SYS_INFO_ID 0x25E0000 87 #define CS35L56_DSP1_SYS_INFO_END 0x25E004C 88 #define CS35L56_DSP1_AHBM_WINDOW_DEBUG_0 0x25E2040 89 #define CS35L56_DSP1_AHBM_WINDOW_DEBUG_1 0x25E2044 90 #define CS35L56_DSP1_XMEM_UNPACKED24_0 0x2800000 91 #define CS35L56_DSP1_FW_VER 0x2800010 92 #define CS35L56_DSP1_HALO_STATE 0x28021E0 93 #define CS35L56_B2_DSP1_HALO_STATE 0x2803D20 94 #define CS35L56_DSP1_PM_CUR_STATE 0x2804308 95 #define CS35L56_B2_DSP1_PM_CUR_STATE 0x2804678 96 #define CS35L56_DSP1_XMEM_UNPACKED24_8191 0x2807FFC 97 #define CS35L56_DSP1_CORE_BASE 0x2B80000 98 #define CS35L56_DSP1_SCRATCH1 0x2B805C0 99 #define CS35L56_DSP1_SCRATCH2 0x2B805C8 100 #define CS35L56_DSP1_SCRATCH3 0x2B805D0 101 #define CS35L56_DSP1_SCRATCH4 0x2B805D8 102 #define CS35L56_DSP1_YMEM_PACKED_0 0x2C00000 103 #define CS35L56_DSP1_YMEM_PACKED_4604 0x2C047F0 104 #define CS35L56_DSP1_YMEM_UNPACKED32_0 0x3000000 105 #define CS35L56_DSP1_YMEM_UNPACKED32_3070 0x3002FF8 106 #define CS35L56_DSP1_YMEM_UNPACKED24_0 0x3400000 107 #define CS35L56_MAIN_RENDER_USER_MUTE 0x3400024 108 #define CS35L56_MAIN_RENDER_USER_VOLUME 0x340002C 109 #define CS35L56_MAIN_POSTURE_NUMBER 0x3400094 110 #define CS35L56_PROTECTION_STATUS 0x34000D8 111 #define CS35L56_TRANSDUCER_ACTUAL_PS 0x3400150 112 #define CS35L56_DSP1_YMEM_UNPACKED24_6141 0x3405FF4 113 #define CS35L56_DSP1_PMEM_0 0x3800000 114 #define CS35L56_DSP1_PMEM_5114 0x3804FE8 115 116 #define CS35L63_DSP1_FW_VER CS35L56_DSP1_FW_VER 117 #define CS35L63_DSP1_HALO_STATE 0x2803C04 118 #define CS35L63_DSP1_PM_CUR_STATE 0x2804518 119 #define CS35L63_PROTECTION_STATUS 0x340009C 120 #define CS35L63_TRANSDUCER_ACTUAL_PS 0x34000F4 121 #define CS35L63_MAIN_RENDER_USER_MUTE 0x3400020 122 #define CS35L63_MAIN_RENDER_USER_VOLUME 0x3400028 123 #define CS35L63_MAIN_POSTURE_NUMBER 0x3400068 124 125 /* DEVID */ 126 #define CS35L56_DEVID_MASK 0x00FFFFFF 127 128 /* REVID */ 129 #define CS35L56_AREVID_MASK 0x000000F0 130 #define CS35L56_MTLREVID_MASK 0x0000000F 131 #define CS35L56_REVID_B0 0x000000B0 132 133 /* ASP_ENABLES1 */ 134 #define CS35L56_ASP_RX2_EN_SHIFT 17 135 #define CS35L56_ASP_RX1_EN_SHIFT 16 136 #define CS35L56_ASP_TX4_EN_SHIFT 3 137 #define CS35L56_ASP_TX3_EN_SHIFT 2 138 #define CS35L56_ASP_TX2_EN_SHIFT 1 139 #define CS35L56_ASP_TX1_EN_SHIFT 0 140 141 /* ASP_CONTROL1 */ 142 #define CS35L56_ASP_BCLK_FREQ_MASK 0x0000003F 143 #define CS35L56_ASP_BCLK_FREQ_SHIFT 0 144 145 /* ASP_CONTROL2 */ 146 #define CS35L56_ASP_RX_WIDTH_MASK 0xFF000000 147 #define CS35L56_ASP_RX_WIDTH_SHIFT 24 148 #define CS35L56_ASP_TX_WIDTH_MASK 0x00FF0000 149 #define CS35L56_ASP_TX_WIDTH_SHIFT 16 150 #define CS35L56_ASP_FMT_MASK 0x00000700 151 #define CS35L56_ASP_FMT_SHIFT 8 152 #define CS35L56_ASP_BCLK_INV_MASK 0x00000040 153 #define CS35L56_ASP_FSYNC_INV_MASK 0x00000004 154 155 /* ASP_CONTROL3 */ 156 #define CS35L56_ASP1_DOUT_HIZ_CTRL_MASK 0x00000003 157 158 /* ASP_DATA_CONTROL1 */ 159 #define CS35L56_ASP_TX_WL_MASK 0x0000003F 160 161 /* ASP_DATA_CONTROL5 */ 162 #define CS35L56_ASP_RX_WL_MASK 0x0000003F 163 164 /* ASPTXn_INPUT */ 165 #define CS35L56_ASP_TXn_SRC_MASK 0x0000007F 166 167 /* SWIRETX[1..7]_SRC SDWTXn INPUT */ 168 #define CS35L56_SWIRETXn_SRC_MASK 0x0000007F 169 170 /* IRQ1_STATUS */ 171 #define CS35L56_IRQ1_STS_MASK 0x00000001 172 173 /* IRQ1_EINT_1 */ 174 #define CS35L56_AMP_SHORT_ERR_EINT1_MASK 0x80000000 175 176 /* IRQ1_EINT_2 */ 177 #define CS35L56_DSP_VIRTUAL2_MBOX_WR_EINT1_MASK 0x00200000 178 179 /* IRQ1_EINT_4 */ 180 #define CS35L56_OTP_BOOT_DONE_MASK 0x00000002 181 182 /* IRQ1_EINT_8 */ 183 #define CS35L56_TEMP_ERR_EINT1_MASK 0x80000000 184 185 /* MIXER_NGATE_CHn_CFG */ 186 #define CS35L56_AUX_NGATE_CHn_EN 0x00000001 187 188 /* Mixer input sources */ 189 #define CS35L56_INPUT_SRC_NONE 0x00 190 #define CS35L56_INPUT_SRC_ASP1RX1 0x08 191 #define CS35L56_INPUT_SRC_ASP1RX2 0x09 192 #define CS35L56_INPUT_SRC_VMON 0x18 193 #define CS35L56_INPUT_SRC_IMON 0x19 194 #define CS35L56_INPUT_SRC_ERR_VOL 0x20 195 #define CS35L56_INPUT_SRC_CLASSH 0x21 196 #define CS35L56_INPUT_SRC_VDDBMON 0x28 197 #define CS35L56_INPUT_SRC_VBSTMON 0x29 198 #define CS35L56_INPUT_SRC_DSP1TX1 0x32 199 #define CS35L56_INPUT_SRC_DSP1TX2 0x33 200 #define CS35L56_INPUT_SRC_DSP1TX3 0x34 201 #define CS35L56_INPUT_SRC_DSP1TX4 0x35 202 #define CS35L56_INPUT_SRC_DSP1TX5 0x36 203 #define CS35L56_INPUT_SRC_DSP1TX6 0x37 204 #define CS35L56_INPUT_SRC_DSP1TX7 0x38 205 #define CS35L56_INPUT_SRC_DSP1TX8 0x39 206 #define CS35L56_INPUT_SRC_TEMPMON 0x3A 207 #define CS35L56_INPUT_SRC_INTERPOLATOR 0x40 208 #define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1 0x44 209 #define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2 0x45 210 #define CS35L56_INPUT_MASK 0x7F 211 212 #define CS35L56_NUM_INPUT_SRC 21 213 214 /* ASP formats */ 215 #define CS35L56_ASP_FMT_DSP_A 0 216 #define CS35L56_ASP_FMT_I2S 2 217 218 /* ASP HiZ modes */ 219 #define CS35L56_ASP_UNUSED_HIZ_OFF_HIZ 3 220 221 /* MAIN_RENDER_ACTUAL_PS */ 222 #define CS35L56_PS0 0 223 #define CS35L56_PS3 3 224 225 /* CS35L56_DSP_RESTRICT_STS1 */ 226 #define CS35L56_RESTRICTED_MASK 0x7 227 228 /* CS35L56_MAIN_RENDER_USER_MUTE */ 229 #define CS35L56_MAIN_RENDER_USER_MUTE_MASK 1 230 231 /* CS35L56_MAIN_RENDER_USER_VOLUME */ 232 #define CS35L56_MAIN_RENDER_USER_VOLUME_MIN -400 233 #define CS35L56_MAIN_RENDER_USER_VOLUME_MAX 48 234 #define CS35L56_MAIN_RENDER_USER_VOLUME_MASK 0x0000FFC0 235 #define CS35L56_MAIN_RENDER_USER_VOLUME_SHIFT 6 236 #define CS35L56_MAIN_RENDER_USER_VOLUME_SIGNBIT 9 237 238 /* CS35L56_MAIN_POSTURE_NUMBER */ 239 #define CS35L56_MAIN_POSTURE_MIN 0 240 #define CS35L56_MAIN_POSTURE_MAX 255 241 #define CS35L56_MAIN_POSTURE_MASK CS35L56_MAIN_POSTURE_MAX 242 243 /* CS35L56_PROTECTION_STATUS */ 244 #define CS35L56_FIRMWARE_MISSING BIT(0) 245 246 /* Software Values */ 247 #define CS35L56_HALO_STATE_SHUTDOWN 1 248 #define CS35L56_HALO_STATE_BOOT_DONE 2 249 250 #define CS35L56_MBOX_CMD_PING 0x0A000000 251 #define CS35L56_MBOX_CMD_AUDIO_PLAY 0x0B000001 252 #define CS35L56_MBOX_CMD_AUDIO_PAUSE 0x0B000002 253 #define CS35L56_MBOX_CMD_AUDIO_REINIT 0x0B000003 254 #define CS35L56_MBOX_CMD_AUDIO_CALIBRATION 0x0B000006 255 #define CS35L56_MBOX_CMD_HIBERNATE_NOW 0x02000001 256 #define CS35L56_MBOX_CMD_WAKEUP 0x02000002 257 #define CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE 0x02000003 258 #define CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE 0x02000004 259 #define CS35L56_MBOX_CMD_SHUTDOWN 0x02000005 260 #define CS35L56_MBOX_CMD_SYSTEM_RESET 0x02000007 261 262 #define CS35L56_MBOX_TIMEOUT_US 5000 263 #define CS35L56_MBOX_POLL_US 250 264 265 #define CS35L56_PS0_POLL_US 500 266 #define CS35L56_PS0_TIMEOUT_US 50000 267 #define CS35L56_PS3_POLL_US 500 268 #define CS35L56_PS3_TIMEOUT_US 300000 269 270 #define CS35L56_CAL_STATUS_SUCCESS 1 271 #define CS35L56_CAL_STATUS_OUT_OF_RANGE 3 272 273 #define CS35L56_CAL_SET_STATUS_UNKNOWN 0 274 #define CS35L56_CAL_SET_STATUS_DEFAULT 1 275 #define CS35L56_CAL_SET_STATUS_SET 2 276 277 #define CS35L56_CONTROL_PORT_READY_US 2200 278 #define CS35L56_HALO_STATE_POLL_US 1000 279 #define CS35L56_HALO_STATE_TIMEOUT_US 250000 280 #define CS35L56_RESET_PULSE_MIN_US 1100 281 #define CS35L56_WAKE_HOLD_TIME_US 1000 282 283 #define CS35L56_CALIBRATION_POLL_US (100 * USEC_PER_MSEC) 284 #define CS35L56_CALIBRATION_TIMEOUT_US (5 * USEC_PER_SEC) 285 286 #define CS35L56_SDW1_PLAYBACK_PORT 1 287 #define CS35L56_SDW1_CAPTURE_PORT 3 288 289 #define CS35L56_NUM_BULK_SUPPLIES 3 290 #define CS35L56_NUM_DSP_REGIONS 5 291 292 /* Additional margin for SYSTEM_RESET to control port ready on SPI */ 293 #define CS35L56_SPI_RESET_TO_PORT_READY_US (CS35L56_CONTROL_PORT_READY_US + 2500) 294 295 struct cs35l56_spi_payload { 296 __be32 addr; 297 __be16 pad; 298 __be32 value; 299 } __packed; 300 static_assert(sizeof(struct cs35l56_spi_payload) == 10); 301 302 struct cs35l56_fw_reg { 303 unsigned int fw_ver; 304 unsigned int halo_state; 305 unsigned int pm_cur_stat; 306 unsigned int prot_sts; 307 unsigned int transducer_actual_ps; 308 unsigned int user_mute; 309 unsigned int user_volume; 310 unsigned int posture_number; 311 }; 312 313 struct cs35l56_cal_debugfs_fops { 314 const struct debugfs_short_fops calibrate; 315 const struct debugfs_short_fops cal_temperature; 316 const struct debugfs_short_fops cal_data; 317 }; 318 319 struct cs35l56_base { 320 struct device *dev; 321 struct regmap *regmap; 322 struct cs_dsp *dsp; 323 int irq; 324 struct mutex irq_lock; 325 u8 type; 326 u8 rev; 327 bool init_done; 328 bool fw_patched; 329 bool secured; 330 bool can_hibernate; 331 bool cal_data_valid; 332 s8 cal_index; 333 u8 num_amps; 334 struct cirrus_amp_cal_data cal_data; 335 struct gpio_desc *reset_gpio; 336 struct cs35l56_spi_payload *spi_payload_buf; 337 const struct cs35l56_fw_reg *fw_reg; 338 const struct cirrus_amp_cal_controls *calibration_controls; 339 struct dentry *debugfs; 340 u64 silicon_uid; 341 }; 342 343 static inline bool cs35l56_is_otp_register(unsigned int reg) 344 { 345 return (reg >> 16) == 3; 346 } 347 348 static inline int cs35l56_init_config_for_spi(struct cs35l56_base *cs35l56, 349 struct spi_device *spi) 350 { 351 cs35l56->spi_payload_buf = devm_kzalloc(&spi->dev, 352 sizeof(*cs35l56->spi_payload_buf), 353 GFP_KERNEL | GFP_DMA); 354 if (!cs35l56->spi_payload_buf) 355 return -ENOMEM; 356 357 return 0; 358 } 359 360 static inline bool cs35l56_is_spi(struct cs35l56_base *cs35l56) 361 { 362 return IS_ENABLED(CONFIG_SPI_MASTER) && !!cs35l56->spi_payload_buf; 363 } 364 365 extern const struct regmap_config cs35l56_regmap_i2c; 366 extern const struct regmap_config cs35l56_regmap_spi; 367 extern const struct regmap_config cs35l56_regmap_sdw; 368 extern const struct regmap_config cs35l63_regmap_i2c; 369 extern const struct regmap_config cs35l63_regmap_sdw; 370 371 extern const struct cirrus_amp_cal_controls cs35l56_calibration_controls; 372 extern const char * const cs35l56_cal_set_status_text[3]; 373 374 extern const char * const cs35l56_tx_input_texts[CS35L56_NUM_INPUT_SRC]; 375 extern const unsigned int cs35l56_tx_input_values[CS35L56_NUM_INPUT_SRC]; 376 377 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base); 378 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command); 379 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base); 380 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base); 381 void cs35l56_wait_control_port_ready(void); 382 void cs35l56_wait_min_reset_pulse(void); 383 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire); 384 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq); 385 irqreturn_t cs35l56_irq(int irq, void *data); 386 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base); 387 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base); 388 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire); 389 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp); 390 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base); 391 int cs35l56_stash_calibration(struct cs35l56_base *cs35l56_base, 392 const struct cirrus_amp_cal_data *data); 393 ssize_t cs35l56_calibrate_debugfs_write(struct cs35l56_base *cs35l56_base, 394 const char __user *from, size_t count, 395 loff_t *ppos); 396 ssize_t cs35l56_cal_ambient_debugfs_write(struct cs35l56_base *cs35l56_base, 397 const char __user *from, size_t count, 398 loff_t *ppos); 399 ssize_t cs35l56_cal_data_debugfs_read(struct cs35l56_base *cs35l56_base, 400 char __user *to, size_t count, 401 loff_t *ppos); 402 ssize_t cs35l56_cal_data_debugfs_write(struct cs35l56_base *cs35l56_base, 403 const char __user *from, size_t count, 404 loff_t *ppos); 405 void cs35l56_create_cal_debugfs(struct cs35l56_base *cs35l56_base, 406 const struct cs35l56_cal_debugfs_fops *fops); 407 void cs35l56_remove_cal_debugfs(struct cs35l56_base *cs35l56_base); 408 int cs35l56_cal_set_status_get(struct cs35l56_base *cs35l56_base, 409 struct snd_ctl_elem_value *uvalue); 410 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 411 bool *fw_missing, unsigned int *fw_version); 412 void cs35l56_warn_if_firmware_missing(struct cs35l56_base *cs35l56_base); 413 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp); 414 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base); 415 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base); 416 int cs35l56_get_bclk_freq_id(unsigned int freq); 417 void cs35l56_fill_supply_names(struct regulator_bulk_data *data); 418 419 #endif /* ifndef __CS35L56_H */ 420