1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Common definitions for Cirrus Logic CS35L56 smart amp 4 * 5 * Copyright (C) 2023 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 */ 8 9 #ifndef __CS35L56_H 10 #define __CS35L56_H 11 12 #include <linux/firmware/cirrus/cs_dsp.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/regmap.h> 15 #include <linux/spi/spi.h> 16 #include <sound/cs-amp-lib.h> 17 18 #define CS35L56_DEVID 0x0000000 19 #define CS35L56_REVID 0x0000004 20 #define CS35L56_RELID 0x000000C 21 #define CS35L56_OTPID 0x0000010 22 #define CS35L56_SFT_RESET 0x0000020 23 #define CS35L56_GLOBAL_ENABLES 0x0002014 24 #define CS35L56_BLOCK_ENABLES 0x0002018 25 #define CS35L56_BLOCK_ENABLES2 0x000201C 26 #define CS35L56_REFCLK_INPUT 0x0002C04 27 #define CS35L56_GLOBAL_SAMPLE_RATE 0x0002C0C 28 #define CS35L56_OTP_MEM_53 0x00300D4 29 #define CS35L56_OTP_MEM_54 0x00300D8 30 #define CS35L56_OTP_MEM_55 0x00300DC 31 #define CS35L56_ASP1_ENABLES1 0x0004800 32 #define CS35L56_ASP1_CONTROL1 0x0004804 33 #define CS35L56_ASP1_CONTROL2 0x0004808 34 #define CS35L56_ASP1_CONTROL3 0x000480C 35 #define CS35L56_ASP1_FRAME_CONTROL1 0x0004810 36 #define CS35L56_ASP1_FRAME_CONTROL5 0x0004820 37 #define CS35L56_ASP1_DATA_CONTROL1 0x0004830 38 #define CS35L56_ASP1_DATA_CONTROL5 0x0004840 39 #define CS35L56_DACPCM1_INPUT 0x0004C00 40 #define CS35L56_DACPCM2_INPUT 0x0004C08 41 #define CS35L56_ASP1TX1_INPUT 0x0004C20 42 #define CS35L56_ASP1TX2_INPUT 0x0004C24 43 #define CS35L56_ASP1TX3_INPUT 0x0004C28 44 #define CS35L56_ASP1TX4_INPUT 0x0004C2C 45 #define CS35L56_DSP1RX1_INPUT 0x0004C40 46 #define CS35L56_DSP1RX2_INPUT 0x0004C44 47 #define CS35L56_SWIRE_DP3_CH1_INPUT 0x0004C70 48 #define CS35L56_SWIRE_DP3_CH2_INPUT 0x0004C74 49 #define CS35L56_SWIRE_DP3_CH3_INPUT 0x0004C78 50 #define CS35L56_SWIRE_DP3_CH4_INPUT 0x0004C7C 51 #define CS35L56_IRQ1_CFG 0x000E000 52 #define CS35L56_IRQ1_STATUS 0x000E004 53 #define CS35L56_IRQ1_EINT_1 0x000E010 54 #define CS35L56_IRQ1_EINT_2 0x000E014 55 #define CS35L56_IRQ1_EINT_4 0x000E01C 56 #define CS35L56_IRQ1_EINT_8 0x000E02C 57 #define CS35L56_IRQ1_EINT_18 0x000E054 58 #define CS35L56_IRQ1_EINT_20 0x000E05C 59 #define CS35L56_IRQ1_MASK_1 0x000E090 60 #define CS35L56_IRQ1_MASK_2 0x000E094 61 #define CS35L56_IRQ1_MASK_4 0x000E09C 62 #define CS35L56_IRQ1_MASK_8 0x000E0AC 63 #define CS35L56_IRQ1_MASK_18 0x000E0D4 64 #define CS35L56_IRQ1_MASK_20 0x000E0DC 65 #define CS35L56_DSP_MBOX_1_RAW 0x0011000 66 #define CS35L56_DSP_VIRTUAL1_MBOX_1 0x0011020 67 #define CS35L56_DSP_VIRTUAL1_MBOX_2 0x0011024 68 #define CS35L56_DSP_VIRTUAL1_MBOX_3 0x0011028 69 #define CS35L56_DSP_VIRTUAL1_MBOX_4 0x001102C 70 #define CS35L56_DSP_VIRTUAL1_MBOX_5 0x0011030 71 #define CS35L56_DSP_VIRTUAL1_MBOX_6 0x0011034 72 #define CS35L56_DSP_VIRTUAL1_MBOX_7 0x0011038 73 #define CS35L56_DSP_VIRTUAL1_MBOX_8 0x001103C 74 #define CS35L56_DSP_RESTRICT_STS1 0x00190F0 75 #define CS35L56_DSP1_XMEM_PACKED_0 0x2000000 76 #define CS35L56_DSP1_XMEM_PACKED_6143 0x2005FFC 77 #define CS35L56_DSP1_XMEM_UNPACKED32_0 0x2400000 78 #define CS35L56_DSP1_XMEM_UNPACKED32_4095 0x2403FFC 79 #define CS35L56_DSP1_SYS_INFO_ID 0x25E0000 80 #define CS35L56_DSP1_SYS_INFO_END 0x25E004C 81 #define CS35L56_DSP1_AHBM_WINDOW_DEBUG_0 0x25E2040 82 #define CS35L56_DSP1_AHBM_WINDOW_DEBUG_1 0x25E2044 83 #define CS35L56_DSP1_XMEM_UNPACKED24_0 0x2800000 84 #define CS35L56_DSP1_FW_VER 0x2800010 85 #define CS35L56_DSP1_HALO_STATE 0x28021E0 86 #define CS35L56_DSP1_PM_CUR_STATE 0x2804308 87 #define CS35L56_DSP1_XMEM_UNPACKED24_8191 0x2807FFC 88 #define CS35L56_DSP1_CORE_BASE 0x2B80000 89 #define CS35L56_DSP1_SCRATCH1 0x2B805C0 90 #define CS35L56_DSP1_SCRATCH2 0x2B805C8 91 #define CS35L56_DSP1_SCRATCH3 0x2B805D0 92 #define CS35L56_DSP1_SCRATCH4 0x2B805D8 93 #define CS35L56_DSP1_YMEM_PACKED_0 0x2C00000 94 #define CS35L56_DSP1_YMEM_PACKED_4604 0x2C047F0 95 #define CS35L56_DSP1_YMEM_UNPACKED32_0 0x3000000 96 #define CS35L56_DSP1_YMEM_UNPACKED32_3070 0x3002FF8 97 #define CS35L56_DSP1_YMEM_UNPACKED24_0 0x3400000 98 #define CS35L56_MAIN_RENDER_USER_MUTE 0x3400024 99 #define CS35L56_MAIN_RENDER_USER_VOLUME 0x340002C 100 #define CS35L56_MAIN_POSTURE_NUMBER 0x3400094 101 #define CS35L56_PROTECTION_STATUS 0x34000D8 102 #define CS35L56_TRANSDUCER_ACTUAL_PS 0x3400150 103 #define CS35L56_DSP1_YMEM_UNPACKED24_6141 0x3405FF4 104 #define CS35L56_DSP1_PMEM_0 0x3800000 105 #define CS35L56_DSP1_PMEM_5114 0x3804FE8 106 107 /* DEVID */ 108 #define CS35L56_DEVID_MASK 0x00FFFFFF 109 110 /* REVID */ 111 #define CS35L56_AREVID_MASK 0x000000F0 112 #define CS35L56_MTLREVID_MASK 0x0000000F 113 #define CS35L56_REVID_B0 0x000000B0 114 115 /* ASP_ENABLES1 */ 116 #define CS35L56_ASP_RX2_EN_SHIFT 17 117 #define CS35L56_ASP_RX1_EN_SHIFT 16 118 #define CS35L56_ASP_TX4_EN_SHIFT 3 119 #define CS35L56_ASP_TX3_EN_SHIFT 2 120 #define CS35L56_ASP_TX2_EN_SHIFT 1 121 #define CS35L56_ASP_TX1_EN_SHIFT 0 122 123 /* ASP_CONTROL1 */ 124 #define CS35L56_ASP_BCLK_FREQ_MASK 0x0000003F 125 #define CS35L56_ASP_BCLK_FREQ_SHIFT 0 126 127 /* ASP_CONTROL2 */ 128 #define CS35L56_ASP_RX_WIDTH_MASK 0xFF000000 129 #define CS35L56_ASP_RX_WIDTH_SHIFT 24 130 #define CS35L56_ASP_TX_WIDTH_MASK 0x00FF0000 131 #define CS35L56_ASP_TX_WIDTH_SHIFT 16 132 #define CS35L56_ASP_FMT_MASK 0x00000700 133 #define CS35L56_ASP_FMT_SHIFT 8 134 #define CS35L56_ASP_BCLK_INV_MASK 0x00000040 135 #define CS35L56_ASP_FSYNC_INV_MASK 0x00000004 136 137 /* ASP_CONTROL3 */ 138 #define CS35L56_ASP1_DOUT_HIZ_CTRL_MASK 0x00000003 139 140 /* ASP_DATA_CONTROL1 */ 141 #define CS35L56_ASP_TX_WL_MASK 0x0000003F 142 143 /* ASP_DATA_CONTROL5 */ 144 #define CS35L56_ASP_RX_WL_MASK 0x0000003F 145 146 /* ASPTXn_INPUT */ 147 #define CS35L56_ASP_TXn_SRC_MASK 0x0000007F 148 149 /* SWIRETX[1..7]_SRC SDWTXn INPUT */ 150 #define CS35L56_SWIRETXn_SRC_MASK 0x0000007F 151 152 /* IRQ1_STATUS */ 153 #define CS35L56_IRQ1_STS_MASK 0x00000001 154 155 /* IRQ1_EINT_1 */ 156 #define CS35L56_AMP_SHORT_ERR_EINT1_MASK 0x80000000 157 158 /* IRQ1_EINT_2 */ 159 #define CS35L56_DSP_VIRTUAL2_MBOX_WR_EINT1_MASK 0x00200000 160 161 /* IRQ1_EINT_4 */ 162 #define CS35L56_OTP_BOOT_DONE_MASK 0x00000002 163 164 /* IRQ1_EINT_8 */ 165 #define CS35L56_TEMP_ERR_EINT1_MASK 0x80000000 166 167 /* Mixer input sources */ 168 #define CS35L56_INPUT_SRC_NONE 0x00 169 #define CS35L56_INPUT_SRC_ASP1RX1 0x08 170 #define CS35L56_INPUT_SRC_ASP1RX2 0x09 171 #define CS35L56_INPUT_SRC_VMON 0x18 172 #define CS35L56_INPUT_SRC_IMON 0x19 173 #define CS35L56_INPUT_SRC_ERR_VOL 0x20 174 #define CS35L56_INPUT_SRC_CLASSH 0x21 175 #define CS35L56_INPUT_SRC_VDDBMON 0x28 176 #define CS35L56_INPUT_SRC_VBSTMON 0x29 177 #define CS35L56_INPUT_SRC_DSP1TX1 0x32 178 #define CS35L56_INPUT_SRC_DSP1TX2 0x33 179 #define CS35L56_INPUT_SRC_DSP1TX3 0x34 180 #define CS35L56_INPUT_SRC_DSP1TX4 0x35 181 #define CS35L56_INPUT_SRC_DSP1TX5 0x36 182 #define CS35L56_INPUT_SRC_DSP1TX6 0x37 183 #define CS35L56_INPUT_SRC_DSP1TX7 0x38 184 #define CS35L56_INPUT_SRC_DSP1TX8 0x39 185 #define CS35L56_INPUT_SRC_TEMPMON 0x3A 186 #define CS35L56_INPUT_SRC_INTERPOLATOR 0x40 187 #define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1 0x44 188 #define CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2 0x45 189 #define CS35L56_INPUT_MASK 0x7F 190 191 #define CS35L56_NUM_INPUT_SRC 21 192 193 /* ASP formats */ 194 #define CS35L56_ASP_FMT_DSP_A 0 195 #define CS35L56_ASP_FMT_I2S 2 196 197 /* ASP HiZ modes */ 198 #define CS35L56_ASP_UNUSED_HIZ_OFF_HIZ 3 199 200 /* MAIN_RENDER_ACTUAL_PS */ 201 #define CS35L56_PS0 0 202 #define CS35L56_PS3 3 203 204 /* CS35L56_DSP_RESTRICT_STS1 */ 205 #define CS35L56_RESTRICTED_MASK 0x7 206 207 /* CS35L56_MAIN_RENDER_USER_MUTE */ 208 #define CS35L56_MAIN_RENDER_USER_MUTE_MASK 1 209 210 /* CS35L56_MAIN_RENDER_USER_VOLUME */ 211 #define CS35L56_MAIN_RENDER_USER_VOLUME_MIN -400 212 #define CS35L56_MAIN_RENDER_USER_VOLUME_MAX 48 213 #define CS35L56_MAIN_RENDER_USER_VOLUME_MASK 0x0000FFC0 214 #define CS35L56_MAIN_RENDER_USER_VOLUME_SHIFT 6 215 #define CS35L56_MAIN_RENDER_USER_VOLUME_SIGNBIT 9 216 217 /* CS35L56_MAIN_POSTURE_NUMBER */ 218 #define CS35L56_MAIN_POSTURE_MIN 0 219 #define CS35L56_MAIN_POSTURE_MAX 255 220 #define CS35L56_MAIN_POSTURE_MASK CS35L56_MAIN_POSTURE_MAX 221 222 /* CS35L56_PROTECTION_STATUS */ 223 #define CS35L56_FIRMWARE_MISSING BIT(0) 224 225 /* Software Values */ 226 #define CS35L56_HALO_STATE_SHUTDOWN 1 227 #define CS35L56_HALO_STATE_BOOT_DONE 2 228 229 #define CS35L56_MBOX_CMD_PING 0x0A000000 230 #define CS35L56_MBOX_CMD_AUDIO_PLAY 0x0B000001 231 #define CS35L56_MBOX_CMD_AUDIO_PAUSE 0x0B000002 232 #define CS35L56_MBOX_CMD_AUDIO_REINIT 0x0B000003 233 #define CS35L56_MBOX_CMD_HIBERNATE_NOW 0x02000001 234 #define CS35L56_MBOX_CMD_WAKEUP 0x02000002 235 #define CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE 0x02000003 236 #define CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE 0x02000004 237 #define CS35L56_MBOX_CMD_SHUTDOWN 0x02000005 238 #define CS35L56_MBOX_CMD_SYSTEM_RESET 0x02000007 239 240 #define CS35L56_MBOX_TIMEOUT_US 5000 241 #define CS35L56_MBOX_POLL_US 250 242 243 #define CS35L56_PS0_POLL_US 500 244 #define CS35L56_PS0_TIMEOUT_US 50000 245 #define CS35L56_PS3_POLL_US 500 246 #define CS35L56_PS3_TIMEOUT_US 300000 247 248 #define CS35L56_CONTROL_PORT_READY_US 2200 249 #define CS35L56_HALO_STATE_POLL_US 1000 250 #define CS35L56_HALO_STATE_TIMEOUT_US 250000 251 #define CS35L56_RESET_PULSE_MIN_US 1100 252 #define CS35L56_WAKE_HOLD_TIME_US 1000 253 254 #define CS35L56_SDW1_PLAYBACK_PORT 1 255 #define CS35L56_SDW1_CAPTURE_PORT 3 256 257 #define CS35L56_NUM_BULK_SUPPLIES 3 258 #define CS35L56_NUM_DSP_REGIONS 5 259 260 /* Additional margin for SYSTEM_RESET to control port ready on SPI */ 261 #define CS35L56_SPI_RESET_TO_PORT_READY_US (CS35L56_CONTROL_PORT_READY_US + 2500) 262 263 struct cs35l56_spi_payload { 264 __be32 addr; 265 __be16 pad; 266 __be32 value; 267 } __packed; 268 static_assert(sizeof(struct cs35l56_spi_payload) == 10); 269 270 struct cs35l56_base { 271 struct device *dev; 272 struct regmap *regmap; 273 int irq; 274 struct mutex irq_lock; 275 u8 type; 276 u8 rev; 277 bool init_done; 278 bool fw_patched; 279 bool secured; 280 bool can_hibernate; 281 bool cal_data_valid; 282 s8 cal_index; 283 struct cirrus_amp_cal_data cal_data; 284 struct gpio_desc *reset_gpio; 285 struct cs35l56_spi_payload *spi_payload_buf; 286 }; 287 288 static inline bool cs35l56_is_otp_register(unsigned int reg) 289 { 290 return (reg >> 16) == 3; 291 } 292 293 static inline int cs35l56_init_config_for_spi(struct cs35l56_base *cs35l56, 294 struct spi_device *spi) 295 { 296 cs35l56->spi_payload_buf = devm_kzalloc(&spi->dev, 297 sizeof(*cs35l56->spi_payload_buf), 298 GFP_KERNEL | GFP_DMA); 299 if (!cs35l56->spi_payload_buf) 300 return -ENOMEM; 301 302 return 0; 303 } 304 305 static inline bool cs35l56_is_spi(struct cs35l56_base *cs35l56) 306 { 307 return IS_ENABLED(CONFIG_SPI_MASTER) && !!cs35l56->spi_payload_buf; 308 } 309 310 extern const struct regmap_config cs35l56_regmap_i2c; 311 extern const struct regmap_config cs35l56_regmap_spi; 312 extern const struct regmap_config cs35l56_regmap_sdw; 313 314 extern const struct cirrus_amp_cal_controls cs35l56_calibration_controls; 315 316 extern const char * const cs35l56_tx_input_texts[CS35L56_NUM_INPUT_SRC]; 317 extern const unsigned int cs35l56_tx_input_values[CS35L56_NUM_INPUT_SRC]; 318 319 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base); 320 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command); 321 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base); 322 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base); 323 void cs35l56_wait_control_port_ready(void); 324 void cs35l56_wait_min_reset_pulse(void); 325 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire); 326 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq); 327 irqreturn_t cs35l56_irq(int irq, void *data); 328 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base); 329 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base); 330 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire); 331 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp); 332 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base); 333 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 334 bool *fw_missing, unsigned int *fw_version); 335 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base); 336 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base); 337 int cs35l56_get_bclk_freq_id(unsigned int freq); 338 void cs35l56_fill_supply_names(struct regulator_bulk_data *data); 339 340 #endif /* ifndef __CS35L56_H */ 341