1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD ACP 7.x Register Documentation 4 * 5 * Copyright 2026 Advanced Micro Devices, Inc. 6 */ 7 8 #ifndef _acp_ip_7x_chip_OFFSET_BYTE_H 9 #define _acp_ip_7x_chip_OFFSET_BYTE_H 10 11 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x000C00 12 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x000C04 13 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x000C08 14 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x000C0C 15 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x000C10 16 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x000C14 17 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x000C18 18 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x000C1C 19 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x000C20 20 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x000C24 21 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x000C28 22 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x000C2C 23 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x000C30 24 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x000C34 25 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x000C38 26 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x000C3C 27 #define ACPAXI2AXI_ATU_CTRL 0x000C40 28 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x000C44 29 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x000C48 30 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x000C4C 31 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x000C50 32 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x000C54 33 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x000C58 34 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x000C5C 35 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x000C60 36 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x000C64 37 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x000C68 38 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x000C6C 39 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x000C70 40 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x000C74 41 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x000C78 42 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x000C7C 43 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x000C80 44 45 #define ACP_SOFT_RESET 0x001000 46 #define ACP_CONTROL 0x001004 47 #define ACP_STATUS 0x001008 48 #define ACP_DYNAMIC_CG_MASTER_CONTROL 0x001010 49 #define ACP_ZSC_DSP_CTRL 0x001014 50 #define ACP_ZSC_STS 0x001018 51 #define ACP_PGFSM_CONTROL 0x001024 52 #define ACP_PGFSM_STATUS 0x001028 53 #define ACP_CLKMUX_SEL 0x00102C 54 #define ACP_SW_48MHz_CLK_SEL 0x001030 55 #define ACP_AUDIO_CLK_SEL 0x001038 56 #define ACP_PDM_CORE_CLK_SEL 0x00103C 57 58 #define ACP_PME_EN 0x001400 59 #define ACP_DEVICE_STATE 0x001404 60 #define SW_DEVICE_STATE 0x001430 61 #define ACP_PIN_CONFIG 0x001440 62 #define ACP_PAD_PULLUP_CTRL 0x001444 63 #define ACP_PAD_PULLDOWN_CTRL 0x001448 64 #define ACP_PAD_DRIVE_STRENGTH_CTRL 0x00144C 65 #define ACP_PAD_SCHMEN_CTRL 0x001450 66 #define ACP_SW_PAD_KEEPER_EN 0x001454 67 #define ACP_SW_WAKE_EN 0x001458 68 #define ACP_I2S_WAKE_EN 0x00145C 69 #define ACP_ACLK_AUDIOCLK_CTRL 0x001464 70 #define ACP_PAD_DISABLE_OE_CTRL 0x001468 71 #define ACP_SW0_PME_STS 0x001474 72 #define ACP_SW1_PME_STS 0x001478 73 #define ACP_SW2_PME_STS 0x00147C 74 #define ACP_SW3_PME_STS 0x001480 75 #define ACP_I2S_PME_STS 0x001484 76 #define ACP_TDM_LOOPBACK_EN 0x001488 77 78 #define ACP_FUTURE_REG_ACLK_0 0x0018E0 79 #define ACP_FUTURE_REG_ACLK_1 0x0018E4 80 #define ACP_FUTURE_REG_ACLK_2 0x0018E8 81 #define ACP_FUTURE_REG_ACLK_3 0x0018EC 82 #define ACP_FUTURE_REG_ACLK_4 0x0018F0 83 #define ACP_AXI2DAGB_SEM_0 0x0018F4 84 85 #define ACP_EXTERNAL_INTR_ENB 0x001A00 86 #define ACP_EXTERNAL_INTR_CNTL 0x001A04 87 #define ACP_EXTERNAL_INTR_CNTL1 0x001A08 88 #define ACP_EXTERNAL_SW0_INTR_CNTL 0x001A0C 89 #define ACP_EXTERNAL_SW1_INTR_CNTL 0x001A10 90 #define ACP_EXTERNAL_SW2_INTR_CNTL 0x001A14 91 #define ACP_EXTERNAL_SW3_INTR_CNTL 0x001A18 92 #define ACP_EXTERNAL_INTR_STAT 0x001A1C 93 #define ACP_EXTERNAL_INTR_STAT1 0x001A20 94 #define ACP_EXTERNAL_SW0_INTR_STAT 0x001A24 95 #define ACP_EXTERNAL_SW1_INTR_STAT 0x001A28 96 #define ACP_EXTERNAL_SW2_INTR_STAT 0x001A2C 97 #define ACP_EXTERNAL_SW3_INTR_STAT 0x001A30 98 #define ACP_ERROR_STATUS 0x001A88 99 #define ACP_ERROR_INTR_CTRL1 0x001AA4 100 #define ACP_P1_FUTURE_REG_ACLK_0 0x001AB4 101 #define ACP_P1_FUTURE_REG_ACLK_1 0x001AB8 102 103 #define ACP_I2S_TDM0_RX_RINGBUFADDR 0x002000 104 #define ACP_I2S_TDM0_RX_RINGBUFSIZE 0x002004 105 #define ACP_I2S_TDM0_RX_LINKPOSITIONCNTR 0x002008 106 #define ACP_I2S_TDM0_RX_FIFOADDR 0x00200C 107 #define ACP_I2S_TDM0_RX_FIFOSIZE 0x002010 108 #define ACP_I2S_TDM0_RX_DMA_SIZE 0x002014 109 #define ACP_I2S_TDM0_RX_LINEARPOSITIONCNTR_HIGH 0x002018 110 #define ACP_I2S_TDM0_RX_LINEARPOSITIONCNTR_LOW 0x00201C 111 #define ACP_I2S_TDM0_RX_INTR_WATERMARK_SIZE 0x002020 112 #define ACP_I2S_TDM0_TX_RINGBUFADDR 0x002024 113 #define ACP_I2S_TDM0_TX_RINGBUFSIZE 0x002028 114 #define ACP_I2S_TDM0_TX_LINKPOSITIONCNTR 0x00202C 115 #define ACP_I2S_TDM0_TX_FIFOADDR 0x002030 116 #define ACP_I2S_TDM0_TX_FIFOSIZE 0x002034 117 #define ACP_I2S_TDM0_TX_DMA_SIZE 0x002038 118 #define ACP_I2S_TDM0_TX_LINEARPOSITIONCNTR_HIGH 0x00203C 119 #define ACP_I2S_TDM0_TX_LINEARPOSITIONCNTR_LOW 0x002040 120 #define ACP_I2S_TDM0_TX_INTR_WATERMARK_SIZE 0x002044 121 #define ACP_I2S_TDM0_POS_TRACK_TX_CTRL 0x002048 122 #define ACP_I2S_TDM0_TX_DMA_POS 0x00204C 123 #define ACP_I2S_TDM0_POS_TRACK_I2S_RX_CTRL 0x002050 124 #define ACP_I2S_TDM0_RX_DMA_POS 0x002054 125 #define ACP_I2S_TDM0_ERROR_STATUS 0x002058 126 #define ACP_I2S_TDM0_ERROR_MASK 0x00205C 127 #define ACP_I2S_TDM0_IER 0x002100 128 #define ACP_I2S_TDM0_IRER 0x002104 129 #define ACP_I2S_TDM0_RXFRMT 0x002108 130 #define ACP_I2S_TDM0_ITER 0x00210C 131 #define ACP_I2S_TDM0_TXFRMT 0x002110 132 #define ACP_I2S_TDM0_MSTRCLKGEN 0x002114 133 #define ACP_I2S_TDM0_OUTPUT_SPLIT_EN 0x002118 134 #define ACP_I2S_TDM0_WALLCLK_MISC 0x00211C 135 #define ACP_I2S_TDM0_WALL_CLK_COUNTER 0x002120 136 #define ACP_I2S_TDM_REFCLKGEN 0x002124 137 #define ACP_TDM_SYNCEN 0x002128 138 #define ACP_TDM_LRCLK_START 0x00212C 139 #define ACP_I2S_TDM0_WALLCLK_INTR_CNTL 0x002130 140 141 #define ACP_I2S_TDM1_RX_RINGBUFADDR 0x002200 142 #define ACP_I2S_TDM1_RX_RINGBUFSIZE 0x002204 143 #define ACP_I2S_TDM1_RX_LINKPOSITIONCNTR 0x002208 144 #define ACP_I2S_TDM1_RX_FIFOADDR 0x00220C 145 #define ACP_I2S_TDM1_RX_FIFOSIZE 0x002210 146 #define ACP_I2S_TDM1_RX_DMA_SIZE 0x002214 147 #define ACP_I2S_TDM1_RX_LINEARPOSITIONCNTR_HIGH 0x002218 148 #define ACP_I2S_TDM1_RX_LINEARPOSITIONCNTR_LOW 0x00221C 149 #define ACP_I2S_TDM1_RX_INTR_WATERMARK_SIZE 0x002220 150 #define ACP_I2S_TDM1_TX_RINGBUFADDR 0x002224 151 #define ACP_I2S_TDM1_TX_RINGBUFSIZE 0x002228 152 #define ACP_I2S_TDM1_TX_LINKPOSITIONCNTR 0x00222C 153 #define ACP_I2S_TDM1_TX_FIFOADDR 0x002230 154 #define ACP_I2S_TDM1_TX_FIFOSIZE 0x002234 155 #define ACP_I2S_TDM1_TX_DMA_SIZE 0x002238 156 #define ACP_I2S_TDM1_TX_LINEARPOSITIONCNTR_HIGH 0x00223C 157 #define ACP_I2S_TDM1_TX_LINEARPOSITIONCNTR_LOW 0x002240 158 #define ACP_I2S_TDM1_TX_INTR_WATERMARK_SIZE 0x002244 159 #define ACP_I2S_TDM1_POS_TRACK_TX_CTRL 0x002248 160 #define ACP_I2S_TDM1_TX_DMA_POS 0x00224C 161 #define ACP_I2S_TDM1_POS_TRACK_I2S_RX_CTRL 0x002250 162 #define ACP_I2S_TDM1_RX_DMA_POS 0x002254 163 #define ACP_I2S_TDM1_ERROR_STATUS 0x002258 164 #define ACP_I2S_TDM1_ERROR_MASK 0x00225C 165 #define ACP_I2S_TDM1_IER 0x002300 166 #define ACP_I2S_TDM1_IRER 0x002304 167 #define ACP_I2S_TDM1_RXFRMT 0x002308 168 #define ACP_I2S_TDM1_ITER 0x00230C 169 #define ACP_I2S_TDM1_TXFRMT 0x002310 170 #define ACP_I2S_TDM1_MSTRCLKGEN 0x002314 171 #define ACP_I2S_TDM1_OUTPUT_SPLIT_EN 0x002318 172 #define ACP_I2S_TDM1_WALLCLK_MISC 0x00231C 173 #define ACP_I2S_TDM1_WALL_CLK_COUNTER 0x002320 174 #define ACP_I2S_TDM1_WALLCLK_INTR_CNTL 0x002330 175 176 #define ACP_I2S_TDM2_RX_RINGBUFADDR 0x002400 177 #define ACP_I2S_TDM2_RX_RINGBUFSIZE 0x002404 178 #define ACP_I2S_TDM2_RX_LINKPOSITIONCNTR 0x002408 179 #define ACP_I2S_TDM2_RX_FIFOADDR 0x00240C 180 #define ACP_I2S_TDM2_RX_FIFOSIZE 0x002410 181 #define ACP_I2S_TDM2_RX_DMA_SIZE 0x002414 182 #define ACP_I2S_TDM2_RX_LINEARPOSITIONCNTR_HIGH 0x002418 183 #define ACP_I2S_TDM2_RX_LINEARPOSITIONCNTR_LOW 0x00241C 184 #define ACP_I2S_TDM2_RX_INTR_WATERMARK_SIZE 0x002420 185 #define ACP_I2S_TDM2_TX_RINGBUFADDR 0x002424 186 #define ACP_I2S_TDM2_TX_RINGBUFSIZE 0x002428 187 #define ACP_I2S_TDM2_TX_LINKPOSITIONCNTR 0x00242C 188 #define ACP_I2S_TDM2_TX_FIFOADDR 0x002430 189 #define ACP_I2S_TDM2_TX_FIFOSIZE 0x002434 190 #define ACP_I2S_TDM2_TX_DMA_SIZE 0x002438 191 #define ACP_I2S_TDM2_TX_LINEARPOSITIONCNTR_HIGH 0x00243C 192 #define ACP_I2S_TDM2_TX_LINEARPOSITIONCNTR_LOW 0x002440 193 #define ACP_I2S_TDM2_TX_INTR_WATERMARK_SIZE 0x002444 194 #define ACP_I2S_TDM2_POS_TRACK_TX_CTRL 0x002448 195 #define ACP_I2S_TDM2_TX_DMA_POS 0x00244C 196 #define ACP_I2S_TDM2_POS_TRACK_I2S_RX_CTRL 0x002450 197 #define ACP_I2S_TDM2_RX_DMA_POS 0x002454 198 #define ACP_I2S_TDM2_ERROR_STATUS 0x002458 199 #define ACP_I2S_TDM2_ERROR_MASK 0x00245C 200 #define ACP_I2S_TDM2_IER 0x002500 201 #define ACP_I2S_TDM2_IRER 0x002504 202 #define ACP_I2S_TDM2_RXFRMT 0x002508 203 #define ACP_I2S_TDM2_ITER 0x00250C 204 #define ACP_I2S_TDM2_TXFRMT 0x002510 205 #define ACP_I2S_TDM2_MSTRCLKGEN 0x002514 206 #define ACP_I2S_TDM2_OUTPUT_SPLIT_EN 0x002518 207 #define ACP_I2S_TDM2_WALLCLK_MISC 0x00251C 208 #define ACP_I2S_TDM2_WALL_CLK_COUNTER 0x002520 209 #define ACP_I2S_TDM2_WALLCLK_INTR_CNTL 0x002530 210 211 #define ACP_SW_CTRL_COUNT 0x004D00 212 #define ACP_SW_GSYNC_EN 0x004D04 213 #define ACP_SW_GSYNC_EN_PRE_SELECT 0x004D08 214 #define ACP_SW_GSYNC_DP_EN 0x004D0C 215 216 #define ACP_SW0_GLOBAL_CAPABILITIES 0x004E00 217 #define ACP_SW0_RX_DMA0_RINGBUFADDR 0x004E04 218 #define ACP_SW0_RX_DMA0_RINGBUFSIZE 0x004E08 219 #define ACP_SW0_RX_DMA0_FIFOADDR 0x004E0C 220 #define ACP_SW0_RX_DMA0_FIFOSIZE 0x004E10 221 #define ACP_SW0_RX_DMA0_BURST_SIZE 0x004E14 222 #define ACP_SW0_RX_DMA0_LINKPOSITIONCNTR 0x004E18 223 #define ACP_SW0_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x004E1C 224 #define ACP_SW0_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x004E20 225 #define ACP_SW0_RX_DMA0_INTR_WATERMARK_SIZE 0x004E24 226 #define ACP_SW0_RX_DMA1_RINGBUFADDR 0x004E28 227 #define ACP_SW0_RX_DMA1_RINGBUFSIZE 0x004E2C 228 #define ACP_SW0_RX_DMA1_FIFOADDR 0x004E30 229 #define ACP_SW0_RX_DMA1_FIFOSIZE 0x004E34 230 #define ACP_SW0_RX_DMA1_BURST_SIZE 0x004E38 231 #define ACP_SW0_RX_DMA1_LINKPOSITIONCNTR 0x004E3C 232 #define ACP_SW0_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x004E40 233 #define ACP_SW0_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x004E44 234 #define ACP_SW0_RX_DMA1_INTR_WATERMARK_SIZE 0x004E48 235 #define ACP_SW0_RX_DMA2_RINGBUFADDR 0x004E4C 236 #define ACP_SW0_RX_DMA2_RINGBUFSIZE 0x004E50 237 #define ACP_SW0_RX_DMA2_FIFOADDR 0x004E54 238 #define ACP_SW0_RX_DMA2_FIFOSIZE 0x004E58 239 #define ACP_SW0_RX_DMA2_BURST_SIZE 0x004E5C 240 #define ACP_SW0_RX_DMA2_LINKPOSITIONCNTR 0x004E60 241 #define ACP_SW0_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x004E64 242 #define ACP_SW0_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x004E68 243 #define ACP_SW0_RX_DMA2_INTR_WATERMARK_SIZE 0x004E6C 244 #define ACP_SW0_RX_DMA3_RINGBUFADDR 0x004E70 245 #define ACP_SW0_RX_DMA3_RINGBUFSIZE 0x004E74 246 #define ACP_SW0_RX_DMA3_FIFOADDR 0x004E78 247 #define ACP_SW0_RX_DMA3_FIFOSIZE 0x004E7C 248 #define ACP_SW0_RX_DMA3_BURST_SIZE 0x004E80 249 #define ACP_SW0_RX_DMA3_LINKPOSITIONCNTR 0x004E84 250 #define ACP_SW0_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x004E88 251 #define ACP_SW0_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x004E8C 252 #define ACP_SW0_RX_DMA3_INTR_WATERMARK_SIZE 0x004E90 253 #define ACP_SW0_RX_DMA4_RINGBUFADDR 0x004E94 254 #define ACP_SW0_RX_DMA4_RINGBUFSIZE 0x004E98 255 #define ACP_SW0_RX_DMA4_FIFOADDR 0x004E9C 256 #define ACP_SW0_RX_DMA4_FIFOSIZE 0x004EA0 257 #define ACP_SW0_RX_DMA4_BURST_SIZE 0x004EA4 258 #define ACP_SW0_RX_DMA4_LINKPOSITIONCNTR 0x004EA8 259 #define ACP_SW0_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x004EAC 260 #define ACP_SW0_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x004EB0 261 #define ACP_SW0_RX_DMA4_INTR_WATERMARK_SIZE 0x004EB4 262 #define ACP_SW0_RX_DMA5_RINGBUFADDR 0x004EB8 263 #define ACP_SW0_RX_DMA5_RINGBUFSIZE 0x004EBC 264 #define ACP_SW0_RX_DMA5_FIFOADDR 0x004EC0 265 #define ACP_SW0_RX_DMA5_FIFOSIZE 0x004EC4 266 #define ACP_SW0_RX_DMA5_BURST_SIZE 0x004EC8 267 #define ACP_SW0_RX_DMA5_LINKPOSITIONCNTR 0x004ECC 268 #define ACP_SW0_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x004ED0 269 #define ACP_SW0_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x004ED4 270 #define ACP_SW0_RX_DMA5_INTR_WATERMARK_SIZE 0x004ED8 271 #define ACP_SW0_RX_DMA6_RINGBUFADDR 0x004EDC 272 #define ACP_SW0_RX_DMA6_RINGBUFSIZE 0x004EE0 273 #define ACP_SW0_RX_DMA6_FIFOADDR 0x004EE4 274 #define ACP_SW0_RX_DMA6_FIFOSIZE 0x004EE8 275 #define ACP_SW0_RX_DMA6_BURST_SIZE 0x004EEC 276 #define ACP_SW0_RX_DMA6_LINKPOSITIONCNTR 0x004EF0 277 #define ACP_SW0_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x004EF4 278 #define ACP_SW0_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x004EF8 279 #define ACP_SW0_RX_DMA6_INTR_WATERMARK_SIZE 0x004EFC 280 #define ACP_SW0_RX_DMA7_RINGBUFADDR 0x004F00 281 #define ACP_SW0_RX_DMA7_RINGBUFSIZE 0x004F04 282 #define ACP_SW0_RX_DMA7_FIFOADDR 0x004F08 283 #define ACP_SW0_RX_DMA7_FIFOSIZE 0x004F0C 284 #define ACP_SW0_RX_DMA7_BURST_SIZE 0x004F10 285 #define ACP_SW0_RX_DMA7_LINKPOSITIONCNTR 0x004F14 286 #define ACP_SW0_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x004F18 287 #define ACP_SW0_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x004F1C 288 #define ACP_SW0_RX_DMA7_INTR_WATERMARK_SIZE 0x004F20 289 #define ACP_SW0_TX_DMA0_RINGBUFADDR 0x004F24 290 #define ACP_SW0_TX_DMA0_RINGBUFSIZE 0x004F28 291 #define ACP_SW0_TX_DMA0_FIFOADDR 0x004F2C 292 #define ACP_SW0_TX_DMA0_FIFOSIZE 0x004F30 293 #define ACP_SW0_TX_DMA0_BURST_SIZE 0x004F34 294 #define ACP_SW0_TX_DMA0_LINKPOSITIONCNTR 0x004F38 295 #define ACP_SW0_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x004F3C 296 #define ACP_SW0_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x004F40 297 #define ACP_SW0_TX_DMA0_INTR_WATERMARK_SIZE 0x004F44 298 #define ACP_SW0_TX_DMA1_RINGBUFADDR 0x004F48 299 #define ACP_SW0_TX_DMA1_RINGBUFSIZE 0x004F4C 300 #define ACP_SW0_TX_DMA1_FIFOADDR 0x004F50 301 #define ACP_SW0_TX_DMA1_FIFOSIZE 0x004F54 302 #define ACP_SW0_TX_DMA1_BURST_SIZE 0x004F58 303 #define ACP_SW0_TX_DMA1_LINKPOSITIONCNTR 0x004F5C 304 #define ACP_SW0_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x004F60 305 #define ACP_SW0_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x004F64 306 #define ACP_SW0_TX_DMA1_INTR_WATERMARK_SIZE 0x004F68 307 #define ACP_SW0_TX_DMA2_RINGBUFADDR 0x004F6C 308 #define ACP_SW0_TX_DMA2_RINGBUFSIZE 0x004F70 309 #define ACP_SW0_TX_DMA2_FIFOADDR 0x004F74 310 #define ACP_SW0_TX_DMA2_FIFOSIZE 0x004F78 311 #define ACP_SW0_TX_DMA2_BURST_SIZE 0x004F7C 312 #define ACP_SW0_TX_DMA2_LINKPOSITIONCNTR 0x004F80 313 #define ACP_SW0_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x004F84 314 #define ACP_SW0_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x004F88 315 #define ACP_SW0_TX_DMA2_INTR_WATERMARK_SIZE 0x004F8C 316 #define ACP_SW0_TX_DMA3_RINGBUFADDR 0x004F90 317 #define ACP_SW0_TX_DMA3_RINGBUFSIZE 0x004F94 318 #define ACP_SW0_TX_DMA3_FIFOADDR 0x004F98 319 #define ACP_SW0_TX_DMA3_FIFOSIZE 0x004F9C 320 #define ACP_SW0_TX_DMA3_BURST_SIZE 0x004FA0 321 #define ACP_SW0_TX_DMA3_LINKPOSITIONCNTR 0x004FA4 322 #define ACP_SW0_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x004FA8 323 #define ACP_SW0_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x004FAC 324 #define ACP_SW0_TX_DMA3_INTR_WATERMARK_SIZE 0x004FB0 325 #define ACP_SW0_TX_DMA4_RINGBUFADDR 0x004FB4 326 #define ACP_SW0_TX_DMA4_RINGBUFSIZE 0x004FB8 327 #define ACP_SW0_TX_DMA4_FIFOADDR 0x004FBC 328 #define ACP_SW0_TX_DMA4_FIFOSIZE 0x004FC0 329 #define ACP_SW0_TX_DMA4_BURST_SIZE 0x004FC4 330 #define ACP_SW0_TX_DMA4_LINKPOSITIONCNTR 0x004FC8 331 #define ACP_SW0_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x004FCC 332 #define ACP_SW0_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x004FD0 333 #define ACP_SW0_TX_DMA4_INTR_WATERMARK_SIZE 0x004FD4 334 #define ACP_SW0_TX_DMA5_RINGBUFADDR 0x004FD8 335 #define ACP_SW0_TX_DMA5_RINGBUFSIZE 0x004FDC 336 #define ACP_SW0_TX_DMA5_FIFOADDR 0x004FE0 337 #define ACP_SW0_TX_DMA5_FIFOSIZE 0x004FE4 338 #define ACP_SW0_TX_DMA5_BURST_SIZE 0x004FE8 339 #define ACP_SW0_TX_DMA5_LINKPOSITIONCNTR 0x004FEC 340 #define ACP_SW0_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x004FF0 341 #define ACP_SW0_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x004FF4 342 #define ACP_SW0_TX_DMA5_INTR_WATERMARK_SIZE 0x004FF8 343 #define ACP_SW0_TX_DMA6_RINGBUFADDR 0x004FFC 344 #define ACP_SW0_TX_DMA6_RINGBUFSIZE 0x005000 345 #define ACP_SW0_TX_DMA6_FIFOADDR 0x005004 346 #define ACP_SW0_TX_DMA6_FIFOSIZE 0x005008 347 #define ACP_SW0_TX_DMA6_BURST_SIZE 0x00500C 348 #define ACP_SW0_TX_DMA6_LINKPOSITIONCNTR 0x005010 349 #define ACP_SW0_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x005014 350 #define ACP_SW0_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x005018 351 #define ACP_SW0_TX_DMA6_INTR_WATERMARK_SIZE 0x00501C 352 #define ACP_SW0_TX_DMA7_RINGBUFADDR 0x005020 353 #define ACP_SW0_TX_DMA7_RINGBUFSIZE 0x005024 354 #define ACP_SW0_TX_DMA7_FIFOADDR 0x005028 355 #define ACP_SW0_TX_DMA7_FIFOSIZE 0x00502C 356 #define ACP_SW0_TX_DMA7_BURST_SIZE 0x005030 357 #define ACP_SW0_TX_DMA7_LINKPOSITIONCNTR 0x005034 358 #define ACP_SW0_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x005038 359 #define ACP_SW0_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00503C 360 #define ACP_SW0_TX_DMA7_INTR_WATERMARK_SIZE 0x005040 361 #define ACP_SW0_RX_DMA0_POS_TRACK 0x005044 362 #define ACP_SW0_RX_DMA0_POS 0x005048 363 #define ACP_SW0_RX_DMA1_POS_TRACK 0x00504C 364 #define ACP_SW0_RX_DMA1_POS 0x005050 365 #define ACP_SW0_RX_DMA2_POS_TRACK 0x005054 366 #define ACP_SW0_RX_DMA2_POS 0x005058 367 #define ACP_SW0_RX_DMA3_POS_TRACK 0x00505C 368 #define ACP_SW0_RX_DMA3_POS 0x005060 369 #define ACP_SW0_RX_DMA4_POS_TRACK 0x005064 370 #define ACP_SW0_RX_DMA4_POS 0x005068 371 #define ACP_SW0_RX_DMA5_POS_TRACK 0x00506C 372 #define ACP_SW0_RX_DMA5_POS 0x005070 373 #define ACP_SW0_RX_DMA6_POS_TRACK 0x005074 374 #define ACP_SW0_RX_DMA6_POS 0x005078 375 #define ACP_SW0_RX_DMA7_POS_TRACK 0x00507C 376 #define ACP_SW0_RX_DMA7_POS 0x005080 377 #define ACP_SW0_TX_DMA0_POS_TRACK 0x005084 378 #define ACP_SW0_TX_DMA0_POS 0x005088 379 #define ACP_SW0_TX_DMA1_POS_TRACK 0x00508C 380 #define ACP_SW0_TX_DMA1_POS 0x005090 381 #define ACP_SW0_TX_DMA2_POS_TRACK 0x005094 382 #define ACP_SW0_TX_DMA2_POS 0x005098 383 #define ACP_SW0_TX_DMA3_POS_TRACK 0x00509C 384 #define ACP_SW0_TX_DMA3_POS 0x0050A0 385 #define ACP_SW0_TX_DMA4_POS_TRACK 0x0050A4 386 #define ACP_SW0_TX_DMA4_POS 0x0050A8 387 #define ACP_SW0_TX_DMA5_POS_TRACK 0x0050AC 388 #define ACP_SW0_TX_DMA5_POS 0x0050B0 389 #define ACP_SW0_TX_DMA6_POS_TRACK 0x0050B4 390 #define ACP_SW0_TX_DMA6_POS 0x0050B8 391 #define ACP_SW0_TX_DMA7_POS_TRACK 0x0050BC 392 #define ACP_SW0_TX_DMA7_POS 0x0050C0 393 #define ACP_SW0_FIFO_ERROR_REASON 0x0050C4 394 #define ACP_SW0_FIFO_ERROR_INTR_MASK 0x0050C8 395 #define ACP_SW0_ERROR_REASON1 0x0050CC 396 #define ACP_SW0_ERROR_INTR_MASK1 0x0050D0 397 #define ACP_SW0_ERROR_REASON2 0x0050D4 398 #define ACP_SW0_ERROR_INTR_MASK2 0x0050D8 399 400 #define ACP_SW0_CORB_BASE_ADDRESS 0x005100 401 #define ACP_SW0_CORB_WRITE_POINTER 0x005104 402 #define ACP_SW0_CORB_READ_POINTER 0x005108 403 #define ACP_SW0_CORB_CONTROL 0x00510C 404 #define ACP_SW0_CORB_SIZE 0x005114 405 #define ACP_SW0_RIRB_BASE_ADDRESS 0x005118 406 #define ACP_SW0_RIRB_WRITE_POINTER 0x00511C 407 #define ACP_SW0_RIRB_RESPONSE_INTERRUPT_COUNT 0x005120 408 #define ACP_SW0_RIRB_CONTROL 0x005124 409 #define ACP_SW0_RIRB_SIZE 0x005128 410 #define ACP_SW0_RIRB_FIFO_MIN_THDL 0x00512C 411 #define ACP_SW0_IMM_CMD_UPPER_WORD 0x005130 412 #define ACP_SW0_IMM_CMD_LOWER_QWORD 0x005134 413 #define ACP_SW0_IMM_RESP_UPPER_WORD 0x005138 414 #define ACP_SW0_IMM_RESP_LOWER_QWORD 0x00513C 415 #define ACP_SW0_IMM_CMD_STS 0x005140 416 #define ACP_SW0_BRA_BASE_ADDRESS 0x005144 417 #define ACP_SW0_BRA_TRANSFER_SIZE 0x005148 418 #define ACP_SW0_BRA_DMA_BUSY 0x00514C 419 #define ACP_SW0_BRA_RESP 0x005150 420 #define ACP_SW0_BRA_RESP_FRAME_ADDR 0x005154 421 #define ACP_SW0_BRA_CURRENT_TRANSFER_SIZE 0x005158 422 #define ACP_SW0_STATE_CHANGE_STATUS_0TO7 0x00515C 423 #define ACP_SW0_STATE_CHANGE_STATUS_8TO11 0x005160 424 #define ACP_SW0_STATE_CHANGE_STATUS_MASK_0TO7 0x005164 425 #define ACP_SW0_STATE_CHANGE_STATUS_MASK_8TO11 0x005168 426 #define ACP_SW0_CLK_FREQUENCY_CTRL_BANK0 0x00516C 427 #define ACP_SW0_CLK_FREQUENCY_CTRL_BANK1 0x005170 428 #define ACP_SW0_ERROR_INTR_MASK 0x005174 429 #define ACP_SW0_PHY_TEST_MODE_DATA_OFF 0x005178 430 #define ACP_SW0_DATA_TO_PDM_EN 0x00517C 431 432 #define ACP_SW0_EN 0x005200 433 #define ACP_SW0_EN_STATUS 0x005204 434 #define ACP_SW0_FRAMESIZE_BANK0 0x005208 435 #define ACP_SW0_FRAMESIZE_BANK1 0x00520C 436 #define ACP_SW0_SSP_COUNTER 0x005210 437 #define ACP_SW0_TX_STREAM0_EN 0x005214 438 #define ACP_SW0_TX_STREAM1_EN 0x005218 439 #define ACP_SW0_TX_STREAM2_EN 0x00521C 440 #define ACP_SW0_TX_STREAM3_EN 0x005220 441 #define ACP_SW0_TX_STREAM4_EN 0x005224 442 #define ACP_SW0_TX_STREAM5_EN 0x005228 443 #define ACP_SW0_TX_STREAM6_EN 0x00522C 444 #define ACP_SW0_TX_STREAM7_EN 0x005230 445 #define ACP_SW0_TX_STREAM0_EN_STATUS 0x005234 446 #define ACP_SW0_TX_STREAM1_EN_STATUS 0x005238 447 #define ACP_SW0_TX_STREAM2_EN_STATUS 0x00523C 448 #define ACP_SW0_TX_STREAM3_EN_STATUS 0x005240 449 #define ACP_SW0_TX_STREAM4_EN_STATUS 0x005244 450 #define ACP_SW0_TX_STREAM5_EN_STATUS 0x005248 451 #define ACP_SW0_TX_STREAM6_EN_STATUS 0x00524C 452 #define ACP_SW0_TX_STREAM7_EN_STATUS 0x005250 453 #define ACP_SW0_TX_DP0_FRAME_FORMAT 0x005254 454 #define ACP_SW0_TX_DP1_FRAME_FORMAT 0x005258 455 #define ACP_SW0_TX_DP2_FRAME_FORMAT 0x00525C 456 #define ACP_SW0_TX_DP3_FRAME_FORMAT 0x005260 457 #define ACP_SW0_TX_DP4_FRAME_FORMAT 0x005264 458 #define ACP_SW0_TX_DP5_FRAME_FORMAT 0x005268 459 #define ACP_SW0_TX_DP6_FRAME_FORMAT 0x00526C 460 #define ACP_SW0_TX_DP7_FRAME_FORMAT 0x005270 461 #define ACP_SW0_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x005280 462 #define ACP_SW0_TX_DP0_0_HCTRL_BANK0 0x005284 463 #define ACP_SW0_TX_DP0_0_HCTRL_OFFSET_BANK0 0x005288 464 #define ACP_SW0_TX_DP0_0_LANE_CTRL_BANK0 0x00528C 465 #define ACP_SW0_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x005290 466 #define ACP_SW0_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005294 467 #define ACP_SW0_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x005298 468 #define ACP_SW0_TX_DP0_0_HCTRL_BANK1 0x00529C 469 #define ACP_SW0_TX_DP0_0_HCTRL_OFFSET_BANK1 0x0052A0 470 #define ACP_SW0_TX_DP0_0_LANE_CTRL_BANK1 0x0052A4 471 #define ACP_SW0_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x0052A8 472 #define ACP_SW0_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0052AC 473 #define ACP_SW0_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x0052B0 474 #define ACP_SW0_TX_DP0_1_HCTRL_BANK0 0x0052B4 475 #define ACP_SW0_TX_DP0_1_HCTRL_OFFSET_BANK0 0x0052B8 476 #define ACP_SW0_TX_DP0_1_LANE_CTRL_BANK0 0x0052BC 477 #define ACP_SW0_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x0052C0 478 #define ACP_SW0_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0052C4 479 #define ACP_SW0_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x0052C8 480 #define ACP_SW0_TX_DP0_1_HCTRL_BANK1 0x0052CC 481 #define ACP_SW0_TX_DP0_1_HCTRL_OFFSET_BANK1 0x0052D0 482 #define ACP_SW0_TX_DP0_1_LANE_CTRL_BANK1 0x0052D4 483 #define ACP_SW0_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x0052D8 484 #define ACP_SW0_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0052DC 485 #define ACP_SW0_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x0052E0 486 #define ACP_SW0_TX_DP0_2_HCTRL_BANK0 0x0052E4 487 #define ACP_SW0_TX_DP0_2_HCTRL_OFFSET_BANK0 0x0052E8 488 #define ACP_SW0_TX_DP0_2_LANE_CTRL_BANK0 0x0052EC 489 #define ACP_SW0_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x0052F0 490 #define ACP_SW0_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0052F4 491 #define ACP_SW0_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x0052F8 492 #define ACP_SW0_TX_DP0_2_HCTRL_BANK1 0x0052FC 493 #define ACP_SW0_TX_DP0_2_HCTRL_OFFSET_BANK1 0x005300 494 #define ACP_SW0_TX_DP0_2_LANE_CTRL_BANK1 0x005304 495 #define ACP_SW0_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x005308 496 #define ACP_SW0_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00530C 497 #define ACP_SW0_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x005310 498 #define ACP_SW0_TX_DP0_3_HCTRL_BANK0 0x005314 499 #define ACP_SW0_TX_DP0_3_HCTRL_OFFSET_BANK0 0x005318 500 #define ACP_SW0_TX_DP0_3_LANE_CTRL_BANK0 0x00531C 501 #define ACP_SW0_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x005320 502 #define ACP_SW0_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005324 503 #define ACP_SW0_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x005328 504 #define ACP_SW0_TX_DP0_3_HCTRL_BANK1 0x00532C 505 #define ACP_SW0_TX_DP0_3_HCTRL_OFFSET_BANK1 0x005330 506 #define ACP_SW0_TX_DP0_3_LANE_CTRL_BANK1 0x005334 507 #define ACP_SW0_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x005338 508 #define ACP_SW0_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00533C 509 #define ACP_SW0_TX_DP1_SAMPLEINTERVAL_BANK0 0x005370 510 #define ACP_SW0_TX_DP1_HCTRL_BANK0 0x005374 511 #define ACP_SW0_TX_DP1_HCTRL_OFFSET_BANK0 0x005378 512 #define ACP_SW0_TX_DP1_LANE_CTRL_BANK0 0x00537C 513 #define ACP_SW0_TX_DP1_CHANNEL_ENABLE_BANK0 0x005380 514 #define ACP_SW0_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005384 515 #define ACP_SW0_TX_DP1_SAMPLEINTERVAL_BANK1 0x005388 516 #define ACP_SW0_TX_DP1_HCTRL_BANK1 0x00538C 517 #define ACP_SW0_TX_DP1_HCTRL_OFFSET_BANK1 0x005390 518 #define ACP_SW0_TX_DP1_LANE_CTRL_BANK1 0x005394 519 #define ACP_SW0_TX_DP1_CHANNEL_ENABLE_BANK1 0x005398 520 #define ACP_SW0_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00539C 521 #define ACP_SW0_TX_DP2_SAMPLEINTERVAL_BANK0 0x0053A0 522 #define ACP_SW0_TX_DP2_HCTRL_BANK0 0x0053A4 523 #define ACP_SW0_TX_DP2_HCTRL_OFFSET_BANK0 0x0053A8 524 #define ACP_SW0_TX_DP2_LANE_CTRL_BANK0 0x0053AC 525 #define ACP_SW0_TX_DP2_CHANNEL_ENABLE_BANK0 0x0053B0 526 #define ACP_SW0_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0053B4 527 #define ACP_SW0_TX_DP2_SAMPLEINTERVAL_BANK1 0x0053B8 528 #define ACP_SW0_TX_DP2_HCTRL_BANK1 0x0053BC 529 #define ACP_SW0_TX_DP2_HCTRL_OFFSET_BANK1 0x0053C0 530 #define ACP_SW0_TX_DP2_LANE_CTRL_BANK1 0x0053C4 531 #define ACP_SW0_TX_DP2_CHANNEL_ENABLE_BANK1 0x0053C8 532 #define ACP_SW0_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0053CC 533 #define ACP_SW0_TX_DP3_SAMPLEINTERVAL_BANK0 0x0053D0 534 #define ACP_SW0_TX_DP3_HCTRL_BANK0 0x0053D4 535 #define ACP_SW0_TX_DP3_HCTRL_OFFSET_BANK0 0x0053D8 536 #define ACP_SW0_TX_DP3_LANE_CTRL_BANK0 0x0053DC 537 #define ACP_SW0_TX_DP3_CHANNEL_ENABLE_BANK0 0x0053E0 538 #define ACP_SW0_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0053E4 539 #define ACP_SW0_TX_DP3_SAMPLEINTERVAL_BANK1 0x0053E8 540 #define ACP_SW0_TX_DP3_HCTRL_BANK1 0x0053EC 541 #define ACP_SW0_TX_DP3_HCTRL_OFFSET_BANK1 0x0053F0 542 #define ACP_SW0_TX_DP3_LANE_CTRL_BANK1 0x0053F4 543 #define ACP_SW0_TX_DP3_CHANNEL_ENABLE_BANK1 0x0053F8 544 #define ACP_SW0_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0053FC 545 #define ACP_SW0_TX_DP4_SAMPLEINTERVAL_BANK0 0x005400 546 #define ACP_SW0_TX_DP4_HCTRL_BANK0 0x005404 547 #define ACP_SW0_TX_DP4_HCTRL_OFFSET_BANK0 0x005408 548 #define ACP_SW0_TX_DP4_LANE_CTRL_BANK0 0x00540C 549 #define ACP_SW0_TX_DP4_CHANNEL_ENABLE_BANK0 0x005410 550 #define ACP_SW0_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005414 551 #define ACP_SW0_TX_DP4_SAMPLEINTERVAL_BANK1 0x005418 552 #define ACP_SW0_TX_DP4_HCTRL_BANK1 0x00541C 553 #define ACP_SW0_TX_DP4_HCTRL_OFFSET_BANK1 0x005420 554 #define ACP_SW0_TX_DP4_LANE_CTRL_BANK1 0x005424 555 #define ACP_SW0_TX_DP4_CHANNEL_ENABLE_BANK1 0x005428 556 #define ACP_SW0_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00542C 557 #define ACP_SW0_TX_DP5_SAMPLEINTERVAL_BANK0 0x005430 558 #define ACP_SW0_TX_DP5_HCTRL_BANK0 0x005434 559 #define ACP_SW0_TX_DP5_HCTRL_OFFSET_BANK0 0x005438 560 #define ACP_SW0_TX_DP5_LANE_CTRL_BANK0 0x00543C 561 #define ACP_SW0_TX_DP5_CHANNEL_ENABLE_BANK0 0x005440 562 #define ACP_SW0_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005444 563 #define ACP_SW0_TX_DP5_SAMPLEINTERVAL_BANK1 0x005448 564 #define ACP_SW0_TX_DP5_HCTRL_BANK1 0x00544C 565 #define ACP_SW0_TX_DP5_HCTRL_OFFSET_BANK1 0x005450 566 #define ACP_SW0_TX_DP5_LANE_CTRL_BANK1 0x005454 567 #define ACP_SW0_TX_DP5_CHANNEL_ENABLE_BANK1 0x005458 568 #define ACP_SW0_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00545C 569 #define ACP_SW0_TX_DP6_SAMPLEINTERVAL_BANK0 0x005460 570 #define ACP_SW0_TX_DP6_HCTRL_BANK0 0x005464 571 #define ACP_SW0_TX_DP6_HCTRL_OFFSET_BANK0 0x005468 572 #define ACP_SW0_TX_DP6_LANE_CTRL_BANK0 0x00546C 573 #define ACP_SW0_TX_DP6_CHANNEL_ENABLE_BANK0 0x005470 574 #define ACP_SW0_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005474 575 #define ACP_SW0_TX_DP6_SAMPLEINTERVAL_BANK1 0x005478 576 #define ACP_SW0_TX_DP6_HCTRL_BANK1 0x00547C 577 #define ACP_SW0_TX_DP6_HCTRL_OFFSET_BANK1 0x005480 578 #define ACP_SW0_TX_DP6_LANE_CTRL_BANK1 0x005484 579 #define ACP_SW0_TX_DP6_CHANNEL_ENABLE_BANK1 0x005488 580 #define ACP_SW0_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00548C 581 #define ACP_SW0_TX_DP7_SAMPLEINTERVAL_BANK0 0x005490 582 #define ACP_SW0_TX_DP7_HCTRL_BANK0 0x005494 583 #define ACP_SW0_TX_DP7_HCTRL_OFFSET_BANK0 0x005498 584 #define ACP_SW0_TX_DP7_LANE_CTRL_BANK0 0x00549C 585 #define ACP_SW0_TX_DP7_CHANNEL_ENABLE_BANK0 0x0054A0 586 #define ACP_SW0_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0054A4 587 #define ACP_SW0_TX_DP7_SAMPLEINTERVAL_BANK1 0x0054A8 588 #define ACP_SW0_TX_DP7_HCTRL_BANK1 0x0054AC 589 #define ACP_SW0_TX_DP7_HCTRL_OFFSET_BANK1 0x0054B0 590 #define ACP_SW0_TX_DP7_LANE_CTRL_BANK1 0x0054B4 591 #define ACP_SW0_TX_DP7_CHANNEL_ENABLE_BANK1 0x0054B8 592 #define ACP_SW0_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0054BC 593 #define ACP_SW0_RX_STREAM0_EN 0x005514 594 #define ACP_SW0_RX_STREAM1_EN 0x005518 595 #define ACP_SW0_RX_STREAM2_EN 0x00551C 596 #define ACP_SW0_RX_STREAM3_EN 0x005520 597 #define ACP_SW0_RX_STREAM4_EN 0x005524 598 #define ACP_SW0_RX_STREAM5_EN 0x005528 599 #define ACP_SW0_RX_STREAM6_EN 0x00552C 600 #define ACP_SW0_RX_STREAM7_EN 0x005530 601 #define ACP_SW0_RX_STREAM0_EN_STATUS 0x005534 602 #define ACP_SW0_RX_STREAM1_EN_STATUS 0x005538 603 #define ACP_SW0_RX_STREAM2_EN_STATUS 0x00553C 604 #define ACP_SW0_RX_STREAM3_EN_STATUS 0x005540 605 #define ACP_SW0_RX_STREAM4_EN_STATUS 0x005544 606 #define ACP_SW0_RX_STREAM5_EN_STATUS 0x005548 607 #define ACP_SW0_RX_STREAM6_EN_STATUS 0x00554C 608 #define ACP_SW0_RX_STREAM7_EN_STATUS 0x005550 609 #define ACP_SW0_RX_DP0_FRAME_FORMAT 0x005554 610 #define ACP_SW0_RX_DP1_FRAME_FORMAT 0x005558 611 #define ACP_SW0_RX_DP2_FRAME_FORMAT 0x00555C 612 #define ACP_SW0_RX_DP3_FRAME_FORMAT 0x005560 613 #define ACP_SW0_RX_DP4_FRAME_FORMAT 0x005564 614 #define ACP_SW0_RX_DP5_FRAME_FORMAT 0x005568 615 #define ACP_SW0_RX_DP6_FRAME_FORMAT 0x00556C 616 #define ACP_SW0_RX_DP7_FRAME_FORMAT 0x005570 617 #define ACP_SW0_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x005580 618 #define ACP_SW0_RX_DP0_0_HCTRL_BANK0 0x005584 619 #define ACP_SW0_RX_DP0_0_HCTRL_OFFSET_BANK0 0x005588 620 #define ACP_SW0_RX_DP0_0_LANE_CTRL_BANK0 0x00558C 621 #define ACP_SW0_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x005590 622 #define ACP_SW0_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005594 623 #define ACP_SW0_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x005598 624 #define ACP_SW0_RX_DP0_0_HCTRL_BANK1 0x00559C 625 #define ACP_SW0_RX_DP0_0_HCTRL_OFFSET_BANK1 0x0055A0 626 #define ACP_SW0_RX_DP0_0_LANE_CTRL_BANK1 0x0055A4 627 #define ACP_SW0_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x0055A8 628 #define ACP_SW0_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0055AC 629 #define ACP_SW0_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x0055B0 630 #define ACP_SW0_RX_DP0_1_HCTRL_BANK0 0x0055B4 631 #define ACP_SW0_RX_DP0_1_HCTRL_OFFSET_BANK0 0x0055B8 632 #define ACP_SW0_RX_DP0_1_LANE_CTRL_BANK0 0x0055BC 633 #define ACP_SW0_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x0055C0 634 #define ACP_SW0_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0055C4 635 #define ACP_SW0_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x0055C8 636 #define ACP_SW0_RX_DP0_1_HCTRL_BANK1 0x0055CC 637 #define ACP_SW0_RX_DP0_1_HCTRL_OFFSET_BANK1 0x0055D0 638 #define ACP_SW0_RX_DP0_1_LANE_CTRL_BANK1 0x0055D4 639 #define ACP_SW0_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x0055D8 640 #define ACP_SW0_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0055DC 641 #define ACP_SW0_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x0055E0 642 #define ACP_SW0_RX_DP0_2_HCTRL_BANK0 0x0055E4 643 #define ACP_SW0_RX_DP0_2_HCTRL_OFFSET_BANK0 0x0055E8 644 #define ACP_SW0_RX_DP0_2_LANE_CTRL_BANK0 0x0055EC 645 #define ACP_SW0_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x0055F0 646 #define ACP_SW0_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0055F4 647 #define ACP_SW0_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x0055F8 648 #define ACP_SW0_RX_DP0_2_HCTRL_BANK1 0x0055FC 649 #define ACP_SW0_RX_DP0_2_HCTRL_OFFSET_BANK1 0x005600 650 #define ACP_SW0_RX_DP0_2_LANE_CTRL_BANK1 0x005604 651 #define ACP_SW0_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x005608 652 #define ACP_SW0_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00560C 653 #define ACP_SW0_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x005610 654 #define ACP_SW0_RX_DP0_3_HCTRL_BANK0 0x005614 655 #define ACP_SW0_RX_DP0_3_HCTRL_OFFSET_BANK0 0x005618 656 #define ACP_SW0_RX_DP0_3_LANE_CTRL_BANK0 0x00561C 657 #define ACP_SW0_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x005620 658 #define ACP_SW0_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005624 659 #define ACP_SW0_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x005628 660 #define ACP_SW0_RX_DP0_3_HCTRL_BANK1 0x00562C 661 #define ACP_SW0_RX_DP0_3_HCTRL_OFFSET_BANK1 0x005630 662 #define ACP_SW0_RX_DP0_3_LANE_CTRL_BANK1 0x005634 663 #define ACP_SW0_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x005638 664 #define ACP_SW0_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00563C 665 #define ACP_SW0_RX_DP1_SAMPLEINTERVAL_BANK0 0x005670 666 #define ACP_SW0_RX_DP1_HCTRL_BANK0 0x005674 667 #define ACP_SW0_RX_DP1_HCTRL_OFFSET_BANK0 0x005678 668 #define ACP_SW0_RX_DP1_LANE_CTRL_BANK0 0x00567C 669 #define ACP_SW0_RX_DP1_CHANNEL_ENABLE_BANK0 0x005680 670 #define ACP_SW0_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005684 671 #define ACP_SW0_RX_DP1_SAMPLEINTERVAL_BANK1 0x005688 672 #define ACP_SW0_RX_DP1_HCTRL_BANK1 0x00568C 673 #define ACP_SW0_RX_DP1_HCTRL_OFFSET_BANK1 0x005690 674 #define ACP_SW0_RX_DP1_LANE_CTRL_BANK1 0x005694 675 #define ACP_SW0_RX_DP1_CHANNEL_ENABLE_BANK1 0x005698 676 #define ACP_SW0_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00569C 677 #define ACP_SW0_RX_DP2_SAMPLEINTERVAL_BANK0 0x0056A0 678 #define ACP_SW0_RX_DP2_HCTRL_BANK0 0x0056A4 679 #define ACP_SW0_RX_DP2_HCTRL_OFFSET_BANK0 0x0056A8 680 #define ACP_SW0_RX_DP2_LANE_CTRL_BANK0 0x0056AC 681 #define ACP_SW0_RX_DP2_CHANNEL_ENABLE_BANK0 0x0056B0 682 #define ACP_SW0_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0056B4 683 #define ACP_SW0_RX_DP2_SAMPLEINTERVAL_BANK1 0x0056B8 684 #define ACP_SW0_RX_DP2_HCTRL_BANK1 0x0056BC 685 #define ACP_SW0_RX_DP2_HCTRL_OFFSET_BANK1 0x0056C0 686 #define ACP_SW0_RX_DP2_LANE_CTRL_BANK1 0x0056C4 687 #define ACP_SW0_RX_DP2_CHANNEL_ENABLE_BANK1 0x0056C8 688 #define ACP_SW0_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0056CC 689 #define ACP_SW0_RX_DP3_SAMPLEINTERVAL_BANK0 0x0056D0 690 #define ACP_SW0_RX_DP3_HCTRL_BANK0 0x0056D4 691 #define ACP_SW0_RX_DP3_HCTRL_OFFSET_BANK0 0x0056D8 692 #define ACP_SW0_RX_DP3_LANE_CTRL_BANK0 0x0056DC 693 #define ACP_SW0_RX_DP3_CHANNEL_ENABLE_BANK0 0x0056E0 694 #define ACP_SW0_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0056E4 695 #define ACP_SW0_RX_DP3_SAMPLEINTERVAL_BANK1 0x0056E8 696 #define ACP_SW0_RX_DP3_HCTRL_BANK1 0x0056EC 697 #define ACP_SW0_RX_DP3_HCTRL_OFFSET_BANK1 0x0056F0 698 #define ACP_SW0_RX_DP3_LANE_CTRL_BANK1 0x0056F4 699 #define ACP_SW0_RX_DP3_CHANNEL_ENABLE_BANK1 0x0056F8 700 #define ACP_SW0_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0056FC 701 #define ACP_SW0_RX_DP4_SAMPLEINTERVAL_BANK0 0x005700 702 #define ACP_SW0_RX_DP4_HCTRL_BANK0 0x005704 703 #define ACP_SW0_RX_DP4_HCTRL_OFFSET_BANK0 0x005708 704 #define ACP_SW0_RX_DP4_LANE_CTRL_BANK0 0x00570C 705 #define ACP_SW0_RX_DP4_CHANNEL_ENABLE_BANK0 0x005710 706 #define ACP_SW0_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005714 707 #define ACP_SW0_RX_DP4_SAMPLEINTERVAL_BANK1 0x005718 708 #define ACP_SW0_RX_DP4_HCTRL_BANK1 0x00571C 709 #define ACP_SW0_RX_DP4_HCTRL_OFFSET_BANK1 0x005720 710 #define ACP_SW0_RX_DP4_LANE_CTRL_BANK1 0x005724 711 #define ACP_SW0_RX_DP4_CHANNEL_ENABLE_BANK1 0x005728 712 #define ACP_SW0_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00572C 713 #define ACP_SW0_RX_DP5_SAMPLEINTERVAL_BANK0 0x005730 714 #define ACP_SW0_RX_DP5_HCTRL_BANK0 0x005734 715 #define ACP_SW0_RX_DP5_HCTRL_OFFSET_BANK0 0x005738 716 #define ACP_SW0_RX_DP5_LANE_CTRL_BANK0 0x00573C 717 #define ACP_SW0_RX_DP5_CHANNEL_ENABLE_BANK0 0x005740 718 #define ACP_SW0_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005744 719 #define ACP_SW0_RX_DP5_SAMPLEINTERVAL_BANK1 0x005748 720 #define ACP_SW0_RX_DP5_HCTRL_BANK1 0x00574C 721 #define ACP_SW0_RX_DP5_HCTRL_OFFSET_BANK1 0x005750 722 #define ACP_SW0_RX_DP5_LANE_CTRL_BANK1 0x005754 723 #define ACP_SW0_RX_DP5_CHANNEL_ENABLE_BANK1 0x005758 724 #define ACP_SW0_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00575C 725 #define ACP_SW0_RX_DP6_SAMPLEINTERVAL_BANK0 0x005760 726 #define ACP_SW0_RX_DP6_HCTRL_BANK0 0x005764 727 #define ACP_SW0_RX_DP6_HCTRL_OFFSET_BANK0 0x005768 728 #define ACP_SW0_RX_DP6_LANE_CTRL_BANK0 0x00576C 729 #define ACP_SW0_RX_DP6_CHANNEL_ENABLE_BANK0 0x005770 730 #define ACP_SW0_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005774 731 #define ACP_SW0_RX_DP6_SAMPLEINTERVAL_BANK1 0x005778 732 #define ACP_SW0_RX_DP6_HCTRL_BANK1 0x00577C 733 #define ACP_SW0_RX_DP6_HCTRL_OFFSET_BANK1 0x005780 734 #define ACP_SW0_RX_DP6_LANE_CTRL_BANK1 0x005784 735 #define ACP_SW0_RX_DP6_CHANNEL_ENABLE_BANK1 0x005788 736 #define ACP_SW0_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00578C 737 #define ACP_SW0_RX_DP7_SAMPLEINTERVAL_BANK0 0x005790 738 #define ACP_SW0_RX_DP7_HCTRL_BANK0 0x005794 739 #define ACP_SW0_RX_DP7_HCTRL_OFFSET_BANK0 0x005798 740 #define ACP_SW0_RX_DP7_LANE_CTRL_BANK0 0x00579C 741 #define ACP_SW0_RX_DP7_CHANNEL_ENABLE_BANK0 0x0057A0 742 #define ACP_SW0_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0057A4 743 #define ACP_SW0_RX_DP7_SAMPLEINTERVAL_BANK1 0x0057A8 744 #define ACP_SW0_RX_DP7_HCTRL_BANK1 0x0057AC 745 #define ACP_SW0_RX_DP7_HCTRL_OFFSET_BANK1 0x0057B0 746 #define ACP_SW0_RX_DP7_LANE_CTRL_BANK1 0x0057B4 747 #define ACP_SW0_RX_DP7_CHANNEL_ENABLE_BANK1 0x0057B8 748 #define ACP_SW0_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0057BC 749 #define ACP_SW0_BPT_PORT_EN 0x0057C0 750 #define ACP_SW0_BPT_PORT_EN_STATUS 0x0057C4 751 #define ACP_SW0_BPT_PORT_FRAME_FORMAT 0x0057C8 752 #define ACP_SW0_BPT_PORT_SAMPLEINTERVAL_BANK0 0x0057CC 753 #define ACP_SW0_BPT_PORT_HCTRL_BANK0 0x0057D0 754 #define ACP_SW0_BPT_PORT_OFFSET_BANK0 0x0057D4 755 #define ACP_SW0_BPT_PORT_LANE_SELECT_BANK0 0x0057D8 756 #define ACP_SW0_BPT_PORT_CHANNEL_ENABLE_BANK0 0x0057DC 757 #define ACP_SW0_BPT_PORT_SAMPLEINTERVAL_BANK1 0x0057E0 758 #define ACP_SW0_BPT_PORT_HCTRL_BANK1 0x0057E4 759 #define ACP_SW0_BPT_PORT_OFFSET_BANK1 0x0057E8 760 #define ACP_SW0_BPT_PORT_LANE_SELECT_BANK1 0x0057EC 761 #define ACP_SW0_BPT_PORT_CHANNEL_ENABLE_BANK1 0x0057F0 762 #define ACP_SW0_BPT_PORT_FIRST_BYTE_ADDR 0x0057F4 763 #define ACP_SW0_CLK_RESUME_CTRL 0x0057F8 764 #define ACP_SW0_CLK_RESUME_DELAY_CNTR 0x0057FC 765 #define ACP_SW0_BUS_RESET_CTRL 0x005800 766 #define ACP_SW0_PRBS_ERR_STATUS 0x005804 767 #define ACP_SW0_WALLCLK_MISC 0x005808 768 #define ACP_SW0_WALL_CLK_COUNTER 0x00580C 769 #define ACP_SW0_PING_STATUS_REGISTER_LOW 0x005810 770 #define ACP_SW0_PING_STATUS_REGISTER_HIGH 0x005814 771 #define ACP_SW0_PING_STATUS_CURRENT_BANK_SEL 0x005818 772 #define ACP_SW0_TZD_CHANGE 0x00581C 773 #define ACP_SW0_WALLCLK_INTR_CNTL 0x005820 774 775 #define ACP_SW1_GLOBAL_CAPABILITIES 0x006E00 776 #define ACP_SW1_RX_DMA0_RINGBUFADDR 0x006E04 777 #define ACP_SW1_RX_DMA0_RINGBUFSIZE 0x006E08 778 #define ACP_SW1_RX_DMA0_FIFOADDR 0x006E0C 779 #define ACP_SW1_RX_DMA0_FIFOSIZE 0x006E10 780 #define ACP_SW1_RX_DMA0_BURST_SIZE 0x006E14 781 #define ACP_SW1_RX_DMA0_LINKPOSITIONCNTR 0x006E18 782 #define ACP_SW1_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x006E1C 783 #define ACP_SW1_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x006E20 784 #define ACP_SW1_RX_DMA0_INTR_WATERMARK_SIZE 0x006E24 785 #define ACP_SW1_RX_DMA1_RINGBUFADDR 0x006E28 786 #define ACP_SW1_RX_DMA1_RINGBUFSIZE 0x006E2C 787 #define ACP_SW1_RX_DMA1_FIFOADDR 0x006E30 788 #define ACP_SW1_RX_DMA1_FIFOSIZE 0x006E34 789 #define ACP_SW1_RX_DMA1_BURST_SIZE 0x006E38 790 #define ACP_SW1_RX_DMA1_LINKPOSITIONCNTR 0x006E3C 791 #define ACP_SW1_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x006E40 792 #define ACP_SW1_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x006E44 793 #define ACP_SW1_RX_DMA1_INTR_WATERMARK_SIZE 0x006E48 794 #define ACP_SW1_RX_DMA2_RINGBUFADDR 0x006E4C 795 #define ACP_SW1_RX_DMA2_RINGBUFSIZE 0x006E50 796 #define ACP_SW1_RX_DMA2_FIFOADDR 0x006E54 797 #define ACP_SW1_RX_DMA2_FIFOSIZE 0x006E58 798 #define ACP_SW1_RX_DMA2_BURST_SIZE 0x006E5C 799 #define ACP_SW1_RX_DMA2_LINKPOSITIONCNTR 0x006E60 800 #define ACP_SW1_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x006E64 801 #define ACP_SW1_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x006E68 802 #define ACP_SW1_RX_DMA2_INTR_WATERMARK_SIZE 0x006E6C 803 #define ACP_SW1_RX_DMA3_RINGBUFADDR 0x006E70 804 #define ACP_SW1_RX_DMA3_RINGBUFSIZE 0x006E74 805 #define ACP_SW1_RX_DMA3_FIFOADDR 0x006E78 806 #define ACP_SW1_RX_DMA3_FIFOSIZE 0x006E7C 807 #define ACP_SW1_RX_DMA3_BURST_SIZE 0x006E80 808 #define ACP_SW1_RX_DMA3_LINKPOSITIONCNTR 0x006E84 809 #define ACP_SW1_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x006E88 810 #define ACP_SW1_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x006E8C 811 #define ACP_SW1_RX_DMA3_INTR_WATERMARK_SIZE 0x006E90 812 #define ACP_SW1_RX_DMA4_RINGBUFADDR 0x006E94 813 #define ACP_SW1_RX_DMA4_RINGBUFSIZE 0x006E98 814 #define ACP_SW1_RX_DMA4_FIFOADDR 0x006E9C 815 #define ACP_SW1_RX_DMA4_FIFOSIZE 0x006EA0 816 #define ACP_SW1_RX_DMA4_BURST_SIZE 0x006EA4 817 #define ACP_SW1_RX_DMA4_LINKPOSITIONCNTR 0x006EA8 818 #define ACP_SW1_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x006EAC 819 #define ACP_SW1_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x006EB0 820 #define ACP_SW1_RX_DMA4_INTR_WATERMARK_SIZE 0x006EB4 821 #define ACP_SW1_RX_DMA5_RINGBUFADDR 0x006EB8 822 #define ACP_SW1_RX_DMA5_RINGBUFSIZE 0x006EBC 823 #define ACP_SW1_RX_DMA5_FIFOADDR 0x006EC0 824 #define ACP_SW1_RX_DMA5_FIFOSIZE 0x006EC4 825 #define ACP_SW1_RX_DMA5_BURST_SIZE 0x006EC8 826 #define ACP_SW1_RX_DMA5_LINKPOSITIONCNTR 0x006ECC 827 #define ACP_SW1_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x006ED0 828 #define ACP_SW1_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x006ED4 829 #define ACP_SW1_RX_DMA5_INTR_WATERMARK_SIZE 0x006ED8 830 #define ACP_SW1_RX_DMA6_RINGBUFADDR 0x006EDC 831 #define ACP_SW1_RX_DMA6_RINGBUFSIZE 0x006EE0 832 #define ACP_SW1_RX_DMA6_FIFOADDR 0x006EE4 833 #define ACP_SW1_RX_DMA6_FIFOSIZE 0x006EE8 834 #define ACP_SW1_RX_DMA6_BURST_SIZE 0x006EEC 835 #define ACP_SW1_RX_DMA6_LINKPOSITIONCNTR 0x006EF0 836 #define ACP_SW1_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x006EF4 837 #define ACP_SW1_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x006EF8 838 #define ACP_SW1_RX_DMA6_INTR_WATERMARK_SIZE 0x006EFC 839 #define ACP_SW1_RX_DMA7_RINGBUFADDR 0x006F00 840 #define ACP_SW1_RX_DMA7_RINGBUFSIZE 0x006F04 841 #define ACP_SW1_RX_DMA7_FIFOADDR 0x006F08 842 #define ACP_SW1_RX_DMA7_FIFOSIZE 0x006F0C 843 #define ACP_SW1_RX_DMA7_BURST_SIZE 0x006F10 844 #define ACP_SW1_RX_DMA7_LINKPOSITIONCNTR 0x006F14 845 #define ACP_SW1_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x006F18 846 #define ACP_SW1_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x006F1C 847 #define ACP_SW1_RX_DMA7_INTR_WATERMARK_SIZE 0x006F20 848 #define ACP_SW1_TX_DMA0_RINGBUFADDR 0x006F24 849 #define ACP_SW1_TX_DMA0_RINGBUFSIZE 0x006F28 850 #define ACP_SW1_TX_DMA0_FIFOADDR 0x006F2C 851 #define ACP_SW1_TX_DMA0_FIFOSIZE 0x006F30 852 #define ACP_SW1_TX_DMA0_BURST_SIZE 0x006F34 853 #define ACP_SW1_TX_DMA0_LINKPOSITIONCNTR 0x006F38 854 #define ACP_SW1_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x006F3C 855 #define ACP_SW1_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x006F40 856 #define ACP_SW1_TX_DMA0_INTR_WATERMARK_SIZE 0x006F44 857 #define ACP_SW1_TX_DMA1_RINGBUFADDR 0x006F48 858 #define ACP_SW1_TX_DMA1_RINGBUFSIZE 0x006F4C 859 #define ACP_SW1_TX_DMA1_FIFOADDR 0x006F50 860 #define ACP_SW1_TX_DMA1_FIFOSIZE 0x006F54 861 #define ACP_SW1_TX_DMA1_BURST_SIZE 0x006F58 862 #define ACP_SW1_TX_DMA1_LINKPOSITIONCNTR 0x006F5C 863 #define ACP_SW1_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x006F60 864 #define ACP_SW1_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x006F64 865 #define ACP_SW1_TX_DMA1_INTR_WATERMARK_SIZE 0x006F68 866 #define ACP_SW1_TX_DMA2_RINGBUFADDR 0x006F6C 867 #define ACP_SW1_TX_DMA2_RINGBUFSIZE 0x006F70 868 #define ACP_SW1_TX_DMA2_FIFOADDR 0x006F74 869 #define ACP_SW1_TX_DMA2_FIFOSIZE 0x006F78 870 #define ACP_SW1_TX_DMA2_BURST_SIZE 0x006F7C 871 #define ACP_SW1_TX_DMA2_LINKPOSITIONCNTR 0x006F80 872 #define ACP_SW1_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x006F84 873 #define ACP_SW1_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x006F88 874 #define ACP_SW1_TX_DMA2_INTR_WATERMARK_SIZE 0x006F8C 875 #define ACP_SW1_TX_DMA3_RINGBUFADDR 0x006F90 876 #define ACP_SW1_TX_DMA3_RINGBUFSIZE 0x006F94 877 #define ACP_SW1_TX_DMA3_FIFOADDR 0x006F98 878 #define ACP_SW1_TX_DMA3_FIFOSIZE 0x006F9C 879 #define ACP_SW1_TX_DMA3_BURST_SIZE 0x006FA0 880 #define ACP_SW1_TX_DMA3_LINKPOSITIONCNTR 0x006FA4 881 #define ACP_SW1_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x006FA8 882 #define ACP_SW1_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x006FAC 883 #define ACP_SW1_TX_DMA3_INTR_WATERMARK_SIZE 0x006FB0 884 #define ACP_SW1_TX_DMA4_RINGBUFADDR 0x006FB4 885 #define ACP_SW1_TX_DMA4_RINGBUFSIZE 0x006FB8 886 #define ACP_SW1_TX_DMA4_FIFOADDR 0x006FBC 887 #define ACP_SW1_TX_DMA4_FIFOSIZE 0x006FC0 888 #define ACP_SW1_TX_DMA4_BURST_SIZE 0x006FC4 889 #define ACP_SW1_TX_DMA4_LINKPOSITIONCNTR 0x006FC8 890 #define ACP_SW1_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x006FCC 891 #define ACP_SW1_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x006FD0 892 #define ACP_SW1_TX_DMA4_INTR_WATERMARK_SIZE 0x006FD4 893 #define ACP_SW1_TX_DMA5_RINGBUFADDR 0x006FD8 894 #define ACP_SW1_TX_DMA5_RINGBUFSIZE 0x006FDC 895 #define ACP_SW1_TX_DMA5_FIFOADDR 0x006FE0 896 #define ACP_SW1_TX_DMA5_FIFOSIZE 0x006FE4 897 #define ACP_SW1_TX_DMA5_BURST_SIZE 0x006FE8 898 #define ACP_SW1_TX_DMA5_LINKPOSITIONCNTR 0x006FEC 899 #define ACP_SW1_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x006FF0 900 #define ACP_SW1_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x006FF4 901 #define ACP_SW1_TX_DMA5_INTR_WATERMARK_SIZE 0x006FF8 902 #define ACP_SW1_TX_DMA6_RINGBUFADDR 0x006FFC 903 #define ACP_SW1_TX_DMA6_RINGBUFSIZE 0x007000 904 #define ACP_SW1_TX_DMA6_FIFOADDR 0x007004 905 #define ACP_SW1_TX_DMA6_FIFOSIZE 0x007008 906 #define ACP_SW1_TX_DMA6_BURST_SIZE 0x00700C 907 #define ACP_SW1_TX_DMA6_LINKPOSITIONCNTR 0x007010 908 #define ACP_SW1_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x007014 909 #define ACP_SW1_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x007018 910 #define ACP_SW1_TX_DMA6_INTR_WATERMARK_SIZE 0x00701C 911 #define ACP_SW1_TX_DMA7_RINGBUFADDR 0x007020 912 #define ACP_SW1_TX_DMA7_RINGBUFSIZE 0x007024 913 #define ACP_SW1_TX_DMA7_FIFOADDR 0x007028 914 #define ACP_SW1_TX_DMA7_FIFOSIZE 0x00702C 915 #define ACP_SW1_TX_DMA7_BURST_SIZE 0x007030 916 #define ACP_SW1_TX_DMA7_LINKPOSITIONCNTR 0x007034 917 #define ACP_SW1_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x007038 918 #define ACP_SW1_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00703C 919 #define ACP_SW1_TX_DMA7_INTR_WATERMARK_SIZE 0x007040 920 #define ACP_SW1_RX_DMA0_POS_TRACK 0x007044 921 #define ACP_SW1_RX_DMA0_POS 0x007048 922 #define ACP_SW1_RX_DMA1_POS_TRACK 0x00704C 923 #define ACP_SW1_RX_DMA1_POS 0x007050 924 #define ACP_SW1_RX_DMA2_POS_TRACK 0x007054 925 #define ACP_SW1_RX_DMA2_POS 0x007058 926 #define ACP_SW1_RX_DMA3_POS_TRACK 0x00705C 927 #define ACP_SW1_RX_DMA3_POS 0x007060 928 #define ACP_SW1_RX_DMA4_POS_TRACK 0x007064 929 #define ACP_SW1_RX_DMA4_POS 0x007068 930 #define ACP_SW1_RX_DMA5_POS_TRACK 0x00706C 931 #define ACP_SW1_RX_DMA5_POS 0x007070 932 #define ACP_SW1_RX_DMA6_POS_TRACK 0x007074 933 #define ACP_SW1_RX_DMA6_POS 0x007078 934 #define ACP_SW1_RX_DMA7_POS_TRACK 0x00707C 935 #define ACP_SW1_RX_DMA7_POS 0x007080 936 #define ACP_SW1_TX_DMA0_POS_TRACK 0x007084 937 #define ACP_SW1_TX_DMA0_POS 0x007088 938 #define ACP_SW1_TX_DMA1_POS_TRACK 0x00708C 939 #define ACP_SW1_TX_DMA1_POS 0x007090 940 #define ACP_SW1_TX_DMA2_POS_TRACK 0x007094 941 #define ACP_SW1_TX_DMA2_POS 0x007098 942 #define ACP_SW1_TX_DMA3_POS_TRACK 0x00709C 943 #define ACP_SW1_TX_DMA3_POS 0x0070A0 944 #define ACP_SW1_TX_DMA4_POS_TRACK 0x0070A4 945 #define ACP_SW1_TX_DMA4_POS 0x0070A8 946 #define ACP_SW1_TX_DMA5_POS_TRACK 0x0070AC 947 #define ACP_SW1_TX_DMA5_POS 0x0070B0 948 #define ACP_SW1_TX_DMA6_POS_TRACK 0x0070B4 949 #define ACP_SW1_TX_DMA6_POS 0x0070B8 950 #define ACP_SW1_TX_DMA7_POS_TRACK 0x0070BC 951 #define ACP_SW1_TX_DMA7_POS 0x0070C0 952 #define ACP_SW1_FIFO_ERROR_REASON 0x0070C4 953 #define ACP_SW1_FIFO_ERROR_INTR_MASK 0x0070C8 954 #define ACP_SW1_ERROR_REASON1 0x0070CC 955 #define ACP_SW1_ERROR_INTR_MASK1 0x0070D0 956 #define ACP_SW1_ERROR_REASON2 0x0070D4 957 #define ACP_SW1_ERROR_INTR_MASK2 0x0070D8 958 959 #define ACP_SW1_CORB_BASE_ADDRESS 0x007100 960 #define ACP_SW1_CORB_WRITE_POINTER 0x007104 961 #define ACP_SW1_CORB_READ_POINTER 0x007108 962 #define ACP_SW1_CORB_CONTROL 0x00710C 963 #define ACP_SW1_CORB_SIZE 0x007114 964 #define ACP_SW1_RIRB_BASE_ADDRESS 0x007118 965 #define ACP_SW1_RIRB_WRITE_POINTER 0x00711C 966 #define ACP_SW1_RIRB_RESPONSE_INTERRUPT_COUNT 0x007120 967 #define ACP_SW1_RIRB_CONTROL 0x007124 968 #define ACP_SW1_RIRB_SIZE 0x007128 969 #define ACP_SW1_RIRB_FIFO_MIN_THDL 0x00712C 970 #define ACP_SW1_IMM_CMD_UPPER_WORD 0x007130 971 #define ACP_SW1_IMM_CMD_LOWER_QWORD 0x007134 972 #define ACP_SW1_IMM_RESP_UPPER_WORD 0x007138 973 #define ACP_SW1_IMM_RESP_LOWER_QWORD 0x00713C 974 #define ACP_SW1_IMM_CMD_STS 0x007140 975 #define ACP_SW1_BRA_BASE_ADDRESS 0x007144 976 #define ACP_SW1_BRA_TRANSFER_SIZE 0x007148 977 #define ACP_SW1_BRA_DMA_BUSY 0x00714C 978 #define ACP_SW1_BRA_RESP 0x007150 979 #define ACP_SW1_BRA_RESP_FRAME_ADDR 0x007154 980 #define ACP_SW1_BRA_CURRENT_TRANSFER_SIZE 0x007158 981 #define ACP_SW1_STATE_CHANGE_STATUS_0TO7 0x00715C 982 #define ACP_SW1_STATE_CHANGE_STATUS_8TO11 0x007160 983 #define ACP_SW1_STATE_CHANGE_STATUS_MASK_0TO7 0x007164 984 #define ACP_SW1_STATE_CHANGE_STATUS_MASK_8TO11 0x007168 985 #define ACP_SW1_CLK_FREQUENCY_CTRL_BANK0 0x00716C 986 #define ACP_SW1_CLK_FREQUENCY_CTRL_BANK1 0x007170 987 #define ACP_SW1_ERROR_INTR_MASK 0x007174 988 #define ACP_SW1_PHY_TEST_MODE_DATA_OFF 0x007178 989 #define ACP_SW1_DATA_TO_PDM_EN 0x00717C 990 991 #define ACP_SW1_EN 0x007200 992 #define ACP_SW1_EN_STATUS 0x007204 993 #define ACP_SW1_FRAMESIZE_BANK0 0x007208 994 #define ACP_SW1_FRAMESIZE_BANK1 0x00720C 995 #define ACP_SW1_SSP_COUNTER 0x007210 996 #define ACP_SW1_TX_STREAM0_EN 0x007214 997 #define ACP_SW1_TX_STREAM1_EN 0x007218 998 #define ACP_SW1_TX_STREAM2_EN 0x00721C 999 #define ACP_SW1_TX_STREAM3_EN 0x007220 1000 #define ACP_SW1_TX_STREAM4_EN 0x007224 1001 #define ACP_SW1_TX_STREAM5_EN 0x007228 1002 #define ACP_SW1_TX_STREAM6_EN 0x00722C 1003 #define ACP_SW1_TX_STREAM7_EN 0x007230 1004 #define ACP_SW1_TX_STREAM0_EN_STATUS 0x007234 1005 #define ACP_SW1_TX_STREAM1_EN_STATUS 0x007238 1006 #define ACP_SW1_TX_STREAM2_EN_STATUS 0x00723C 1007 #define ACP_SW1_TX_STREAM3_EN_STATUS 0x007240 1008 #define ACP_SW1_TX_STREAM4_EN_STATUS 0x007244 1009 #define ACP_SW1_TX_STREAM5_EN_STATUS 0x007248 1010 #define ACP_SW1_TX_STREAM6_EN_STATUS 0x00724C 1011 #define ACP_SW1_TX_STREAM7_EN_STATUS 0x007250 1012 #define ACP_SW1_TX_DP0_FRAME_FORMAT 0x007254 1013 #define ACP_SW1_TX_DP1_FRAME_FORMAT 0x007258 1014 #define ACP_SW1_TX_DP2_FRAME_FORMAT 0x00725C 1015 #define ACP_SW1_TX_DP3_FRAME_FORMAT 0x007260 1016 #define ACP_SW1_TX_DP4_FRAME_FORMAT 0x007264 1017 #define ACP_SW1_TX_DP5_FRAME_FORMAT 0x007268 1018 #define ACP_SW1_TX_DP6_FRAME_FORMAT 0x00726C 1019 #define ACP_SW1_TX_DP7_FRAME_FORMAT 0x007270 1020 #define ACP_SW1_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x007280 1021 #define ACP_SW1_TX_DP0_0_HCTRL_BANK0 0x007284 1022 #define ACP_SW1_TX_DP0_0_HCTRL_OFFSET_BANK0 0x007288 1023 #define ACP_SW1_TX_DP0_0_LANE_CTRL_BANK0 0x00728C 1024 #define ACP_SW1_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x007290 1025 #define ACP_SW1_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007294 1026 #define ACP_SW1_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x007298 1027 #define ACP_SW1_TX_DP0_0_HCTRL_BANK1 0x00729C 1028 #define ACP_SW1_TX_DP0_0_HCTRL_OFFSET_BANK1 0x0072A0 1029 #define ACP_SW1_TX_DP0_0_LANE_CTRL_BANK1 0x0072A4 1030 #define ACP_SW1_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x0072A8 1031 #define ACP_SW1_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0072AC 1032 #define ACP_SW1_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x0072B0 1033 #define ACP_SW1_TX_DP0_1_HCTRL_BANK0 0x0072B4 1034 #define ACP_SW1_TX_DP0_1_HCTRL_OFFSET_BANK0 0x0072B8 1035 #define ACP_SW1_TX_DP0_1_LANE_CTRL_BANK0 0x0072BC 1036 #define ACP_SW1_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x0072C0 1037 #define ACP_SW1_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0072C4 1038 #define ACP_SW1_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x0072C8 1039 #define ACP_SW1_TX_DP0_1_HCTRL_BANK1 0x0072CC 1040 #define ACP_SW1_TX_DP0_1_HCTRL_OFFSET_BANK1 0x0072D0 1041 #define ACP_SW1_TX_DP0_1_LANE_CTRL_BANK1 0x0072D4 1042 #define ACP_SW1_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x0072D8 1043 #define ACP_SW1_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0072DC 1044 #define ACP_SW1_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x0072E0 1045 #define ACP_SW1_TX_DP0_2_HCTRL_BANK0 0x0072E4 1046 #define ACP_SW1_TX_DP0_2_HCTRL_OFFSET_BANK0 0x0072E8 1047 #define ACP_SW1_TX_DP0_2_LANE_CTRL_BANK0 0x0072EC 1048 #define ACP_SW1_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x0072F0 1049 #define ACP_SW1_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0072F4 1050 #define ACP_SW1_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x0072F8 1051 #define ACP_SW1_TX_DP0_2_HCTRL_BANK1 0x0072FC 1052 #define ACP_SW1_TX_DP0_2_HCTRL_OFFSET_BANK1 0x007300 1053 #define ACP_SW1_TX_DP0_2_LANE_CTRL_BANK1 0x007304 1054 #define ACP_SW1_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x007308 1055 #define ACP_SW1_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00730C 1056 #define ACP_SW1_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x007310 1057 #define ACP_SW1_TX_DP0_3_HCTRL_BANK0 0x007314 1058 #define ACP_SW1_TX_DP0_3_HCTRL_OFFSET_BANK0 0x007318 1059 #define ACP_SW1_TX_DP0_3_LANE_CTRL_BANK0 0x00731C 1060 #define ACP_SW1_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x007320 1061 #define ACP_SW1_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007324 1062 #define ACP_SW1_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x007328 1063 #define ACP_SW1_TX_DP0_3_HCTRL_BANK1 0x00732C 1064 #define ACP_SW1_TX_DP0_3_HCTRL_OFFSET_BANK1 0x007330 1065 #define ACP_SW1_TX_DP0_3_LANE_CTRL_BANK1 0x007334 1066 #define ACP_SW1_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x007338 1067 #define ACP_SW1_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00733C 1068 #define ACP_SW1_TX_DP1_SAMPLEINTERVAL_BANK0 0x007370 1069 #define ACP_SW1_TX_DP1_HCTRL_BANK0 0x007374 1070 #define ACP_SW1_TX_DP1_HCTRL_OFFSET_BANK0 0x007378 1071 #define ACP_SW1_TX_DP1_LANE_CTRL_BANK0 0x00737C 1072 #define ACP_SW1_TX_DP1_CHANNEL_ENABLE_BANK0 0x007380 1073 #define ACP_SW1_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007384 1074 #define ACP_SW1_TX_DP1_SAMPLEINTERVAL_BANK1 0x007388 1075 #define ACP_SW1_TX_DP1_HCTRL_BANK1 0x00738C 1076 #define ACP_SW1_TX_DP1_HCTRL_OFFSET_BANK1 0x007390 1077 #define ACP_SW1_TX_DP1_LANE_CTRL_BANK1 0x007394 1078 #define ACP_SW1_TX_DP1_CHANNEL_ENABLE_BANK1 0x007398 1079 #define ACP_SW1_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00739C 1080 #define ACP_SW1_TX_DP2_SAMPLEINTERVAL_BANK0 0x0073A0 1081 #define ACP_SW1_TX_DP2_HCTRL_BANK0 0x0073A4 1082 #define ACP_SW1_TX_DP2_HCTRL_OFFSET_BANK0 0x0073A8 1083 #define ACP_SW1_TX_DP2_LANE_CTRL_BANK0 0x0073AC 1084 #define ACP_SW1_TX_DP2_CHANNEL_ENABLE_BANK0 0x0073B0 1085 #define ACP_SW1_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0073B4 1086 #define ACP_SW1_TX_DP2_SAMPLEINTERVAL_BANK1 0x0073B8 1087 #define ACP_SW1_TX_DP2_HCTRL_BANK1 0x0073BC 1088 #define ACP_SW1_TX_DP2_HCTRL_OFFSET_BANK1 0x0073C0 1089 #define ACP_SW1_TX_DP2_LANE_CTRL_BANK1 0x0073C4 1090 #define ACP_SW1_TX_DP2_CHANNEL_ENABLE_BANK1 0x0073C8 1091 #define ACP_SW1_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0073CC 1092 #define ACP_SW1_TX_DP3_SAMPLEINTERVAL_BANK0 0x0073D0 1093 #define ACP_SW1_TX_DP3_HCTRL_BANK0 0x0073D4 1094 #define ACP_SW1_TX_DP3_HCTRL_OFFSET_BANK0 0x0073D8 1095 #define ACP_SW1_TX_DP3_LANE_CTRL_BANK0 0x0073DC 1096 #define ACP_SW1_TX_DP3_CHANNEL_ENABLE_BANK0 0x0073E0 1097 #define ACP_SW1_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0073E4 1098 #define ACP_SW1_TX_DP3_SAMPLEINTERVAL_BANK1 0x0073E8 1099 #define ACP_SW1_TX_DP3_HCTRL_BANK1 0x0073EC 1100 #define ACP_SW1_TX_DP3_HCTRL_OFFSET_BANK1 0x0073F0 1101 #define ACP_SW1_TX_DP3_LANE_CTRL_BANK1 0x0073F4 1102 #define ACP_SW1_TX_DP3_CHANNEL_ENABLE_BANK1 0x0073F8 1103 #define ACP_SW1_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0073FC 1104 #define ACP_SW1_TX_DP4_SAMPLEINTERVAL_BANK0 0x007400 1105 #define ACP_SW1_TX_DP4_HCTRL_BANK0 0x007404 1106 #define ACP_SW1_TX_DP4_HCTRL_OFFSET_BANK0 0x007408 1107 #define ACP_SW1_TX_DP4_LANE_CTRL_BANK0 0x00740C 1108 #define ACP_SW1_TX_DP4_CHANNEL_ENABLE_BANK0 0x007410 1109 #define ACP_SW1_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007414 1110 #define ACP_SW1_TX_DP4_SAMPLEINTERVAL_BANK1 0x007418 1111 #define ACP_SW1_TX_DP4_HCTRL_BANK1 0x00741C 1112 #define ACP_SW1_TX_DP4_HCTRL_OFFSET_BANK1 0x007420 1113 #define ACP_SW1_TX_DP4_LANE_CTRL_BANK1 0x007424 1114 #define ACP_SW1_TX_DP4_CHANNEL_ENABLE_BANK1 0x007428 1115 #define ACP_SW1_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00742C 1116 #define ACP_SW1_TX_DP5_SAMPLEINTERVAL_BANK0 0x007430 1117 #define ACP_SW1_TX_DP5_HCTRL_BANK0 0x007434 1118 #define ACP_SW1_TX_DP5_HCTRL_OFFSET_BANK0 0x007438 1119 #define ACP_SW1_TX_DP5_LANE_CTRL_BANK0 0x00743C 1120 #define ACP_SW1_TX_DP5_CHANNEL_ENABLE_BANK0 0x007440 1121 #define ACP_SW1_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007444 1122 #define ACP_SW1_TX_DP5_SAMPLEINTERVAL_BANK1 0x007448 1123 #define ACP_SW1_TX_DP5_HCTRL_BANK1 0x00744C 1124 #define ACP_SW1_TX_DP5_HCTRL_OFFSET_BANK1 0x007450 1125 #define ACP_SW1_TX_DP5_LANE_CTRL_BANK1 0x007454 1126 #define ACP_SW1_TX_DP5_CHANNEL_ENABLE_BANK1 0x007458 1127 #define ACP_SW1_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00745C 1128 #define ACP_SW1_TX_DP6_SAMPLEINTERVAL_BANK0 0x007460 1129 #define ACP_SW1_TX_DP6_HCTRL_BANK0 0x007464 1130 #define ACP_SW1_TX_DP6_HCTRL_OFFSET_BANK0 0x007468 1131 #define ACP_SW1_TX_DP6_LANE_CTRL_BANK0 0x00746C 1132 #define ACP_SW1_TX_DP6_CHANNEL_ENABLE_BANK0 0x007470 1133 #define ACP_SW1_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007474 1134 #define ACP_SW1_TX_DP6_SAMPLEINTERVAL_BANK1 0x007478 1135 #define ACP_SW1_TX_DP6_HCTRL_BANK1 0x00747C 1136 #define ACP_SW1_TX_DP6_HCTRL_OFFSET_BANK1 0x007480 1137 #define ACP_SW1_TX_DP6_LANE_CTRL_BANK1 0x007484 1138 #define ACP_SW1_TX_DP6_CHANNEL_ENABLE_BANK1 0x007488 1139 #define ACP_SW1_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00748C 1140 #define ACP_SW1_TX_DP7_SAMPLEINTERVAL_BANK0 0x007490 1141 #define ACP_SW1_TX_DP7_HCTRL_BANK0 0x007494 1142 #define ACP_SW1_TX_DP7_HCTRL_OFFSET_BANK0 0x007498 1143 #define ACP_SW1_TX_DP7_LANE_CTRL_BANK0 0x00749C 1144 #define ACP_SW1_TX_DP7_CHANNEL_ENABLE_BANK0 0x0074A0 1145 #define ACP_SW1_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0074A4 1146 #define ACP_SW1_TX_DP7_SAMPLEINTERVAL_BANK1 0x0074A8 1147 #define ACP_SW1_TX_DP7_HCTRL_BANK1 0x0074AC 1148 #define ACP_SW1_TX_DP7_HCTRL_OFFSET_BANK1 0x0074B0 1149 #define ACP_SW1_TX_DP7_LANE_CTRL_BANK1 0x0074B4 1150 #define ACP_SW1_TX_DP7_CHANNEL_ENABLE_BANK1 0x0074B8 1151 #define ACP_SW1_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0074BC 1152 #define ACP_SW1_RX_STREAM0_EN 0x007514 1153 #define ACP_SW1_RX_STREAM1_EN 0x007518 1154 #define ACP_SW1_RX_STREAM2_EN 0x00751C 1155 #define ACP_SW1_RX_STREAM3_EN 0x007520 1156 #define ACP_SW1_RX_STREAM4_EN 0x007524 1157 #define ACP_SW1_RX_STREAM5_EN 0x007528 1158 #define ACP_SW1_RX_STREAM6_EN 0x00752C 1159 #define ACP_SW1_RX_STREAM7_EN 0x007530 1160 #define ACP_SW1_RX_STREAM0_EN_STATUS 0x007534 1161 #define ACP_SW1_RX_STREAM1_EN_STATUS 0x007538 1162 #define ACP_SW1_RX_STREAM2_EN_STATUS 0x00753C 1163 #define ACP_SW1_RX_STREAM3_EN_STATUS 0x007540 1164 #define ACP_SW1_RX_STREAM4_EN_STATUS 0x007544 1165 #define ACP_SW1_RX_STREAM5_EN_STATUS 0x007548 1166 #define ACP_SW1_RX_STREAM6_EN_STATUS 0x00754C 1167 #define ACP_SW1_RX_STREAM7_EN_STATUS 0x007550 1168 #define ACP_SW1_RX_DP0_FRAME_FORMAT 0x007554 1169 #define ACP_SW1_RX_DP1_FRAME_FORMAT 0x007558 1170 #define ACP_SW1_RX_DP2_FRAME_FORMAT 0x00755C 1171 #define ACP_SW1_RX_DP3_FRAME_FORMAT 0x007560 1172 #define ACP_SW1_RX_DP4_FRAME_FORMAT 0x007564 1173 #define ACP_SW1_RX_DP5_FRAME_FORMAT 0x007568 1174 #define ACP_SW1_RX_DP6_FRAME_FORMAT 0x00756C 1175 #define ACP_SW1_RX_DP7_FRAME_FORMAT 0x007570 1176 #define ACP_SW1_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x007580 1177 #define ACP_SW1_RX_DP0_0_HCTRL_BANK0 0x007584 1178 #define ACP_SW1_RX_DP0_0_HCTRL_OFFSET_BANK0 0x007588 1179 #define ACP_SW1_RX_DP0_0_LANE_CTRL_BANK0 0x00758C 1180 #define ACP_SW1_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x007590 1181 #define ACP_SW1_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007594 1182 #define ACP_SW1_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x007598 1183 #define ACP_SW1_RX_DP0_0_HCTRL_BANK1 0x00759C 1184 #define ACP_SW1_RX_DP0_0_HCTRL_OFFSET_BANK1 0x0075A0 1185 #define ACP_SW1_RX_DP0_0_LANE_CTRL_BANK1 0x0075A4 1186 #define ACP_SW1_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x0075A8 1187 #define ACP_SW1_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0075AC 1188 #define ACP_SW1_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x0075B0 1189 #define ACP_SW1_RX_DP0_1_HCTRL_BANK0 0x0075B4 1190 #define ACP_SW1_RX_DP0_1_HCTRL_OFFSET_BANK0 0x0075B8 1191 #define ACP_SW1_RX_DP0_1_LANE_CTRL_BANK0 0x0075BC 1192 #define ACP_SW1_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x0075C0 1193 #define ACP_SW1_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0075C4 1194 #define ACP_SW1_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x0075C8 1195 #define ACP_SW1_RX_DP0_1_HCTRL_BANK1 0x0075CC 1196 #define ACP_SW1_RX_DP0_1_HCTRL_OFFSET_BANK1 0x0075D0 1197 #define ACP_SW1_RX_DP0_1_LANE_CTRL_BANK1 0x0075D4 1198 #define ACP_SW1_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x0075D8 1199 #define ACP_SW1_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0075DC 1200 #define ACP_SW1_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x0075E0 1201 #define ACP_SW1_RX_DP0_2_HCTRL_BANK0 0x0075E4 1202 #define ACP_SW1_RX_DP0_2_HCTRL_OFFSET_BANK0 0x0075E8 1203 #define ACP_SW1_RX_DP0_2_LANE_CTRL_BANK0 0x0075EC 1204 #define ACP_SW1_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x0075F0 1205 #define ACP_SW1_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0075F4 1206 #define ACP_SW1_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x0075F8 1207 #define ACP_SW1_RX_DP0_2_HCTRL_BANK1 0x0075FC 1208 #define ACP_SW1_RX_DP0_2_HCTRL_OFFSET_BANK1 0x007600 1209 #define ACP_SW1_RX_DP0_2_LANE_CTRL_BANK1 0x007604 1210 #define ACP_SW1_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x007608 1211 #define ACP_SW1_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00760C 1212 #define ACP_SW1_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x007610 1213 #define ACP_SW1_RX_DP0_3_HCTRL_BANK0 0x007614 1214 #define ACP_SW1_RX_DP0_3_HCTRL_OFFSET_BANK0 0x007618 1215 #define ACP_SW1_RX_DP0_3_LANE_CTRL_BANK0 0x00761C 1216 #define ACP_SW1_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x007620 1217 #define ACP_SW1_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007624 1218 #define ACP_SW1_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x007628 1219 #define ACP_SW1_RX_DP0_3_HCTRL_BANK1 0x00762C 1220 #define ACP_SW1_RX_DP0_3_HCTRL_OFFSET_BANK1 0x007630 1221 #define ACP_SW1_RX_DP0_3_LANE_CTRL_BANK1 0x007634 1222 #define ACP_SW1_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x007638 1223 #define ACP_SW1_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00763C 1224 #define ACP_SW1_RX_DP1_SAMPLEINTERVAL_BANK0 0x007670 1225 #define ACP_SW1_RX_DP1_HCTRL_BANK0 0x007674 1226 #define ACP_SW1_RX_DP1_HCTRL_OFFSET_BANK0 0x007678 1227 #define ACP_SW1_RX_DP1_LANE_CTRL_BANK0 0x00767C 1228 #define ACP_SW1_RX_DP1_CHANNEL_ENABLE_BANK0 0x007680 1229 #define ACP_SW1_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007684 1230 #define ACP_SW1_RX_DP1_SAMPLEINTERVAL_BANK1 0x007688 1231 #define ACP_SW1_RX_DP1_HCTRL_BANK1 0x00768C 1232 #define ACP_SW1_RX_DP1_HCTRL_OFFSET_BANK1 0x007690 1233 #define ACP_SW1_RX_DP1_LANE_CTRL_BANK1 0x007694 1234 #define ACP_SW1_RX_DP1_CHANNEL_ENABLE_BANK1 0x007698 1235 #define ACP_SW1_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00769C 1236 #define ACP_SW1_RX_DP2_SAMPLEINTERVAL_BANK0 0x0076A0 1237 #define ACP_SW1_RX_DP2_HCTRL_BANK0 0x0076A4 1238 #define ACP_SW1_RX_DP2_HCTRL_OFFSET_BANK0 0x0076A8 1239 #define ACP_SW1_RX_DP2_LANE_CTRL_BANK0 0x0076AC 1240 #define ACP_SW1_RX_DP2_CHANNEL_ENABLE_BANK0 0x0076B0 1241 #define ACP_SW1_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0076B4 1242 #define ACP_SW1_RX_DP2_SAMPLEINTERVAL_BANK1 0x0076B8 1243 #define ACP_SW1_RX_DP2_HCTRL_BANK1 0x0076BC 1244 #define ACP_SW1_RX_DP2_HCTRL_OFFSET_BANK1 0x0076C0 1245 #define ACP_SW1_RX_DP2_LANE_CTRL_BANK1 0x0076C4 1246 #define ACP_SW1_RX_DP2_CHANNEL_ENABLE_BANK1 0x0076C8 1247 #define ACP_SW1_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0076CC 1248 #define ACP_SW1_RX_DP3_SAMPLEINTERVAL_BANK0 0x0076D0 1249 #define ACP_SW1_RX_DP3_HCTRL_BANK0 0x0076D4 1250 #define ACP_SW1_RX_DP3_HCTRL_OFFSET_BANK0 0x0076D8 1251 #define ACP_SW1_RX_DP3_LANE_CTRL_BANK0 0x0076DC 1252 #define ACP_SW1_RX_DP3_CHANNEL_ENABLE_BANK0 0x0076E0 1253 #define ACP_SW1_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0076E4 1254 #define ACP_SW1_RX_DP3_SAMPLEINTERVAL_BANK1 0x0076E8 1255 #define ACP_SW1_RX_DP3_HCTRL_BANK1 0x0076EC 1256 #define ACP_SW1_RX_DP3_HCTRL_OFFSET_BANK1 0x0076F0 1257 #define ACP_SW1_RX_DP3_LANE_CTRL_BANK1 0x0076F4 1258 #define ACP_SW1_RX_DP3_CHANNEL_ENABLE_BANK1 0x0076F8 1259 #define ACP_SW1_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0076FC 1260 #define ACP_SW1_RX_DP4_SAMPLEINTERVAL_BANK0 0x007700 1261 #define ACP_SW1_RX_DP4_HCTRL_BANK0 0x007704 1262 #define ACP_SW1_RX_DP4_HCTRL_OFFSET_BANK0 0x007708 1263 #define ACP_SW1_RX_DP4_LANE_CTRL_BANK0 0x00770C 1264 #define ACP_SW1_RX_DP4_CHANNEL_ENABLE_BANK0 0x007710 1265 #define ACP_SW1_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007714 1266 #define ACP_SW1_RX_DP4_SAMPLEINTERVAL_BANK1 0x007718 1267 #define ACP_SW1_RX_DP4_HCTRL_BANK1 0x00771C 1268 #define ACP_SW1_RX_DP4_HCTRL_OFFSET_BANK1 0x007720 1269 #define ACP_SW1_RX_DP4_LANE_CTRL_BANK1 0x007724 1270 #define ACP_SW1_RX_DP4_CHANNEL_ENABLE_BANK1 0x007728 1271 #define ACP_SW1_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00772C 1272 #define ACP_SW1_RX_DP5_SAMPLEINTERVAL_BANK0 0x007730 1273 #define ACP_SW1_RX_DP5_HCTRL_BANK0 0x007734 1274 #define ACP_SW1_RX_DP5_HCTRL_OFFSET_BANK0 0x007738 1275 #define ACP_SW1_RX_DP5_LANE_CTRL_BANK0 0x00773C 1276 #define ACP_SW1_RX_DP5_CHANNEL_ENABLE_BANK0 0x007740 1277 #define ACP_SW1_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007744 1278 #define ACP_SW1_RX_DP5_SAMPLEINTERVAL_BANK1 0x007748 1279 #define ACP_SW1_RX_DP5_HCTRL_BANK1 0x00774C 1280 #define ACP_SW1_RX_DP5_HCTRL_OFFSET_BANK1 0x007750 1281 #define ACP_SW1_RX_DP5_LANE_CTRL_BANK1 0x007754 1282 #define ACP_SW1_RX_DP5_CHANNEL_ENABLE_BANK1 0x007758 1283 #define ACP_SW1_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00775C 1284 #define ACP_SW1_RX_DP6_SAMPLEINTERVAL_BANK0 0x007760 1285 #define ACP_SW1_RX_DP6_HCTRL_BANK0 0x007764 1286 #define ACP_SW1_RX_DP6_HCTRL_OFFSET_BANK0 0x007768 1287 #define ACP_SW1_RX_DP6_LANE_CTRL_BANK0 0x00776C 1288 #define ACP_SW1_RX_DP6_CHANNEL_ENABLE_BANK0 0x007770 1289 #define ACP_SW1_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007774 1290 #define ACP_SW1_RX_DP6_SAMPLEINTERVAL_BANK1 0x007778 1291 #define ACP_SW1_RX_DP6_HCTRL_BANK1 0x00777C 1292 #define ACP_SW1_RX_DP6_HCTRL_OFFSET_BANK1 0x007780 1293 #define ACP_SW1_RX_DP6_LANE_CTRL_BANK1 0x007784 1294 #define ACP_SW1_RX_DP6_CHANNEL_ENABLE_BANK1 0x007788 1295 #define ACP_SW1_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00778C 1296 #define ACP_SW1_RX_DP7_SAMPLEINTERVAL_BANK0 0x007790 1297 #define ACP_SW1_RX_DP7_HCTRL_BANK0 0x007794 1298 #define ACP_SW1_RX_DP7_HCTRL_OFFSET_BANK0 0x007798 1299 #define ACP_SW1_RX_DP7_LANE_CTRL_BANK0 0x00779C 1300 #define ACP_SW1_RX_DP7_CHANNEL_ENABLE_BANK0 0x0077A0 1301 #define ACP_SW1_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0077A4 1302 #define ACP_SW1_RX_DP7_SAMPLEINTERVAL_BANK1 0x0077A8 1303 #define ACP_SW1_RX_DP7_HCTRL_BANK1 0x0077AC 1304 #define ACP_SW1_RX_DP7_HCTRL_OFFSET_BANK1 0x0077B0 1305 #define ACP_SW1_RX_DP7_LANE_CTRL_BANK1 0x0077B4 1306 #define ACP_SW1_RX_DP7_CHANNEL_ENABLE_BANK1 0x0077B8 1307 #define ACP_SW1_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0077BC 1308 #define ACP_SW1_BPT_PORT_EN 0x0077C0 1309 #define ACP_SW1_BPT_PORT_EN_STATUS 0x0077C4 1310 #define ACP_SW1_BPT_PORT_FRAME_FORMAT 0x0077C8 1311 #define ACP_SW1_BPT_PORT_SAMPLEINTERVAL_BANK0 0x0077CC 1312 #define ACP_SW1_BPT_PORT_HCTRL_BANK0 0x0077D0 1313 #define ACP_SW1_BPT_PORT_OFFSET_BANK0 0x0077D4 1314 #define ACP_SW1_BPT_PORT_LANE_SELECT_BANK0 0x0077D8 1315 #define ACP_SW1_BPT_PORT_CHANNEL_ENABLE_BANK0 0x0077DC 1316 #define ACP_SW1_BPT_PORT_SAMPLEINTERVAL_BANK1 0x0077E0 1317 #define ACP_SW1_BPT_PORT_HCTRL_BANK1 0x0077E4 1318 #define ACP_SW1_BPT_PORT_OFFSET_BANK1 0x0077E8 1319 #define ACP_SW1_BPT_PORT_LANE_SELECT_BANK1 0x0077EC 1320 #define ACP_SW1_BPT_PORT_CHANNEL_ENABLE_BANK1 0x0077F0 1321 #define ACP_SW1_BPT_PORT_FIRST_BYTE_ADDR 0x0077F4 1322 #define ACP_SW1_CLK_RESUME_CTRL 0x0077F8 1323 #define ACP_SW1_CLK_RESUME_DELAY_CNTR 0x0077FC 1324 #define ACP_SW1_BUS_RESET_CTRL 0x007800 1325 #define ACP_SW1_PRBS_ERR_STATUS 0x007804 1326 #define ACP_SW1_WALLCLK_MISC 0x007808 1327 #define ACP_SW1_WALL_CLK_COUNTER 0x00780C 1328 #define ACP_SW1_PING_STATUS_REGISTER_LOW 0x007810 1329 #define ACP_SW1_PING_STATUS_REGISTER_HIGH 0x007814 1330 #define ACP_SW1_PING_STATUS_CURRENT_BANK_SEL 0x007818 1331 #define ACP_SW1_TZD_CHANGE 0x00781C 1332 #define ACP_SW1_WALLCLK_INTR_CNTL 0x007820 1333 1334 #define ACP_SW2_GLOBAL_CAPABILITIES 0x008E00 1335 #define ACP_SW2_RX_DMA0_RINGBUFADDR 0x008E04 1336 #define ACP_SW2_RX_DMA0_RINGBUFSIZE 0x008E08 1337 #define ACP_SW2_RX_DMA0_FIFOADDR 0x008E0C 1338 #define ACP_SW2_RX_DMA0_FIFOSIZE 0x008E10 1339 #define ACP_SW2_RX_DMA0_BURST_SIZE 0x008E14 1340 #define ACP_SW2_RX_DMA0_LINKPOSITIONCNTR 0x008E18 1341 #define ACP_SW2_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x008E1C 1342 #define ACP_SW2_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x008E20 1343 #define ACP_SW2_RX_DMA0_INTR_WATERMARK_SIZE 0x008E24 1344 #define ACP_SW2_RX_DMA1_RINGBUFADDR 0x008E28 1345 #define ACP_SW2_RX_DMA1_RINGBUFSIZE 0x008E2C 1346 #define ACP_SW2_RX_DMA1_FIFOADDR 0x008E30 1347 #define ACP_SW2_RX_DMA1_FIFOSIZE 0x008E34 1348 #define ACP_SW2_RX_DMA1_BURST_SIZE 0x008E38 1349 #define ACP_SW2_RX_DMA1_LINKPOSITIONCNTR 0x008E3C 1350 #define ACP_SW2_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x008E40 1351 #define ACP_SW2_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x008E44 1352 #define ACP_SW2_RX_DMA1_INTR_WATERMARK_SIZE 0x008E48 1353 #define ACP_SW2_RX_DMA2_RINGBUFADDR 0x008E4C 1354 #define ACP_SW2_RX_DMA2_RINGBUFSIZE 0x008E50 1355 #define ACP_SW2_RX_DMA2_FIFOADDR 0x008E54 1356 #define ACP_SW2_RX_DMA2_FIFOSIZE 0x008E58 1357 #define ACP_SW2_RX_DMA2_BURST_SIZE 0x008E5C 1358 #define ACP_SW2_RX_DMA2_LINKPOSITIONCNTR 0x008E60 1359 #define ACP_SW2_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x008E64 1360 #define ACP_SW2_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x008E68 1361 #define ACP_SW2_RX_DMA2_INTR_WATERMARK_SIZE 0x008E6C 1362 #define ACP_SW2_RX_DMA3_RINGBUFADDR 0x008E70 1363 #define ACP_SW2_RX_DMA3_RINGBUFSIZE 0x008E74 1364 #define ACP_SW2_RX_DMA3_FIFOADDR 0x008E78 1365 #define ACP_SW2_RX_DMA3_FIFOSIZE 0x008E7C 1366 #define ACP_SW2_RX_DMA3_BURST_SIZE 0x008E80 1367 #define ACP_SW2_RX_DMA3_LINKPOSITIONCNTR 0x008E84 1368 #define ACP_SW2_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x008E88 1369 #define ACP_SW2_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x008E8C 1370 #define ACP_SW2_RX_DMA3_INTR_WATERMARK_SIZE 0x008E90 1371 #define ACP_SW2_RX_DMA4_RINGBUFADDR 0x008E94 1372 #define ACP_SW2_RX_DMA4_RINGBUFSIZE 0x008E98 1373 #define ACP_SW2_RX_DMA4_FIFOADDR 0x008E9C 1374 #define ACP_SW2_RX_DMA4_FIFOSIZE 0x008EA0 1375 #define ACP_SW2_RX_DMA4_BURST_SIZE 0x008EA4 1376 #define ACP_SW2_RX_DMA4_LINKPOSITIONCNTR 0x008EA8 1377 #define ACP_SW2_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x008EAC 1378 #define ACP_SW2_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x008EB0 1379 #define ACP_SW2_RX_DMA4_INTR_WATERMARK_SIZE 0x008EB4 1380 #define ACP_SW2_RX_DMA5_RINGBUFADDR 0x008EB8 1381 #define ACP_SW2_RX_DMA5_RINGBUFSIZE 0x008EBC 1382 #define ACP_SW2_RX_DMA5_FIFOADDR 0x008EC0 1383 #define ACP_SW2_RX_DMA5_FIFOSIZE 0x008EC4 1384 #define ACP_SW2_RX_DMA5_BURST_SIZE 0x008EC8 1385 #define ACP_SW2_RX_DMA5_LINKPOSITIONCNTR 0x008ECC 1386 #define ACP_SW2_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x008ED0 1387 #define ACP_SW2_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x008ED4 1388 #define ACP_SW2_RX_DMA5_INTR_WATERMARK_SIZE 0x008ED8 1389 #define ACP_SW2_RX_DMA6_RINGBUFADDR 0x008EDC 1390 #define ACP_SW2_RX_DMA6_RINGBUFSIZE 0x008EE0 1391 #define ACP_SW2_RX_DMA6_FIFOADDR 0x008EE4 1392 #define ACP_SW2_RX_DMA6_FIFOSIZE 0x008EE8 1393 #define ACP_SW2_RX_DMA6_BURST_SIZE 0x008EEC 1394 #define ACP_SW2_RX_DMA6_LINKPOSITIONCNTR 0x008EF0 1395 #define ACP_SW2_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x008EF4 1396 #define ACP_SW2_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x008EF8 1397 #define ACP_SW2_RX_DMA6_INTR_WATERMARK_SIZE 0x008EFC 1398 #define ACP_SW2_RX_DMA7_RINGBUFADDR 0x008F00 1399 #define ACP_SW2_RX_DMA7_RINGBUFSIZE 0x008F04 1400 #define ACP_SW2_RX_DMA7_FIFOADDR 0x008F08 1401 #define ACP_SW2_RX_DMA7_FIFOSIZE 0x008F0C 1402 #define ACP_SW2_RX_DMA7_BURST_SIZE 0x008F10 1403 #define ACP_SW2_RX_DMA7_LINKPOSITIONCNTR 0x008F14 1404 #define ACP_SW2_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x008F18 1405 #define ACP_SW2_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x008F1C 1406 #define ACP_SW2_RX_DMA7_INTR_WATERMARK_SIZE 0x008F20 1407 #define ACP_SW2_TX_DMA0_RINGBUFADDR 0x008F24 1408 #define ACP_SW2_TX_DMA0_RINGBUFSIZE 0x008F28 1409 #define ACP_SW2_TX_DMA0_FIFOADDR 0x008F2C 1410 #define ACP_SW2_TX_DMA0_FIFOSIZE 0x008F30 1411 #define ACP_SW2_TX_DMA0_BURST_SIZE 0x008F34 1412 #define ACP_SW2_TX_DMA0_LINKPOSITIONCNTR 0x008F38 1413 #define ACP_SW2_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x008F3C 1414 #define ACP_SW2_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x008F40 1415 #define ACP_SW2_TX_DMA0_INTR_WATERMARK_SIZE 0x008F44 1416 #define ACP_SW2_TX_DMA1_RINGBUFADDR 0x008F48 1417 #define ACP_SW2_TX_DMA1_RINGBUFSIZE 0x008F4C 1418 #define ACP_SW2_TX_DMA1_FIFOADDR 0x008F50 1419 #define ACP_SW2_TX_DMA1_FIFOSIZE 0x008F54 1420 #define ACP_SW2_TX_DMA1_BURST_SIZE 0x008F58 1421 #define ACP_SW2_TX_DMA1_LINKPOSITIONCNTR 0x008F5C 1422 #define ACP_SW2_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x008F60 1423 #define ACP_SW2_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x008F64 1424 #define ACP_SW2_TX_DMA1_INTR_WATERMARK_SIZE 0x008F68 1425 #define ACP_SW2_TX_DMA2_RINGBUFADDR 0x008F6C 1426 #define ACP_SW2_TX_DMA2_RINGBUFSIZE 0x008F70 1427 #define ACP_SW2_TX_DMA2_FIFOADDR 0x008F74 1428 #define ACP_SW2_TX_DMA2_FIFOSIZE 0x008F78 1429 #define ACP_SW2_TX_DMA2_BURST_SIZE 0x008F7C 1430 #define ACP_SW2_TX_DMA2_LINKPOSITIONCNTR 0x008F80 1431 #define ACP_SW2_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x008F84 1432 #define ACP_SW2_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x008F88 1433 #define ACP_SW2_TX_DMA2_INTR_WATERMARK_SIZE 0x008F8C 1434 #define ACP_SW2_TX_DMA3_RINGBUFADDR 0x008F90 1435 #define ACP_SW2_TX_DMA3_RINGBUFSIZE 0x008F94 1436 #define ACP_SW2_TX_DMA3_FIFOADDR 0x008F98 1437 #define ACP_SW2_TX_DMA3_FIFOSIZE 0x008F9C 1438 #define ACP_SW2_TX_DMA3_BURST_SIZE 0x008FA0 1439 #define ACP_SW2_TX_DMA3_LINKPOSITIONCNTR 0x008FA4 1440 #define ACP_SW2_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x008FA8 1441 #define ACP_SW2_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x008FAC 1442 #define ACP_SW2_TX_DMA3_INTR_WATERMARK_SIZE 0x008FB0 1443 #define ACP_SW2_TX_DMA4_RINGBUFADDR 0x008FB4 1444 #define ACP_SW2_TX_DMA4_RINGBUFSIZE 0x008FB8 1445 #define ACP_SW2_TX_DMA4_FIFOADDR 0x008FBC 1446 #define ACP_SW2_TX_DMA4_FIFOSIZE 0x008FC0 1447 #define ACP_SW2_TX_DMA4_BURST_SIZE 0x008FC4 1448 #define ACP_SW2_TX_DMA4_LINKPOSITIONCNTR 0x008FC8 1449 #define ACP_SW2_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x008FCC 1450 #define ACP_SW2_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x008FD0 1451 #define ACP_SW2_TX_DMA4_INTR_WATERMARK_SIZE 0x008FD4 1452 #define ACP_SW2_TX_DMA5_RINGBUFADDR 0x008FD8 1453 #define ACP_SW2_TX_DMA5_RINGBUFSIZE 0x008FDC 1454 #define ACP_SW2_TX_DMA5_FIFOADDR 0x008FE0 1455 #define ACP_SW2_TX_DMA5_FIFOSIZE 0x008FE4 1456 #define ACP_SW2_TX_DMA5_BURST_SIZE 0x008FE8 1457 #define ACP_SW2_TX_DMA5_LINKPOSITIONCNTR 0x008FEC 1458 #define ACP_SW2_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x008FF0 1459 #define ACP_SW2_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x008FF4 1460 #define ACP_SW2_TX_DMA5_INTR_WATERMARK_SIZE 0x008FF8 1461 #define ACP_SW2_TX_DMA6_RINGBUFADDR 0x008FFC 1462 #define ACP_SW2_TX_DMA6_RINGBUFSIZE 0x009000 1463 #define ACP_SW2_TX_DMA6_FIFOADDR 0x009004 1464 #define ACP_SW2_TX_DMA6_FIFOSIZE 0x009008 1465 #define ACP_SW2_TX_DMA6_BURST_SIZE 0x00900C 1466 #define ACP_SW2_TX_DMA6_LINKPOSITIONCNTR 0x009010 1467 #define ACP_SW2_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x009014 1468 #define ACP_SW2_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x009018 1469 #define ACP_SW2_TX_DMA6_INTR_WATERMARK_SIZE 0x00901C 1470 #define ACP_SW2_TX_DMA7_RINGBUFADDR 0x009020 1471 #define ACP_SW2_TX_DMA7_RINGBUFSIZE 0x009024 1472 #define ACP_SW2_TX_DMA7_FIFOADDR 0x009028 1473 #define ACP_SW2_TX_DMA7_FIFOSIZE 0x00902C 1474 #define ACP_SW2_TX_DMA7_BURST_SIZE 0x009030 1475 #define ACP_SW2_TX_DMA7_LINKPOSITIONCNTR 0x009034 1476 #define ACP_SW2_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x009038 1477 #define ACP_SW2_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00903C 1478 #define ACP_SW2_TX_DMA7_INTR_WATERMARK_SIZE 0x009040 1479 #define ACP_SW2_RX_DMA0_POS_TRACK 0x009044 1480 #define ACP_SW2_RX_DMA0_POS 0x009048 1481 #define ACP_SW2_RX_DMA1_POS_TRACK 0x00904C 1482 #define ACP_SW2_RX_DMA1_POS 0x009050 1483 #define ACP_SW2_RX_DMA2_POS_TRACK 0x009054 1484 #define ACP_SW2_RX_DMA2_POS 0x009058 1485 #define ACP_SW2_RX_DMA3_POS_TRACK 0x00905C 1486 #define ACP_SW2_RX_DMA3_POS 0x009060 1487 #define ACP_SW2_RX_DMA4_POS_TRACK 0x009064 1488 #define ACP_SW2_RX_DMA4_POS 0x009068 1489 #define ACP_SW2_RX_DMA5_POS_TRACK 0x00906C 1490 #define ACP_SW2_RX_DMA5_POS 0x009070 1491 #define ACP_SW2_RX_DMA6_POS_TRACK 0x009074 1492 #define ACP_SW2_RX_DMA6_POS 0x009078 1493 #define ACP_SW2_RX_DMA7_POS_TRACK 0x00907C 1494 #define ACP_SW2_RX_DMA7_POS 0x009080 1495 #define ACP_SW2_TX_DMA0_POS_TRACK 0x009084 1496 #define ACP_SW2_TX_DMA0_POS 0x009088 1497 #define ACP_SW2_TX_DMA1_POS_TRACK 0x00908C 1498 #define ACP_SW2_TX_DMA1_POS 0x009090 1499 #define ACP_SW2_TX_DMA2_POS_TRACK 0x009094 1500 #define ACP_SW2_TX_DMA2_POS 0x009098 1501 #define ACP_SW2_TX_DMA3_POS_TRACK 0x00909C 1502 #define ACP_SW2_TX_DMA3_POS 0x0090A0 1503 #define ACP_SW2_TX_DMA4_POS_TRACK 0x0090A4 1504 #define ACP_SW2_TX_DMA4_POS 0x0090A8 1505 #define ACP_SW2_TX_DMA5_POS_TRACK 0x0090AC 1506 #define ACP_SW2_TX_DMA5_POS 0x0090B0 1507 #define ACP_SW2_TX_DMA6_POS_TRACK 0x0090B4 1508 #define ACP_SW2_TX_DMA6_POS 0x0090B8 1509 #define ACP_SW2_TX_DMA7_POS_TRACK 0x0090BC 1510 #define ACP_SW2_TX_DMA7_POS 0x0090C0 1511 #define ACP_SW2_FIFO_ERROR_REASON 0x0090C4 1512 #define ACP_SW2_FIFO_ERROR_INTR_MASK 0x0090C8 1513 #define ACP_SW2_ERROR_REASON1 0x0090CC 1514 #define ACP_SW2_ERROR_INTR_MASK1 0x0090D0 1515 #define ACP_SW2_ERROR_REASON2 0x0090D4 1516 #define ACP_SW2_ERROR_INTR_MASK2 0x0090D8 1517 1518 #define ACP_SW2_CORB_BASE_ADDRESS 0x009100 1519 #define ACP_SW2_CORB_WRITE_POINTER 0x009104 1520 #define ACP_SW2_CORB_READ_POINTER 0x009108 1521 #define ACP_SW2_CORB_CONTROL 0x00910C 1522 #define ACP_SW2_CORB_SIZE 0x009114 1523 #define ACP_SW2_RIRB_BASE_ADDRESS 0x009118 1524 #define ACP_SW2_RIRB_WRITE_POINTER 0x00911C 1525 #define ACP_SW2_RIRB_RESPONSE_INTERRUPT_COUNT 0x009120 1526 #define ACP_SW2_RIRB_CONTROL 0x009124 1527 #define ACP_SW2_RIRB_SIZE 0x009128 1528 #define ACP_SW2_RIRB_FIFO_MIN_THDL 0x00912C 1529 #define ACP_SW2_IMM_CMD_UPPER_WORD 0x009130 1530 #define ACP_SW2_IMM_CMD_LOWER_QWORD 0x009134 1531 #define ACP_SW2_IMM_RESP_UPPER_WORD 0x009138 1532 #define ACP_SW2_IMM_RESP_LOWER_QWORD 0x00913C 1533 #define ACP_SW2_IMM_CMD_STS 0x009140 1534 #define ACP_SW2_BRA_BASE_ADDRESS 0x009144 1535 #define ACP_SW2_BRA_TRANSFER_SIZE 0x009148 1536 #define ACP_SW2_BRA_DMA_BUSY 0x00914C 1537 #define ACP_SW2_BRA_RESP 0x009150 1538 #define ACP_SW2_BRA_RESP_FRAME_ADDR 0x009154 1539 #define ACP_SW2_BRA_CURRENT_TRANSFER_SIZE 0x009158 1540 #define ACP_SW2_STATE_CHANGE_STATUS_0TO7 0x00915C 1541 #define ACP_SW2_STATE_CHANGE_STATUS_8TO11 0x009160 1542 #define ACP_SW2_STATE_CHANGE_STATUS_MASK_0TO7 0x009164 1543 #define ACP_SW2_STATE_CHANGE_STATUS_MASK_8TO11 0x009168 1544 #define ACP_SW2_CLK_FREQUENCY_CTRL_BANK0 0x00916C 1545 #define ACP_SW2_CLK_FREQUENCY_CTRL_BANK1 0x009170 1546 #define ACP_SW2_ERROR_INTR_MASK 0x009174 1547 #define ACP_SW2_PHY_TEST_MODE_DATA_OFF 0x009178 1548 #define ACP_SW2_DATA_TO_PDM_EN 0x00917C 1549 1550 #define ACP_SW2_EN 0x009200 1551 #define ACP_SW2_EN_STATUS 0x009204 1552 #define ACP_SW2_FRAMESIZE_BANK0 0x009208 1553 #define ACP_SW2_FRAMESIZE_BANK1 0x00920C 1554 #define ACP_SW2_SSP_COUNTER 0x009210 1555 #define ACP_SW2_TX_STREAM0_EN 0x009214 1556 #define ACP_SW2_TX_STREAM1_EN 0x009218 1557 #define ACP_SW2_TX_STREAM2_EN 0x00921C 1558 #define ACP_SW2_TX_STREAM3_EN 0x009220 1559 #define ACP_SW2_TX_STREAM4_EN 0x009224 1560 #define ACP_SW2_TX_STREAM5_EN 0x009228 1561 #define ACP_SW2_TX_STREAM6_EN 0x00922C 1562 #define ACP_SW2_TX_STREAM7_EN 0x009230 1563 #define ACP_SW2_TX_STREAM0_EN_STATUS 0x009234 1564 #define ACP_SW2_TX_STREAM1_EN_STATUS 0x009238 1565 #define ACP_SW2_TX_STREAM2_EN_STATUS 0x00923C 1566 #define ACP_SW2_TX_STREAM3_EN_STATUS 0x009240 1567 #define ACP_SW2_TX_STREAM4_EN_STATUS 0x009244 1568 #define ACP_SW2_TX_STREAM5_EN_STATUS 0x009248 1569 #define ACP_SW2_TX_STREAM6_EN_STATUS 0x00924C 1570 #define ACP_SW2_TX_STREAM7_EN_STATUS 0x009250 1571 #define ACP_SW2_TX_DP0_FRAME_FORMAT 0x009254 1572 #define ACP_SW2_TX_DP1_FRAME_FORMAT 0x009258 1573 #define ACP_SW2_TX_DP2_FRAME_FORMAT 0x00925C 1574 #define ACP_SW2_TX_DP3_FRAME_FORMAT 0x009260 1575 #define ACP_SW2_TX_DP4_FRAME_FORMAT 0x009264 1576 #define ACP_SW2_TX_DP5_FRAME_FORMAT 0x009268 1577 #define ACP_SW2_TX_DP6_FRAME_FORMAT 0x00926C 1578 #define ACP_SW2_TX_DP7_FRAME_FORMAT 0x009270 1579 #define ACP_SW2_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x009280 1580 #define ACP_SW2_TX_DP0_0_HCTRL_BANK0 0x009284 1581 #define ACP_SW2_TX_DP0_0_HCTRL_OFFSET_BANK0 0x009288 1582 #define ACP_SW2_TX_DP0_0_LANE_CTRL_BANK0 0x00928C 1583 #define ACP_SW2_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x009290 1584 #define ACP_SW2_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009294 1585 #define ACP_SW2_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x009298 1586 #define ACP_SW2_TX_DP0_0_HCTRL_BANK1 0x00929C 1587 #define ACP_SW2_TX_DP0_0_HCTRL_OFFSET_BANK1 0x0092A0 1588 #define ACP_SW2_TX_DP0_0_LANE_CTRL_BANK1 0x0092A4 1589 #define ACP_SW2_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x0092A8 1590 #define ACP_SW2_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0092AC 1591 #define ACP_SW2_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x0092B0 1592 #define ACP_SW2_TX_DP0_1_HCTRL_BANK0 0x0092B4 1593 #define ACP_SW2_TX_DP0_1_HCTRL_OFFSET_BANK0 0x0092B8 1594 #define ACP_SW2_TX_DP0_1_LANE_CTRL_BANK0 0x0092BC 1595 #define ACP_SW2_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x0092C0 1596 #define ACP_SW2_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0092C4 1597 #define ACP_SW2_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x0092C8 1598 #define ACP_SW2_TX_DP0_1_HCTRL_BANK1 0x0092CC 1599 #define ACP_SW2_TX_DP0_1_HCTRL_OFFSET_BANK1 0x0092D0 1600 #define ACP_SW2_TX_DP0_1_LANE_CTRL_BANK1 0x0092D4 1601 #define ACP_SW2_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x0092D8 1602 #define ACP_SW2_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0092DC 1603 #define ACP_SW2_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x0092E0 1604 #define ACP_SW2_TX_DP0_2_HCTRL_BANK0 0x0092E4 1605 #define ACP_SW2_TX_DP0_2_HCTRL_OFFSET_BANK0 0x0092E8 1606 #define ACP_SW2_TX_DP0_2_LANE_CTRL_BANK0 0x0092EC 1607 #define ACP_SW2_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x0092F0 1608 #define ACP_SW2_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0092F4 1609 #define ACP_SW2_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x0092F8 1610 #define ACP_SW2_TX_DP0_2_HCTRL_BANK1 0x0092FC 1611 #define ACP_SW2_TX_DP0_2_HCTRL_OFFSET_BANK1 0x009300 1612 #define ACP_SW2_TX_DP0_2_LANE_CTRL_BANK1 0x009304 1613 #define ACP_SW2_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x009308 1614 #define ACP_SW2_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00930C 1615 #define ACP_SW2_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x009310 1616 #define ACP_SW2_TX_DP0_3_HCTRL_BANK0 0x009314 1617 #define ACP_SW2_TX_DP0_3_HCTRL_OFFSET_BANK0 0x009318 1618 #define ACP_SW2_TX_DP0_3_LANE_CTRL_BANK0 0x00931C 1619 #define ACP_SW2_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x009320 1620 #define ACP_SW2_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009324 1621 #define ACP_SW2_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x009328 1622 #define ACP_SW2_TX_DP0_3_HCTRL_BANK1 0x00932C 1623 #define ACP_SW2_TX_DP0_3_HCTRL_OFFSET_BANK1 0x009330 1624 #define ACP_SW2_TX_DP0_3_LANE_CTRL_BANK1 0x009334 1625 #define ACP_SW2_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x009338 1626 #define ACP_SW2_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00933C 1627 #define ACP_SW2_TX_DP1_SAMPLEINTERVAL_BANK0 0x009370 1628 #define ACP_SW2_TX_DP1_HCTRL_BANK0 0x009374 1629 #define ACP_SW2_TX_DP1_HCTRL_OFFSET_BANK0 0x009378 1630 #define ACP_SW2_TX_DP1_LANE_CTRL_BANK0 0x00937C 1631 #define ACP_SW2_TX_DP1_CHANNEL_ENABLE_BANK0 0x009380 1632 #define ACP_SW2_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009384 1633 #define ACP_SW2_TX_DP1_SAMPLEINTERVAL_BANK1 0x009388 1634 #define ACP_SW2_TX_DP1_HCTRL_BANK1 0x00938C 1635 #define ACP_SW2_TX_DP1_HCTRL_OFFSET_BANK1 0x009390 1636 #define ACP_SW2_TX_DP1_LANE_CTRL_BANK1 0x009394 1637 #define ACP_SW2_TX_DP1_CHANNEL_ENABLE_BANK1 0x009398 1638 #define ACP_SW2_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00939C 1639 #define ACP_SW2_TX_DP2_SAMPLEINTERVAL_BANK0 0x0093A0 1640 #define ACP_SW2_TX_DP2_HCTRL_BANK0 0x0093A4 1641 #define ACP_SW2_TX_DP2_HCTRL_OFFSET_BANK0 0x0093A8 1642 #define ACP_SW2_TX_DP2_LANE_CTRL_BANK0 0x0093AC 1643 #define ACP_SW2_TX_DP2_CHANNEL_ENABLE_BANK0 0x0093B0 1644 #define ACP_SW2_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0093B4 1645 #define ACP_SW2_TX_DP2_SAMPLEINTERVAL_BANK1 0x0093B8 1646 #define ACP_SW2_TX_DP2_HCTRL_BANK1 0x0093BC 1647 #define ACP_SW2_TX_DP2_HCTRL_OFFSET_BANK1 0x0093C0 1648 #define ACP_SW2_TX_DP2_LANE_CTRL_BANK1 0x0093C4 1649 #define ACP_SW2_TX_DP2_CHANNEL_ENABLE_BANK1 0x0093C8 1650 #define ACP_SW2_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0093CC 1651 #define ACP_SW2_TX_DP3_SAMPLEINTERVAL_BANK0 0x0093D0 1652 #define ACP_SW2_TX_DP3_HCTRL_BANK0 0x0093D4 1653 #define ACP_SW2_TX_DP3_HCTRL_OFFSET_BANK0 0x0093D8 1654 #define ACP_SW2_TX_DP3_LANE_CTRL_BANK0 0x0093DC 1655 #define ACP_SW2_TX_DP3_CHANNEL_ENABLE_BANK0 0x0093E0 1656 #define ACP_SW2_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0093E4 1657 #define ACP_SW2_TX_DP3_SAMPLEINTERVAL_BANK1 0x0093E8 1658 #define ACP_SW2_TX_DP3_HCTRL_BANK1 0x0093EC 1659 #define ACP_SW2_TX_DP3_HCTRL_OFFSET_BANK1 0x0093F0 1660 #define ACP_SW2_TX_DP3_LANE_CTRL_BANK1 0x0093F4 1661 #define ACP_SW2_TX_DP3_CHANNEL_ENABLE_BANK1 0x0093F8 1662 #define ACP_SW2_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0093FC 1663 #define ACP_SW2_TX_DP4_SAMPLEINTERVAL_BANK0 0x009400 1664 #define ACP_SW2_TX_DP4_HCTRL_BANK0 0x009404 1665 #define ACP_SW2_TX_DP4_HCTRL_OFFSET_BANK0 0x009408 1666 #define ACP_SW2_TX_DP4_LANE_CTRL_BANK0 0x00940C 1667 #define ACP_SW2_TX_DP4_CHANNEL_ENABLE_BANK0 0x009410 1668 #define ACP_SW2_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009414 1669 #define ACP_SW2_TX_DP4_SAMPLEINTERVAL_BANK1 0x009418 1670 #define ACP_SW2_TX_DP4_HCTRL_BANK1 0x00941C 1671 #define ACP_SW2_TX_DP4_HCTRL_OFFSET_BANK1 0x009420 1672 #define ACP_SW2_TX_DP4_LANE_CTRL_BANK1 0x009424 1673 #define ACP_SW2_TX_DP4_CHANNEL_ENABLE_BANK1 0x009428 1674 #define ACP_SW2_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00942C 1675 #define ACP_SW2_TX_DP5_SAMPLEINTERVAL_BANK0 0x009430 1676 #define ACP_SW2_TX_DP5_HCTRL_BANK0 0x009434 1677 #define ACP_SW2_TX_DP5_HCTRL_OFFSET_BANK0 0x009438 1678 #define ACP_SW2_TX_DP5_LANE_CTRL_BANK0 0x00943C 1679 #define ACP_SW2_TX_DP5_CHANNEL_ENABLE_BANK0 0x009440 1680 #define ACP_SW2_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009444 1681 #define ACP_SW2_TX_DP5_SAMPLEINTERVAL_BANK1 0x009448 1682 #define ACP_SW2_TX_DP5_HCTRL_BANK1 0x00944C 1683 #define ACP_SW2_TX_DP5_HCTRL_OFFSET_BANK1 0x009450 1684 #define ACP_SW2_TX_DP5_LANE_CTRL_BANK1 0x009454 1685 #define ACP_SW2_TX_DP5_CHANNEL_ENABLE_BANK1 0x009458 1686 #define ACP_SW2_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00945C 1687 #define ACP_SW2_TX_DP6_SAMPLEINTERVAL_BANK0 0x009460 1688 #define ACP_SW2_TX_DP6_HCTRL_BANK0 0x009464 1689 #define ACP_SW2_TX_DP6_HCTRL_OFFSET_BANK0 0x009468 1690 #define ACP_SW2_TX_DP6_LANE_CTRL_BANK0 0x00946C 1691 #define ACP_SW2_TX_DP6_CHANNEL_ENABLE_BANK0 0x009470 1692 #define ACP_SW2_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009474 1693 #define ACP_SW2_TX_DP6_SAMPLEINTERVAL_BANK1 0x009478 1694 #define ACP_SW2_TX_DP6_HCTRL_BANK1 0x00947C 1695 #define ACP_SW2_TX_DP6_HCTRL_OFFSET_BANK1 0x009480 1696 #define ACP_SW2_TX_DP6_LANE_CTRL_BANK1 0x009484 1697 #define ACP_SW2_TX_DP6_CHANNEL_ENABLE_BANK1 0x009488 1698 #define ACP_SW2_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00948C 1699 #define ACP_SW2_TX_DP7_SAMPLEINTERVAL_BANK0 0x009490 1700 #define ACP_SW2_TX_DP7_HCTRL_BANK0 0x009494 1701 #define ACP_SW2_TX_DP7_HCTRL_OFFSET_BANK0 0x009498 1702 #define ACP_SW2_TX_DP7_LANE_CTRL_BANK0 0x00949C 1703 #define ACP_SW2_TX_DP7_CHANNEL_ENABLE_BANK0 0x0094A0 1704 #define ACP_SW2_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0094A4 1705 #define ACP_SW2_TX_DP7_SAMPLEINTERVAL_BANK1 0x0094A8 1706 #define ACP_SW2_TX_DP7_HCTRL_BANK1 0x0094AC 1707 #define ACP_SW2_TX_DP7_HCTRL_OFFSET_BANK1 0x0094B0 1708 #define ACP_SW2_TX_DP7_LANE_CTRL_BANK1 0x0094B4 1709 #define ACP_SW2_TX_DP7_CHANNEL_ENABLE_BANK1 0x0094B8 1710 #define ACP_SW2_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0094BC 1711 #define ACP_SW2_RX_STREAM0_EN 0x009514 1712 #define ACP_SW2_RX_STREAM1_EN 0x009518 1713 #define ACP_SW2_RX_STREAM2_EN 0x00951C 1714 #define ACP_SW2_RX_STREAM3_EN 0x009520 1715 #define ACP_SW2_RX_STREAM4_EN 0x009524 1716 #define ACP_SW2_RX_STREAM5_EN 0x009528 1717 #define ACP_SW2_RX_STREAM6_EN 0x00952C 1718 #define ACP_SW2_RX_STREAM7_EN 0x009530 1719 #define ACP_SW2_RX_STREAM0_EN_STATUS 0x009534 1720 #define ACP_SW2_RX_STREAM1_EN_STATUS 0x009538 1721 #define ACP_SW2_RX_STREAM2_EN_STATUS 0x00953C 1722 #define ACP_SW2_RX_STREAM3_EN_STATUS 0x009540 1723 #define ACP_SW2_RX_STREAM4_EN_STATUS 0x009544 1724 #define ACP_SW2_RX_STREAM5_EN_STATUS 0x009548 1725 #define ACP_SW2_RX_STREAM6_EN_STATUS 0x00954C 1726 #define ACP_SW2_RX_STREAM7_EN_STATUS 0x009550 1727 #define ACP_SW2_RX_DP0_FRAME_FORMAT 0x009554 1728 #define ACP_SW2_RX_DP1_FRAME_FORMAT 0x009558 1729 #define ACP_SW2_RX_DP2_FRAME_FORMAT 0x00955C 1730 #define ACP_SW2_RX_DP3_FRAME_FORMAT 0x009560 1731 #define ACP_SW2_RX_DP4_FRAME_FORMAT 0x009564 1732 #define ACP_SW2_RX_DP5_FRAME_FORMAT 0x009568 1733 #define ACP_SW2_RX_DP6_FRAME_FORMAT 0x00956C 1734 #define ACP_SW2_RX_DP7_FRAME_FORMAT 0x009570 1735 #define ACP_SW2_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x009580 1736 #define ACP_SW2_RX_DP0_0_HCTRL_BANK0 0x009584 1737 #define ACP_SW2_RX_DP0_0_HCTRL_OFFSET_BANK0 0x009588 1738 #define ACP_SW2_RX_DP0_0_LANE_CTRL_BANK0 0x00958C 1739 #define ACP_SW2_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x009590 1740 #define ACP_SW2_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009594 1741 #define ACP_SW2_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x009598 1742 #define ACP_SW2_RX_DP0_0_HCTRL_BANK1 0x00959C 1743 #define ACP_SW2_RX_DP0_0_HCTRL_OFFSET_BANK1 0x0095A0 1744 #define ACP_SW2_RX_DP0_0_LANE_CTRL_BANK1 0x0095A4 1745 #define ACP_SW2_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x0095A8 1746 #define ACP_SW2_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0095AC 1747 #define ACP_SW2_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x0095B0 1748 #define ACP_SW2_RX_DP0_1_HCTRL_BANK0 0x0095B4 1749 #define ACP_SW2_RX_DP0_1_HCTRL_OFFSET_BANK0 0x0095B8 1750 #define ACP_SW2_RX_DP0_1_LANE_CTRL_BANK0 0x0095BC 1751 #define ACP_SW2_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x0095C0 1752 #define ACP_SW2_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0095C4 1753 #define ACP_SW2_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x0095C8 1754 #define ACP_SW2_RX_DP0_1_HCTRL_BANK1 0x0095CC 1755 #define ACP_SW2_RX_DP0_1_HCTRL_OFFSET_BANK1 0x0095D0 1756 #define ACP_SW2_RX_DP0_1_LANE_CTRL_BANK1 0x0095D4 1757 #define ACP_SW2_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x0095D8 1758 #define ACP_SW2_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0095DC 1759 #define ACP_SW2_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x0095E0 1760 #define ACP_SW2_RX_DP0_2_HCTRL_BANK0 0x0095E4 1761 #define ACP_SW2_RX_DP0_2_HCTRL_OFFSET_BANK0 0x0095E8 1762 #define ACP_SW2_RX_DP0_2_LANE_CTRL_BANK0 0x0095EC 1763 #define ACP_SW2_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x0095F0 1764 #define ACP_SW2_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0095F4 1765 #define ACP_SW2_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x0095F8 1766 #define ACP_SW2_RX_DP0_2_HCTRL_BANK1 0x0095FC 1767 #define ACP_SW2_RX_DP0_2_HCTRL_OFFSET_BANK1 0x009600 1768 #define ACP_SW2_RX_DP0_2_LANE_CTRL_BANK1 0x009604 1769 #define ACP_SW2_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x009608 1770 #define ACP_SW2_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00960C 1771 #define ACP_SW2_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x009610 1772 #define ACP_SW2_RX_DP0_3_HCTRL_BANK0 0x009614 1773 #define ACP_SW2_RX_DP0_3_HCTRL_OFFSET_BANK0 0x009618 1774 #define ACP_SW2_RX_DP0_3_LANE_CTRL_BANK0 0x00961C 1775 #define ACP_SW2_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x009620 1776 #define ACP_SW2_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009624 1777 #define ACP_SW2_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x009628 1778 #define ACP_SW2_RX_DP0_3_HCTRL_BANK1 0x00962C 1779 #define ACP_SW2_RX_DP0_3_HCTRL_OFFSET_BANK1 0x009630 1780 #define ACP_SW2_RX_DP0_3_LANE_CTRL_BANK1 0x009634 1781 #define ACP_SW2_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x009638 1782 #define ACP_SW2_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00963C 1783 #define ACP_SW2_RX_DP1_SAMPLEINTERVAL_BANK0 0x009670 1784 #define ACP_SW2_RX_DP1_HCTRL_BANK0 0x009674 1785 #define ACP_SW2_RX_DP1_HCTRL_OFFSET_BANK0 0x009678 1786 #define ACP_SW2_RX_DP1_LANE_CTRL_BANK0 0x00967C 1787 #define ACP_SW2_RX_DP1_CHANNEL_ENABLE_BANK0 0x009680 1788 #define ACP_SW2_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009684 1789 #define ACP_SW2_RX_DP1_SAMPLEINTERVAL_BANK1 0x009688 1790 #define ACP_SW2_RX_DP1_HCTRL_BANK1 0x00968C 1791 #define ACP_SW2_RX_DP1_HCTRL_OFFSET_BANK1 0x009690 1792 #define ACP_SW2_RX_DP1_LANE_CTRL_BANK1 0x009694 1793 #define ACP_SW2_RX_DP1_CHANNEL_ENABLE_BANK1 0x009698 1794 #define ACP_SW2_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00969C 1795 #define ACP_SW2_RX_DP2_SAMPLEINTERVAL_BANK0 0x0096A0 1796 #define ACP_SW2_RX_DP2_HCTRL_BANK0 0x0096A4 1797 #define ACP_SW2_RX_DP2_HCTRL_OFFSET_BANK0 0x0096A8 1798 #define ACP_SW2_RX_DP2_LANE_CTRL_BANK0 0x0096AC 1799 #define ACP_SW2_RX_DP2_CHANNEL_ENABLE_BANK0 0x0096B0 1800 #define ACP_SW2_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0096B4 1801 #define ACP_SW2_RX_DP2_SAMPLEINTERVAL_BANK1 0x0096B8 1802 #define ACP_SW2_RX_DP2_HCTRL_BANK1 0x0096BC 1803 #define ACP_SW2_RX_DP2_HCTRL_OFFSET_BANK1 0x0096C0 1804 #define ACP_SW2_RX_DP2_LANE_CTRL_BANK1 0x0096C4 1805 #define ACP_SW2_RX_DP2_CHANNEL_ENABLE_BANK1 0x0096C8 1806 #define ACP_SW2_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0096CC 1807 #define ACP_SW2_RX_DP3_SAMPLEINTERVAL_BANK0 0x0096D0 1808 #define ACP_SW2_RX_DP3_HCTRL_BANK0 0x0096D4 1809 #define ACP_SW2_RX_DP3_HCTRL_OFFSET_BANK0 0x0096D8 1810 #define ACP_SW2_RX_DP3_LANE_CTRL_BANK0 0x0096DC 1811 #define ACP_SW2_RX_DP3_CHANNEL_ENABLE_BANK0 0x0096E0 1812 #define ACP_SW2_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0096E4 1813 #define ACP_SW2_RX_DP3_SAMPLEINTERVAL_BANK1 0x0096E8 1814 #define ACP_SW2_RX_DP3_HCTRL_BANK1 0x0096EC 1815 #define ACP_SW2_RX_DP3_HCTRL_OFFSET_BANK1 0x0096F0 1816 #define ACP_SW2_RX_DP3_LANE_CTRL_BANK1 0x0096F4 1817 #define ACP_SW2_RX_DP3_CHANNEL_ENABLE_BANK1 0x0096F8 1818 #define ACP_SW2_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0096FC 1819 #define ACP_SW2_RX_DP4_SAMPLEINTERVAL_BANK0 0x009700 1820 #define ACP_SW2_RX_DP4_HCTRL_BANK0 0x009704 1821 #define ACP_SW2_RX_DP4_HCTRL_OFFSET_BANK0 0x009708 1822 #define ACP_SW2_RX_DP4_LANE_CTRL_BANK0 0x00970C 1823 #define ACP_SW2_RX_DP4_CHANNEL_ENABLE_BANK0 0x009710 1824 #define ACP_SW2_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009714 1825 #define ACP_SW2_RX_DP4_SAMPLEINTERVAL_BANK1 0x009718 1826 #define ACP_SW2_RX_DP4_HCTRL_BANK1 0x00971C 1827 #define ACP_SW2_RX_DP4_HCTRL_OFFSET_BANK1 0x009720 1828 #define ACP_SW2_RX_DP4_LANE_CTRL_BANK1 0x009724 1829 #define ACP_SW2_RX_DP4_CHANNEL_ENABLE_BANK1 0x009728 1830 #define ACP_SW2_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00972C 1831 #define ACP_SW2_RX_DP5_SAMPLEINTERVAL_BANK0 0x009730 1832 #define ACP_SW2_RX_DP5_HCTRL_BANK0 0x009734 1833 #define ACP_SW2_RX_DP5_HCTRL_OFFSET_BANK0 0x009738 1834 #define ACP_SW2_RX_DP5_LANE_CTRL_BANK0 0x00973C 1835 #define ACP_SW2_RX_DP5_CHANNEL_ENABLE_BANK0 0x009740 1836 #define ACP_SW2_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009744 1837 #define ACP_SW2_RX_DP5_SAMPLEINTERVAL_BANK1 0x009748 1838 #define ACP_SW2_RX_DP5_HCTRL_BANK1 0x00974C 1839 #define ACP_SW2_RX_DP5_HCTRL_OFFSET_BANK1 0x009750 1840 #define ACP_SW2_RX_DP5_LANE_CTRL_BANK1 0x009754 1841 #define ACP_SW2_RX_DP5_CHANNEL_ENABLE_BANK1 0x009758 1842 #define ACP_SW2_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00975C 1843 #define ACP_SW2_RX_DP6_SAMPLEINTERVAL_BANK0 0x009760 1844 #define ACP_SW2_RX_DP6_HCTRL_BANK0 0x009764 1845 #define ACP_SW2_RX_DP6_HCTRL_OFFSET_BANK0 0x009768 1846 #define ACP_SW2_RX_DP6_LANE_CTRL_BANK0 0x00976C 1847 #define ACP_SW2_RX_DP6_CHANNEL_ENABLE_BANK0 0x009770 1848 #define ACP_SW2_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009774 1849 #define ACP_SW2_RX_DP6_SAMPLEINTERVAL_BANK1 0x009778 1850 #define ACP_SW2_RX_DP6_HCTRL_BANK1 0x00977C 1851 #define ACP_SW2_RX_DP6_HCTRL_OFFSET_BANK1 0x009780 1852 #define ACP_SW2_RX_DP6_LANE_CTRL_BANK1 0x009784 1853 #define ACP_SW2_RX_DP6_CHANNEL_ENABLE_BANK1 0x009788 1854 #define ACP_SW2_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00978C 1855 #define ACP_SW2_RX_DP7_SAMPLEINTERVAL_BANK0 0x009790 1856 #define ACP_SW2_RX_DP7_HCTRL_BANK0 0x009794 1857 #define ACP_SW2_RX_DP7_HCTRL_OFFSET_BANK0 0x009798 1858 #define ACP_SW2_RX_DP7_LANE_CTRL_BANK0 0x00979C 1859 #define ACP_SW2_RX_DP7_CHANNEL_ENABLE_BANK0 0x0097A0 1860 #define ACP_SW2_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0097A4 1861 #define ACP_SW2_RX_DP7_SAMPLEINTERVAL_BANK1 0x0097A8 1862 #define ACP_SW2_RX_DP7_HCTRL_BANK1 0x0097AC 1863 #define ACP_SW2_RX_DP7_HCTRL_OFFSET_BANK1 0x0097B0 1864 #define ACP_SW2_RX_DP7_LANE_CTRL_BANK1 0x0097B4 1865 #define ACP_SW2_RX_DP7_CHANNEL_ENABLE_BANK1 0x0097B8 1866 #define ACP_SW2_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0097BC 1867 #define ACP_SW2_BPT_PORT_EN 0x0097C0 1868 #define ACP_SW2_BPT_PORT_EN_STATUS 0x0097C4 1869 #define ACP_SW2_BPT_PORT_FRAME_FORMAT 0x0097C8 1870 #define ACP_SW2_BPT_PORT_SAMPLEINTERVAL_BANK0 0x0097CC 1871 #define ACP_SW2_BPT_PORT_HCTRL_BANK0 0x0097D0 1872 #define ACP_SW2_BPT_PORT_OFFSET_BANK0 0x0097D4 1873 #define ACP_SW2_BPT_PORT_LANE_SELECT_BANK0 0x0097D8 1874 #define ACP_SW2_BPT_PORT_CHANNEL_ENABLE_BANK0 0x0097DC 1875 #define ACP_SW2_BPT_PORT_SAMPLEINTERVAL_BANK1 0x0097E0 1876 #define ACP_SW2_BPT_PORT_HCTRL_BANK1 0x0097E4 1877 #define ACP_SW2_BPT_PORT_OFFSET_BANK1 0x0097E8 1878 #define ACP_SW2_BPT_PORT_LANE_SELECT_BANK1 0x0097EC 1879 #define ACP_SW2_BPT_PORT_CHANNEL_ENABLE_BANK1 0x0097F0 1880 #define ACP_SW2_BPT_PORT_FIRST_BYTE_ADDR 0x0097F4 1881 #define ACP_SW2_CLK_RESUME_CTRL 0x0097F8 1882 #define ACP_SW2_CLK_RESUME_DELAY_CNTR 0x0097FC 1883 #define ACP_SW2_BUS_RESET_CTRL 0x009800 1884 #define ACP_SW2_PRBS_ERR_STATUS 0x009804 1885 #define ACP_SW2_WALLCLK_MISC 0x009808 1886 #define ACP_SW2_WALL_CLK_COUNTER 0x00980C 1887 #define ACP_SW2_PING_STATUS_REGISTER_LOW 0x009810 1888 #define ACP_SW2_PING_STATUS_REGISTER_HIGH 0x009814 1889 #define ACP_SW2_PING_STATUS_CURRENT_BANK_SEL 0x009818 1890 #define ACP_SW2_TZD_CHANGE 0x00981C 1891 #define ACP_SW2_WALLCLK_INTR_CNTL 0x009820 1892 1893 #define ACP_SW3_GLOBAL_CAPABILITIES 0x00AE00 1894 #define ACP_SW3_RX_DMA0_RINGBUFADDR 0x00AE04 1895 #define ACP_SW3_RX_DMA0_RINGBUFSIZE 0x00AE08 1896 #define ACP_SW3_RX_DMA0_FIFOADDR 0x00AE0C 1897 #define ACP_SW3_RX_DMA0_FIFOSIZE 0x00AE10 1898 #define ACP_SW3_RX_DMA0_BURST_SIZE 0x00AE14 1899 #define ACP_SW3_RX_DMA0_LINKPOSITIONCNTR 0x00AE18 1900 #define ACP_SW3_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x00AE1C 1901 #define ACP_SW3_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x00AE20 1902 #define ACP_SW3_RX_DMA0_INTR_WATERMARK_SIZE 0x00AE24 1903 #define ACP_SW3_RX_DMA1_RINGBUFADDR 0x00AE28 1904 #define ACP_SW3_RX_DMA1_RINGBUFSIZE 0x00AE2C 1905 #define ACP_SW3_RX_DMA1_FIFOADDR 0x00AE30 1906 #define ACP_SW3_RX_DMA1_FIFOSIZE 0x00AE34 1907 #define ACP_SW3_RX_DMA1_BURST_SIZE 0x00AE38 1908 #define ACP_SW3_RX_DMA1_LINKPOSITIONCNTR 0x00AE3C 1909 #define ACP_SW3_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x00AE40 1910 #define ACP_SW3_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x00AE44 1911 #define ACP_SW3_RX_DMA1_INTR_WATERMARK_SIZE 0x00AE48 1912 #define ACP_SW3_RX_DMA2_RINGBUFADDR 0x00AE4C 1913 #define ACP_SW3_RX_DMA2_RINGBUFSIZE 0x00AE50 1914 #define ACP_SW3_RX_DMA2_FIFOADDR 0x00AE54 1915 #define ACP_SW3_RX_DMA2_FIFOSIZE 0x00AE58 1916 #define ACP_SW3_RX_DMA2_BURST_SIZE 0x00AE5C 1917 #define ACP_SW3_RX_DMA2_LINKPOSITIONCNTR 0x00AE60 1918 #define ACP_SW3_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x00AE64 1919 #define ACP_SW3_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x00AE68 1920 #define ACP_SW3_RX_DMA2_INTR_WATERMARK_SIZE 0x00AE6C 1921 #define ACP_SW3_RX_DMA3_RINGBUFADDR 0x00AE70 1922 #define ACP_SW3_RX_DMA3_RINGBUFSIZE 0x00AE74 1923 #define ACP_SW3_RX_DMA3_FIFOADDR 0x00AE78 1924 #define ACP_SW3_RX_DMA3_FIFOSIZE 0x00AE7C 1925 #define ACP_SW3_RX_DMA3_BURST_SIZE 0x00AE80 1926 #define ACP_SW3_RX_DMA3_LINKPOSITIONCNTR 0x00AE84 1927 #define ACP_SW3_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x00AE88 1928 #define ACP_SW3_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x00AE8C 1929 #define ACP_SW3_RX_DMA3_INTR_WATERMARK_SIZE 0x00AE90 1930 #define ACP_SW3_RX_DMA4_RINGBUFADDR 0x00AE94 1931 #define ACP_SW3_RX_DMA4_RINGBUFSIZE 0x00AE98 1932 #define ACP_SW3_RX_DMA4_FIFOADDR 0x00AE9C 1933 #define ACP_SW3_RX_DMA4_FIFOSIZE 0x00AEA0 1934 #define ACP_SW3_RX_DMA4_BURST_SIZE 0x00AEA4 1935 #define ACP_SW3_RX_DMA4_LINKPOSITIONCNTR 0x00AEA8 1936 #define ACP_SW3_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x00AEAC 1937 #define ACP_SW3_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x00AEB0 1938 #define ACP_SW3_RX_DMA4_INTR_WATERMARK_SIZE 0x00AEB4 1939 #define ACP_SW3_RX_DMA5_RINGBUFADDR 0x00AEB8 1940 #define ACP_SW3_RX_DMA5_RINGBUFSIZE 0x00AEBC 1941 #define ACP_SW3_RX_DMA5_FIFOADDR 0x00AEC0 1942 #define ACP_SW3_RX_DMA5_FIFOSIZE 0x00AEC4 1943 #define ACP_SW3_RX_DMA5_BURST_SIZE 0x00AEC8 1944 #define ACP_SW3_RX_DMA5_LINKPOSITIONCNTR 0x00AECC 1945 #define ACP_SW3_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x00AED0 1946 #define ACP_SW3_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x00AED4 1947 #define ACP_SW3_RX_DMA5_INTR_WATERMARK_SIZE 0x00AED8 1948 #define ACP_SW3_RX_DMA6_RINGBUFADDR 0x00AEDC 1949 #define ACP_SW3_RX_DMA6_RINGBUFSIZE 0x00AEE0 1950 #define ACP_SW3_RX_DMA6_FIFOADDR 0x00AEE4 1951 #define ACP_SW3_RX_DMA6_FIFOSIZE 0x00AEE8 1952 #define ACP_SW3_RX_DMA6_BURST_SIZE 0x00AEEC 1953 #define ACP_SW3_RX_DMA6_LINKPOSITIONCNTR 0x00AEF0 1954 #define ACP_SW3_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x00AEF4 1955 #define ACP_SW3_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x00AEF8 1956 #define ACP_SW3_RX_DMA6_INTR_WATERMARK_SIZE 0x00AEFC 1957 #define ACP_SW3_RX_DMA7_RINGBUFADDR 0x00AF00 1958 #define ACP_SW3_RX_DMA7_RINGBUFSIZE 0x00AF04 1959 #define ACP_SW3_RX_DMA7_FIFOADDR 0x00AF08 1960 #define ACP_SW3_RX_DMA7_FIFOSIZE 0x00AF0C 1961 #define ACP_SW3_RX_DMA7_BURST_SIZE 0x00AF10 1962 #define ACP_SW3_RX_DMA7_LINKPOSITIONCNTR 0x00AF14 1963 #define ACP_SW3_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x00AF18 1964 #define ACP_SW3_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x00AF1C 1965 #define ACP_SW3_RX_DMA7_INTR_WATERMARK_SIZE 0x00AF20 1966 #define ACP_SW3_TX_DMA0_RINGBUFADDR 0x00AF24 1967 #define ACP_SW3_TX_DMA0_RINGBUFSIZE 0x00AF28 1968 #define ACP_SW3_TX_DMA0_FIFOADDR 0x00AF2C 1969 #define ACP_SW3_TX_DMA0_FIFOSIZE 0x00AF30 1970 #define ACP_SW3_TX_DMA0_BURST_SIZE 0x00AF34 1971 #define ACP_SW3_TX_DMA0_LINKPOSITIONCNTR 0x00AF38 1972 #define ACP_SW3_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x00AF3C 1973 #define ACP_SW3_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x00AF40 1974 #define ACP_SW3_TX_DMA0_INTR_WATERMARK_SIZE 0x00AF44 1975 #define ACP_SW3_TX_DMA1_RINGBUFADDR 0x00AF48 1976 #define ACP_SW3_TX_DMA1_RINGBUFSIZE 0x00AF4C 1977 #define ACP_SW3_TX_DMA1_FIFOADDR 0x00AF50 1978 #define ACP_SW3_TX_DMA1_FIFOSIZE 0x00AF54 1979 #define ACP_SW3_TX_DMA1_BURST_SIZE 0x00AF58 1980 #define ACP_SW3_TX_DMA1_LINKPOSITIONCNTR 0x00AF5C 1981 #define ACP_SW3_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x00AF60 1982 #define ACP_SW3_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x00AF64 1983 #define ACP_SW3_TX_DMA1_INTR_WATERMARK_SIZE 0x00AF68 1984 #define ACP_SW3_TX_DMA2_RINGBUFADDR 0x00AF6C 1985 #define ACP_SW3_TX_DMA2_RINGBUFSIZE 0x00AF70 1986 #define ACP_SW3_TX_DMA2_FIFOADDR 0x00AF74 1987 #define ACP_SW3_TX_DMA2_FIFOSIZE 0x00AF78 1988 #define ACP_SW3_TX_DMA2_BURST_SIZE 0x00AF7C 1989 #define ACP_SW3_TX_DMA2_LINKPOSITIONCNTR 0x00AF80 1990 #define ACP_SW3_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x00AF84 1991 #define ACP_SW3_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x00AF88 1992 #define ACP_SW3_TX_DMA2_INTR_WATERMARK_SIZE 0x00AF8C 1993 #define ACP_SW3_TX_DMA3_RINGBUFADDR 0x00AF90 1994 #define ACP_SW3_TX_DMA3_RINGBUFSIZE 0x00AF94 1995 #define ACP_SW3_TX_DMA3_FIFOADDR 0x00AF98 1996 #define ACP_SW3_TX_DMA3_FIFOSIZE 0x00AF9C 1997 #define ACP_SW3_TX_DMA3_BURST_SIZE 0x00AFA0 1998 #define ACP_SW3_TX_DMA3_LINKPOSITIONCNTR 0x00AFA4 1999 #define ACP_SW3_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x00AFA8 2000 #define ACP_SW3_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x00AFAC 2001 #define ACP_SW3_TX_DMA3_INTR_WATERMARK_SIZE 0x00AFB0 2002 #define ACP_SW3_TX_DMA4_RINGBUFADDR 0x00AFB4 2003 #define ACP_SW3_TX_DMA4_RINGBUFSIZE 0x00AFB8 2004 #define ACP_SW3_TX_DMA4_FIFOADDR 0x00AFBC 2005 #define ACP_SW3_TX_DMA4_FIFOSIZE 0x00AFC0 2006 #define ACP_SW3_TX_DMA4_BURST_SIZE 0x00AFC4 2007 #define ACP_SW3_TX_DMA4_LINKPOSITIONCNTR 0x00AFC8 2008 #define ACP_SW3_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x00AFCC 2009 #define ACP_SW3_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x00AFD0 2010 #define ACP_SW3_TX_DMA4_INTR_WATERMARK_SIZE 0x00AFD4 2011 #define ACP_SW3_TX_DMA5_RINGBUFADDR 0x00AFD8 2012 #define ACP_SW3_TX_DMA5_RINGBUFSIZE 0x00AFDC 2013 #define ACP_SW3_TX_DMA5_FIFOADDR 0x00AFE0 2014 #define ACP_SW3_TX_DMA5_FIFOSIZE 0x00AFE4 2015 #define ACP_SW3_TX_DMA5_BURST_SIZE 0x00AFE8 2016 #define ACP_SW3_TX_DMA5_LINKPOSITIONCNTR 0x00AFEC 2017 #define ACP_SW3_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x00AFF0 2018 #define ACP_SW3_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x00AFF4 2019 #define ACP_SW3_TX_DMA5_INTR_WATERMARK_SIZE 0x00AFF8 2020 #define ACP_SW3_TX_DMA6_RINGBUFADDR 0x00AFFC 2021 #define ACP_SW3_TX_DMA6_RINGBUFSIZE 0x00B000 2022 #define ACP_SW3_TX_DMA6_FIFOADDR 0x00B004 2023 #define ACP_SW3_TX_DMA6_FIFOSIZE 0x00B008 2024 #define ACP_SW3_TX_DMA6_BURST_SIZE 0x00B00C 2025 #define ACP_SW3_TX_DMA6_LINKPOSITIONCNTR 0x00B010 2026 #define ACP_SW3_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x00B014 2027 #define ACP_SW3_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x00B018 2028 #define ACP_SW3_TX_DMA6_INTR_WATERMARK_SIZE 0x00B01C 2029 #define ACP_SW3_TX_DMA7_RINGBUFADDR 0x00B020 2030 #define ACP_SW3_TX_DMA7_RINGBUFSIZE 0x00B024 2031 #define ACP_SW3_TX_DMA7_FIFOADDR 0x00B028 2032 #define ACP_SW3_TX_DMA7_FIFOSIZE 0x00B02C 2033 #define ACP_SW3_TX_DMA7_BURST_SIZE 0x00B030 2034 #define ACP_SW3_TX_DMA7_LINKPOSITIONCNTR 0x00B034 2035 #define ACP_SW3_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x00B038 2036 #define ACP_SW3_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00B03C 2037 #define ACP_SW3_TX_DMA7_INTR_WATERMARK_SIZE 0x00B040 2038 #define ACP_SW3_RX_DMA0_POS_TRACK 0x00B044 2039 #define ACP_SW3_RX_DMA0_POS 0x00B048 2040 #define ACP_SW3_RX_DMA1_POS_TRACK 0x00B04C 2041 #define ACP_SW3_RX_DMA1_POS 0x00B050 2042 #define ACP_SW3_RX_DMA2_POS_TRACK 0x00B054 2043 #define ACP_SW3_RX_DMA2_POS 0x00B058 2044 #define ACP_SW3_RX_DMA3_POS_TRACK 0x00B05C 2045 #define ACP_SW3_RX_DMA3_POS 0x00B060 2046 #define ACP_SW3_RX_DMA4_POS_TRACK 0x00B064 2047 #define ACP_SW3_RX_DMA4_POS 0x00B068 2048 #define ACP_SW3_RX_DMA5_POS_TRACK 0x00B06C 2049 #define ACP_SW3_RX_DMA5_POS 0x00B070 2050 #define ACP_SW3_RX_DMA6_POS_TRACK 0x00B074 2051 #define ACP_SW3_RX_DMA6_POS 0x00B078 2052 #define ACP_SW3_RX_DMA7_POS_TRACK 0x00B07C 2053 #define ACP_SW3_RX_DMA7_POS 0x00B080 2054 #define ACP_SW3_TX_DMA0_POS_TRACK 0x00B084 2055 #define ACP_SW3_TX_DMA0_POS 0x00B088 2056 #define ACP_SW3_TX_DMA1_POS_TRACK 0x00B08C 2057 #define ACP_SW3_TX_DMA1_POS 0x00B090 2058 #define ACP_SW3_TX_DMA2_POS_TRACK 0x00B094 2059 #define ACP_SW3_TX_DMA2_POS 0x00B098 2060 #define ACP_SW3_TX_DMA3_POS_TRACK 0x00B09C 2061 #define ACP_SW3_TX_DMA3_POS 0x00B0A0 2062 #define ACP_SW3_TX_DMA4_POS_TRACK 0x00B0A4 2063 #define ACP_SW3_TX_DMA4_POS 0x00B0A8 2064 #define ACP_SW3_TX_DMA5_POS_TRACK 0x00B0AC 2065 #define ACP_SW3_TX_DMA5_POS 0x00B0B0 2066 #define ACP_SW3_TX_DMA6_POS_TRACK 0x00B0B4 2067 #define ACP_SW3_TX_DMA6_POS 0x00B0B8 2068 #define ACP_SW3_TX_DMA7_POS_TRACK 0x00B0BC 2069 #define ACP_SW3_TX_DMA7_POS 0x00B0C0 2070 #define ACP_SW3_FIFO_ERROR_REASON 0x00B0C4 2071 #define ACP_SW3_FIFO_ERROR_INTR_MASK 0x00B0C8 2072 #define ACP_SW3_ERROR_REASON1 0x00B0CC 2073 #define ACP_SW3_ERROR_INTR_MASK1 0x00B0D0 2074 #define ACP_SW3_ERROR_REASON2 0x00B0D4 2075 #define ACP_SW3_ERROR_INTR_MASK2 0x00B0D8 2076 2077 #define ACP_SW3_CORB_BASE_ADDRESS 0x00B100 2078 #define ACP_SW3_CORB_WRITE_POINTER 0x00B104 2079 #define ACP_SW3_CORB_READ_POINTER 0x00B108 2080 #define ACP_SW3_CORB_CONTROL 0x00B10C 2081 #define ACP_SW3_CORB_SIZE 0x00B114 2082 #define ACP_SW3_RIRB_BASE_ADDRESS 0x00B118 2083 #define ACP_SW3_RIRB_WRITE_POINTER 0x00B11C 2084 #define ACP_SW3_RIRB_RESPONSE_INTERRUPT_COUNT 0x00B120 2085 #define ACP_SW3_RIRB_CONTROL 0x00B124 2086 #define ACP_SW3_RIRB_SIZE 0x00B128 2087 #define ACP_SW3_RIRB_FIFO_MIN_THDL 0x00B12C 2088 #define ACP_SW3_IMM_CMD_UPPER_WORD 0x00B130 2089 #define ACP_SW3_IMM_CMD_LOWER_QWORD 0x00B134 2090 #define ACP_SW3_IMM_RESP_UPPER_WORD 0x00B138 2091 #define ACP_SW3_IMM_RESP_LOWER_QWORD 0x00B13C 2092 #define ACP_SW3_IMM_CMD_STS 0x00B140 2093 #define ACP_SW3_BRA_BASE_ADDRESS 0x00B144 2094 #define ACP_SW3_BRA_TRANSFER_SIZE 0x00B148 2095 #define ACP_SW3_BRA_DMA_BUSY 0x00B14C 2096 #define ACP_SW3_BRA_RESP 0x00B150 2097 #define ACP_SW3_BRA_RESP_FRAME_ADDR 0x00B154 2098 #define ACP_SW3_BRA_CURRENT_TRANSFER_SIZE 0x00B158 2099 #define ACP_SW3_STATE_CHANGE_STATUS_0TO7 0x00B15C 2100 #define ACP_SW3_STATE_CHANGE_STATUS_8TO11 0x00B160 2101 #define ACP_SW3_STATE_CHANGE_STATUS_MASK_0TO7 0x00B164 2102 #define ACP_SW3_STATE_CHANGE_STATUS_MASK_8TO11 0x00B168 2103 #define ACP_SW3_CLK_FREQUENCY_CTRL_BANK0 0x00B16C 2104 #define ACP_SW3_CLK_FREQUENCY_CTRL_BANK1 0x00B170 2105 #define ACP_SW3_ERROR_INTR_MASK 0x00B174 2106 #define ACP_SW3_PHY_TEST_MODE_DATA_OFF 0x00B178 2107 #define ACP_SW3_DATA_TO_PDM_EN 0x00B17C 2108 2109 #define ACP_SW3_EN 0x00B200 2110 #define ACP_SW3_EN_STATUS 0x00B204 2111 #define ACP_SW3_FRAMESIZE_BANK0 0x00B208 2112 #define ACP_SW3_FRAMESIZE_BANK1 0x00B20C 2113 #define ACP_SW3_SSP_COUNTER 0x00B210 2114 #define ACP_SW3_TX_STREAM0_EN 0x00B214 2115 #define ACP_SW3_TX_STREAM1_EN 0x00B218 2116 #define ACP_SW3_TX_STREAM2_EN 0x00B21C 2117 #define ACP_SW3_TX_STREAM3_EN 0x00B220 2118 #define ACP_SW3_TX_STREAM4_EN 0x00B224 2119 #define ACP_SW3_TX_STREAM5_EN 0x00B228 2120 #define ACP_SW3_TX_STREAM6_EN 0x00B22C 2121 #define ACP_SW3_TX_STREAM7_EN 0x00B230 2122 #define ACP_SW3_TX_STREAM0_EN_STATUS 0x00B234 2123 #define ACP_SW3_TX_STREAM1_EN_STATUS 0x00B238 2124 #define ACP_SW3_TX_STREAM2_EN_STATUS 0x00B23C 2125 #define ACP_SW3_TX_STREAM3_EN_STATUS 0x00B240 2126 #define ACP_SW3_TX_STREAM4_EN_STATUS 0x00B244 2127 #define ACP_SW3_TX_STREAM5_EN_STATUS 0x00B248 2128 #define ACP_SW3_TX_STREAM6_EN_STATUS 0x00B24C 2129 #define ACP_SW3_TX_STREAM7_EN_STATUS 0x00B250 2130 #define ACP_SW3_TX_DP0_FRAME_FORMAT 0x00B254 2131 #define ACP_SW3_TX_DP1_FRAME_FORMAT 0x00B258 2132 #define ACP_SW3_TX_DP2_FRAME_FORMAT 0x00B25C 2133 #define ACP_SW3_TX_DP3_FRAME_FORMAT 0x00B260 2134 #define ACP_SW3_TX_DP4_FRAME_FORMAT 0x00B264 2135 #define ACP_SW3_TX_DP5_FRAME_FORMAT 0x00B268 2136 #define ACP_SW3_TX_DP6_FRAME_FORMAT 0x00B26C 2137 #define ACP_SW3_TX_DP7_FRAME_FORMAT 0x00B270 2138 #define ACP_SW3_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x00B280 2139 #define ACP_SW3_TX_DP0_0_HCTRL_BANK0 0x00B284 2140 #define ACP_SW3_TX_DP0_0_HCTRL_OFFSET_BANK0 0x00B288 2141 #define ACP_SW3_TX_DP0_0_LANE_CTRL_BANK0 0x00B28C 2142 #define ACP_SW3_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x00B290 2143 #define ACP_SW3_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B294 2144 #define ACP_SW3_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x00B298 2145 #define ACP_SW3_TX_DP0_0_HCTRL_BANK1 0x00B29C 2146 #define ACP_SW3_TX_DP0_0_HCTRL_OFFSET_BANK1 0x00B2A0 2147 #define ACP_SW3_TX_DP0_0_LANE_CTRL_BANK1 0x00B2A4 2148 #define ACP_SW3_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x00B2A8 2149 #define ACP_SW3_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B2AC 2150 #define ACP_SW3_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x00B2B0 2151 #define ACP_SW3_TX_DP0_1_HCTRL_BANK0 0x00B2B4 2152 #define ACP_SW3_TX_DP0_1_HCTRL_OFFSET_BANK0 0x00B2B8 2153 #define ACP_SW3_TX_DP0_1_LANE_CTRL_BANK0 0x00B2BC 2154 #define ACP_SW3_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x00B2C0 2155 #define ACP_SW3_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B2C4 2156 #define ACP_SW3_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x00B2C8 2157 #define ACP_SW3_TX_DP0_1_HCTRL_BANK1 0x00B2CC 2158 #define ACP_SW3_TX_DP0_1_HCTRL_OFFSET_BANK1 0x00B2D0 2159 #define ACP_SW3_TX_DP0_1_LANE_CTRL_BANK1 0x00B2D4 2160 #define ACP_SW3_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x00B2D8 2161 #define ACP_SW3_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B2DC 2162 #define ACP_SW3_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x00B2E0 2163 #define ACP_SW3_TX_DP0_2_HCTRL_BANK0 0x00B2E4 2164 #define ACP_SW3_TX_DP0_2_HCTRL_OFFSET_BANK0 0x00B2E8 2165 #define ACP_SW3_TX_DP0_2_LANE_CTRL_BANK0 0x00B2EC 2166 #define ACP_SW3_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x00B2F0 2167 #define ACP_SW3_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B2F4 2168 #define ACP_SW3_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x00B2F8 2169 #define ACP_SW3_TX_DP0_2_HCTRL_BANK1 0x00B2FC 2170 #define ACP_SW3_TX_DP0_2_HCTRL_OFFSET_BANK1 0x00B300 2171 #define ACP_SW3_TX_DP0_2_LANE_CTRL_BANK1 0x00B304 2172 #define ACP_SW3_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x00B308 2173 #define ACP_SW3_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B30C 2174 #define ACP_SW3_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x00B310 2175 #define ACP_SW3_TX_DP0_3_HCTRL_BANK0 0x00B314 2176 #define ACP_SW3_TX_DP0_3_HCTRL_OFFSET_BANK0 0x00B318 2177 #define ACP_SW3_TX_DP0_3_LANE_CTRL_BANK0 0x00B31C 2178 #define ACP_SW3_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x00B320 2179 #define ACP_SW3_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B324 2180 #define ACP_SW3_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x00B328 2181 #define ACP_SW3_TX_DP0_3_HCTRL_BANK1 0x00B32C 2182 #define ACP_SW3_TX_DP0_3_HCTRL_OFFSET_BANK1 0x00B330 2183 #define ACP_SW3_TX_DP0_3_LANE_CTRL_BANK1 0x00B334 2184 #define ACP_SW3_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x00B338 2185 #define ACP_SW3_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B33C 2186 #define ACP_SW3_TX_DP1_SAMPLEINTERVAL_BANK0 0x00B370 2187 #define ACP_SW3_TX_DP1_HCTRL_BANK0 0x00B374 2188 #define ACP_SW3_TX_DP1_HCTRL_OFFSET_BANK0 0x00B378 2189 #define ACP_SW3_TX_DP1_LANE_CTRL_BANK0 0x00B37C 2190 #define ACP_SW3_TX_DP1_CHANNEL_ENABLE_BANK0 0x00B380 2191 #define ACP_SW3_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B384 2192 #define ACP_SW3_TX_DP1_SAMPLEINTERVAL_BANK1 0x00B388 2193 #define ACP_SW3_TX_DP1_HCTRL_BANK1 0x00B38C 2194 #define ACP_SW3_TX_DP1_HCTRL_OFFSET_BANK1 0x00B390 2195 #define ACP_SW3_TX_DP1_LANE_CTRL_BANK1 0x00B394 2196 #define ACP_SW3_TX_DP1_CHANNEL_ENABLE_BANK1 0x00B398 2197 #define ACP_SW3_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B39C 2198 #define ACP_SW3_TX_DP2_SAMPLEINTERVAL_BANK0 0x00B3A0 2199 #define ACP_SW3_TX_DP2_HCTRL_BANK0 0x00B3A4 2200 #define ACP_SW3_TX_DP2_HCTRL_OFFSET_BANK0 0x00B3A8 2201 #define ACP_SW3_TX_DP2_LANE_CTRL_BANK0 0x00B3AC 2202 #define ACP_SW3_TX_DP2_CHANNEL_ENABLE_BANK0 0x00B3B0 2203 #define ACP_SW3_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B3B4 2204 #define ACP_SW3_TX_DP2_SAMPLEINTERVAL_BANK1 0x00B3B8 2205 #define ACP_SW3_TX_DP2_HCTRL_BANK1 0x00B3BC 2206 #define ACP_SW3_TX_DP2_HCTRL_OFFSET_BANK1 0x00B3C0 2207 #define ACP_SW3_TX_DP2_LANE_CTRL_BANK1 0x00B3C4 2208 #define ACP_SW3_TX_DP2_CHANNEL_ENABLE_BANK1 0x00B3C8 2209 #define ACP_SW3_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B3CC 2210 #define ACP_SW3_TX_DP3_SAMPLEINTERVAL_BANK0 0x00B3D0 2211 #define ACP_SW3_TX_DP3_HCTRL_BANK0 0x00B3D4 2212 #define ACP_SW3_TX_DP3_HCTRL_OFFSET_BANK0 0x00B3D8 2213 #define ACP_SW3_TX_DP3_LANE_CTRL_BANK0 0x00B3DC 2214 #define ACP_SW3_TX_DP3_CHANNEL_ENABLE_BANK0 0x00B3E0 2215 #define ACP_SW3_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B3E4 2216 #define ACP_SW3_TX_DP3_SAMPLEINTERVAL_BANK1 0x00B3E8 2217 #define ACP_SW3_TX_DP3_HCTRL_BANK1 0x00B3EC 2218 #define ACP_SW3_TX_DP3_HCTRL_OFFSET_BANK1 0x00B3F0 2219 #define ACP_SW3_TX_DP3_LANE_CTRL_BANK1 0x00B3F4 2220 #define ACP_SW3_TX_DP3_CHANNEL_ENABLE_BANK1 0x00B3F8 2221 #define ACP_SW3_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B3FC 2222 #define ACP_SW3_TX_DP4_SAMPLEINTERVAL_BANK0 0x00B400 2223 #define ACP_SW3_TX_DP4_HCTRL_BANK0 0x00B404 2224 #define ACP_SW3_TX_DP4_HCTRL_OFFSET_BANK0 0x00B408 2225 #define ACP_SW3_TX_DP4_LANE_CTRL_BANK0 0x00B40C 2226 #define ACP_SW3_TX_DP4_CHANNEL_ENABLE_BANK0 0x00B410 2227 #define ACP_SW3_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B414 2228 #define ACP_SW3_TX_DP4_SAMPLEINTERVAL_BANK1 0x00B418 2229 #define ACP_SW3_TX_DP4_HCTRL_BANK1 0x00B41C 2230 #define ACP_SW3_TX_DP4_HCTRL_OFFSET_BANK1 0x00B420 2231 #define ACP_SW3_TX_DP4_LANE_CTRL_BANK1 0x00B424 2232 #define ACP_SW3_TX_DP4_CHANNEL_ENABLE_BANK1 0x00B428 2233 #define ACP_SW3_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B42C 2234 #define ACP_SW3_TX_DP5_SAMPLEINTERVAL_BANK0 0x00B430 2235 #define ACP_SW3_TX_DP5_HCTRL_BANK0 0x00B434 2236 #define ACP_SW3_TX_DP5_HCTRL_OFFSET_BANK0 0x00B438 2237 #define ACP_SW3_TX_DP5_LANE_CTRL_BANK0 0x00B43C 2238 #define ACP_SW3_TX_DP5_CHANNEL_ENABLE_BANK0 0x00B440 2239 #define ACP_SW3_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B444 2240 #define ACP_SW3_TX_DP5_SAMPLEINTERVAL_BANK1 0x00B448 2241 #define ACP_SW3_TX_DP5_HCTRL_BANK1 0x00B44C 2242 #define ACP_SW3_TX_DP5_HCTRL_OFFSET_BANK1 0x00B450 2243 #define ACP_SW3_TX_DP5_LANE_CTRL_BANK1 0x00B454 2244 #define ACP_SW3_TX_DP5_CHANNEL_ENABLE_BANK1 0x00B458 2245 #define ACP_SW3_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B45C 2246 #define ACP_SW3_TX_DP6_SAMPLEINTERVAL_BANK0 0x00B460 2247 #define ACP_SW3_TX_DP6_HCTRL_BANK0 0x00B464 2248 #define ACP_SW3_TX_DP6_HCTRL_OFFSET_BANK0 0x00B468 2249 #define ACP_SW3_TX_DP6_LANE_CTRL_BANK0 0x00B46C 2250 #define ACP_SW3_TX_DP6_CHANNEL_ENABLE_BANK0 0x00B470 2251 #define ACP_SW3_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B474 2252 #define ACP_SW3_TX_DP6_SAMPLEINTERVAL_BANK1 0x00B478 2253 #define ACP_SW3_TX_DP6_HCTRL_BANK1 0x00B47C 2254 #define ACP_SW3_TX_DP6_HCTRL_OFFSET_BANK1 0x00B480 2255 #define ACP_SW3_TX_DP6_LANE_CTRL_BANK1 0x00B484 2256 #define ACP_SW3_TX_DP6_CHANNEL_ENABLE_BANK1 0x00B488 2257 #define ACP_SW3_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B48C 2258 #define ACP_SW3_TX_DP7_SAMPLEINTERVAL_BANK0 0x00B490 2259 #define ACP_SW3_TX_DP7_HCTRL_BANK0 0x00B494 2260 #define ACP_SW3_TX_DP7_HCTRL_OFFSET_BANK0 0x00B498 2261 #define ACP_SW3_TX_DP7_LANE_CTRL_BANK0 0x00B49C 2262 #define ACP_SW3_TX_DP7_CHANNEL_ENABLE_BANK0 0x00B4A0 2263 #define ACP_SW3_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B4A4 2264 #define ACP_SW3_TX_DP7_SAMPLEINTERVAL_BANK1 0x00B4A8 2265 #define ACP_SW3_TX_DP7_HCTRL_BANK1 0x00B4AC 2266 #define ACP_SW3_TX_DP7_HCTRL_OFFSET_BANK1 0x00B4B0 2267 #define ACP_SW3_TX_DP7_LANE_CTRL_BANK1 0x00B4B4 2268 #define ACP_SW3_TX_DP7_CHANNEL_ENABLE_BANK1 0x00B4B8 2269 #define ACP_SW3_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B4BC 2270 #define ACP_SW3_RX_STREAM0_EN 0x00B514 2271 #define ACP_SW3_RX_STREAM1_EN 0x00B518 2272 #define ACP_SW3_RX_STREAM2_EN 0x00B51C 2273 #define ACP_SW3_RX_STREAM3_EN 0x00B520 2274 #define ACP_SW3_RX_STREAM4_EN 0x00B524 2275 #define ACP_SW3_RX_STREAM5_EN 0x00B528 2276 #define ACP_SW3_RX_STREAM6_EN 0x00B52C 2277 #define ACP_SW3_RX_STREAM7_EN 0x00B530 2278 #define ACP_SW3_RX_STREAM0_EN_STATUS 0x00B534 2279 #define ACP_SW3_RX_STREAM1_EN_STATUS 0x00B538 2280 #define ACP_SW3_RX_STREAM2_EN_STATUS 0x00B53C 2281 #define ACP_SW3_RX_STREAM3_EN_STATUS 0x00B540 2282 #define ACP_SW3_RX_STREAM4_EN_STATUS 0x00B544 2283 #define ACP_SW3_RX_STREAM5_EN_STATUS 0x00B548 2284 #define ACP_SW3_RX_STREAM6_EN_STATUS 0x00B54C 2285 #define ACP_SW3_RX_STREAM7_EN_STATUS 0x00B550 2286 #define ACP_SW3_RX_DP0_FRAME_FORMAT 0x00B554 2287 #define ACP_SW3_RX_DP1_FRAME_FORMAT 0x00B558 2288 #define ACP_SW3_RX_DP2_FRAME_FORMAT 0x00B55C 2289 #define ACP_SW3_RX_DP3_FRAME_FORMAT 0x00B560 2290 #define ACP_SW3_RX_DP4_FRAME_FORMAT 0x00B564 2291 #define ACP_SW3_RX_DP5_FRAME_FORMAT 0x00B568 2292 #define ACP_SW3_RX_DP6_FRAME_FORMAT 0x00B56C 2293 #define ACP_SW3_RX_DP7_FRAME_FORMAT 0x00B570 2294 #define ACP_SW3_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x00B580 2295 #define ACP_SW3_RX_DP0_0_HCTRL_BANK0 0x00B584 2296 #define ACP_SW3_RX_DP0_0_HCTRL_OFFSET_BANK0 0x00B588 2297 #define ACP_SW3_RX_DP0_0_LANE_CTRL_BANK0 0x00B58C 2298 #define ACP_SW3_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x00B590 2299 #define ACP_SW3_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B594 2300 #define ACP_SW3_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x00B598 2301 #define ACP_SW3_RX_DP0_0_HCTRL_BANK1 0x00B59C 2302 #define ACP_SW3_RX_DP0_0_HCTRL_OFFSET_BANK1 0x00B5A0 2303 #define ACP_SW3_RX_DP0_0_LANE_CTRL_BANK1 0x00B5A4 2304 #define ACP_SW3_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x00B5A8 2305 #define ACP_SW3_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B5AC 2306 #define ACP_SW3_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x00B5B0 2307 #define ACP_SW3_RX_DP0_1_HCTRL_BANK0 0x00B5B4 2308 #define ACP_SW3_RX_DP0_1_HCTRL_OFFSET_BANK0 0x00B5B8 2309 #define ACP_SW3_RX_DP0_1_LANE_CTRL_BANK0 0x00B5BC 2310 #define ACP_SW3_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x00B5C0 2311 #define ACP_SW3_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B5C4 2312 #define ACP_SW3_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x00B5C8 2313 #define ACP_SW3_RX_DP0_1_HCTRL_BANK1 0x00B5CC 2314 #define ACP_SW3_RX_DP0_1_HCTRL_OFFSET_BANK1 0x00B5D0 2315 #define ACP_SW3_RX_DP0_1_LANE_CTRL_BANK1 0x00B5D4 2316 #define ACP_SW3_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x00B5D8 2317 #define ACP_SW3_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B5DC 2318 #define ACP_SW3_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x00B5E0 2319 #define ACP_SW3_RX_DP0_2_HCTRL_BANK0 0x00B5E4 2320 #define ACP_SW3_RX_DP0_2_HCTRL_OFFSET_BANK0 0x00B5E8 2321 #define ACP_SW3_RX_DP0_2_LANE_CTRL_BANK0 0x00B5EC 2322 #define ACP_SW3_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x00B5F0 2323 #define ACP_SW3_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B5F4 2324 #define ACP_SW3_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x00B5F8 2325 #define ACP_SW3_RX_DP0_2_HCTRL_BANK1 0x00B5FC 2326 #define ACP_SW3_RX_DP0_2_HCTRL_OFFSET_BANK1 0x00B600 2327 #define ACP_SW3_RX_DP0_2_LANE_CTRL_BANK1 0x00B604 2328 #define ACP_SW3_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x00B608 2329 #define ACP_SW3_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B60C 2330 #define ACP_SW3_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x00B610 2331 #define ACP_SW3_RX_DP0_3_HCTRL_BANK0 0x00B614 2332 #define ACP_SW3_RX_DP0_3_HCTRL_OFFSET_BANK0 0x00B618 2333 #define ACP_SW3_RX_DP0_3_LANE_CTRL_BANK0 0x00B61C 2334 #define ACP_SW3_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x00B620 2335 #define ACP_SW3_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B624 2336 #define ACP_SW3_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x00B628 2337 #define ACP_SW3_RX_DP0_3_HCTRL_BANK1 0x00B62C 2338 #define ACP_SW3_RX_DP0_3_HCTRL_OFFSET_BANK1 0x00B630 2339 #define ACP_SW3_RX_DP0_3_LANE_CTRL_BANK1 0x00B634 2340 #define ACP_SW3_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x00B638 2341 #define ACP_SW3_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B63C 2342 #define ACP_SW3_RX_DP1_SAMPLEINTERVAL_BANK0 0x00B670 2343 #define ACP_SW3_RX_DP1_HCTRL_BANK0 0x00B674 2344 #define ACP_SW3_RX_DP1_HCTRL_OFFSET_BANK0 0x00B678 2345 #define ACP_SW3_RX_DP1_LANE_CTRL_BANK0 0x00B67C 2346 #define ACP_SW3_RX_DP1_CHANNEL_ENABLE_BANK0 0x00B680 2347 #define ACP_SW3_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B684 2348 #define ACP_SW3_RX_DP1_SAMPLEINTERVAL_BANK1 0x00B688 2349 #define ACP_SW3_RX_DP1_HCTRL_BANK1 0x00B68C 2350 #define ACP_SW3_RX_DP1_HCTRL_OFFSET_BANK1 0x00B690 2351 #define ACP_SW3_RX_DP1_LANE_CTRL_BANK1 0x00B694 2352 #define ACP_SW3_RX_DP1_CHANNEL_ENABLE_BANK1 0x00B698 2353 #define ACP_SW3_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B69C 2354 #define ACP_SW3_RX_DP2_SAMPLEINTERVAL_BANK0 0x00B6A0 2355 #define ACP_SW3_RX_DP2_HCTRL_BANK0 0x00B6A4 2356 #define ACP_SW3_RX_DP2_HCTRL_OFFSET_BANK0 0x00B6A8 2357 #define ACP_SW3_RX_DP2_LANE_CTRL_BANK0 0x00B6AC 2358 #define ACP_SW3_RX_DP2_CHANNEL_ENABLE_BANK0 0x00B6B0 2359 #define ACP_SW3_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B6B4 2360 #define ACP_SW3_RX_DP2_SAMPLEINTERVAL_BANK1 0x00B6B8 2361 #define ACP_SW3_RX_DP2_HCTRL_BANK1 0x00B6BC 2362 #define ACP_SW3_RX_DP2_HCTRL_OFFSET_BANK1 0x00B6C0 2363 #define ACP_SW3_RX_DP2_LANE_CTRL_BANK1 0x00B6C4 2364 #define ACP_SW3_RX_DP2_CHANNEL_ENABLE_BANK1 0x00B6C8 2365 #define ACP_SW3_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B6CC 2366 #define ACP_SW3_RX_DP3_SAMPLEINTERVAL_BANK0 0x00B6D0 2367 #define ACP_SW3_RX_DP3_HCTRL_BANK0 0x00B6D4 2368 #define ACP_SW3_RX_DP3_HCTRL_OFFSET_BANK0 0x00B6D8 2369 #define ACP_SW3_RX_DP3_LANE_CTRL_BANK0 0x00B6DC 2370 #define ACP_SW3_RX_DP3_CHANNEL_ENABLE_BANK0 0x00B6E0 2371 #define ACP_SW3_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B6E4 2372 #define ACP_SW3_RX_DP3_SAMPLEINTERVAL_BANK1 0x00B6E8 2373 #define ACP_SW3_RX_DP3_HCTRL_BANK1 0x00B6EC 2374 #define ACP_SW3_RX_DP3_HCTRL_OFFSET_BANK1 0x00B6F0 2375 #define ACP_SW3_RX_DP3_LANE_CTRL_BANK1 0x00B6F4 2376 #define ACP_SW3_RX_DP3_CHANNEL_ENABLE_BANK1 0x00B6F8 2377 #define ACP_SW3_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B6FC 2378 #define ACP_SW3_RX_DP4_SAMPLEINTERVAL_BANK0 0x00B700 2379 #define ACP_SW3_RX_DP4_HCTRL_BANK0 0x00B704 2380 #define ACP_SW3_RX_DP4_HCTRL_OFFSET_BANK0 0x00B708 2381 #define ACP_SW3_RX_DP4_LANE_CTRL_BANK0 0x00B70C 2382 #define ACP_SW3_RX_DP4_CHANNEL_ENABLE_BANK0 0x00B710 2383 #define ACP_SW3_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B714 2384 #define ACP_SW3_RX_DP4_SAMPLEINTERVAL_BANK1 0x00B718 2385 #define ACP_SW3_RX_DP4_HCTRL_BANK1 0x00B71C 2386 #define ACP_SW3_RX_DP4_HCTRL_OFFSET_BANK1 0x00B720 2387 #define ACP_SW3_RX_DP4_LANE_CTRL_BANK1 0x00B724 2388 #define ACP_SW3_RX_DP4_CHANNEL_ENABLE_BANK1 0x00B728 2389 #define ACP_SW3_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B72C 2390 #define ACP_SW3_RX_DP5_SAMPLEINTERVAL_BANK0 0x00B730 2391 #define ACP_SW3_RX_DP5_HCTRL_BANK0 0x00B734 2392 #define ACP_SW3_RX_DP5_HCTRL_OFFSET_BANK0 0x00B738 2393 #define ACP_SW3_RX_DP5_LANE_CTRL_BANK0 0x00B73C 2394 #define ACP_SW3_RX_DP5_CHANNEL_ENABLE_BANK0 0x00B740 2395 #define ACP_SW3_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B744 2396 #define ACP_SW3_RX_DP5_SAMPLEINTERVAL_BANK1 0x00B748 2397 #define ACP_SW3_RX_DP5_HCTRL_BANK1 0x00B74C 2398 #define ACP_SW3_RX_DP5_HCTRL_OFFSET_BANK1 0x00B750 2399 #define ACP_SW3_RX_DP5_LANE_CTRL_BANK1 0x00B754 2400 #define ACP_SW3_RX_DP5_CHANNEL_ENABLE_BANK1 0x00B758 2401 #define ACP_SW3_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B75C 2402 #define ACP_SW3_RX_DP6_SAMPLEINTERVAL_BANK0 0x00B760 2403 #define ACP_SW3_RX_DP6_HCTRL_BANK0 0x00B764 2404 #define ACP_SW3_RX_DP6_HCTRL_OFFSET_BANK0 0x00B768 2405 #define ACP_SW3_RX_DP6_LANE_CTRL_BANK0 0x00B76C 2406 #define ACP_SW3_RX_DP6_CHANNEL_ENABLE_BANK0 0x00B770 2407 #define ACP_SW3_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B774 2408 #define ACP_SW3_RX_DP6_SAMPLEINTERVAL_BANK1 0x00B778 2409 #define ACP_SW3_RX_DP6_HCTRL_BANK1 0x00B77C 2410 #define ACP_SW3_RX_DP6_HCTRL_OFFSET_BANK1 0x00B780 2411 #define ACP_SW3_RX_DP6_LANE_CTRL_BANK1 0x00B784 2412 #define ACP_SW3_RX_DP6_CHANNEL_ENABLE_BANK1 0x00B788 2413 #define ACP_SW3_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B78C 2414 #define ACP_SW3_RX_DP7_SAMPLEINTERVAL_BANK0 0x00B790 2415 #define ACP_SW3_RX_DP7_HCTRL_BANK0 0x00B794 2416 #define ACP_SW3_RX_DP7_HCTRL_OFFSET_BANK0 0x00B798 2417 #define ACP_SW3_RX_DP7_LANE_CTRL_BANK0 0x00B79C 2418 #define ACP_SW3_RX_DP7_CHANNEL_ENABLE_BANK0 0x00B7A0 2419 #define ACP_SW3_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B7A4 2420 #define ACP_SW3_RX_DP7_SAMPLEINTERVAL_BANK1 0x00B7A8 2421 #define ACP_SW3_RX_DP7_HCTRL_BANK1 0x00B7AC 2422 #define ACP_SW3_RX_DP7_HCTRL_OFFSET_BANK1 0x00B7B0 2423 #define ACP_SW3_RX_DP7_LANE_CTRL_BANK1 0x00B7B4 2424 #define ACP_SW3_RX_DP7_CHANNEL_ENABLE_BANK1 0x00B7B8 2425 #define ACP_SW3_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B7BC 2426 #define ACP_SW3_BPT_PORT_EN 0x00B7C0 2427 #define ACP_SW3_BPT_PORT_EN_STATUS 0x00B7C4 2428 #define ACP_SW3_BPT_PORT_FRAME_FORMAT 0x00B7C8 2429 #define ACP_SW3_BPT_PORT_SAMPLEINTERVAL_BANK0 0x00B7CC 2430 #define ACP_SW3_BPT_PORT_HCTRL_BANK0 0x00B7D0 2431 #define ACP_SW3_BPT_PORT_OFFSET_BANK0 0x00B7D4 2432 #define ACP_SW3_BPT_PORT_LANE_SELECT_BANK0 0x00B7D8 2433 #define ACP_SW3_BPT_PORT_CHANNEL_ENABLE_BANK0 0x00B7DC 2434 #define ACP_SW3_BPT_PORT_SAMPLEINTERVAL_BANK1 0x00B7E0 2435 #define ACP_SW3_BPT_PORT_HCTRL_BANK1 0x00B7E4 2436 #define ACP_SW3_BPT_PORT_OFFSET_BANK1 0x00B7E8 2437 #define ACP_SW3_BPT_PORT_LANE_SELECT_BANK1 0x00B7EC 2438 #define ACP_SW3_BPT_PORT_CHANNEL_ENABLE_BANK1 0x00B7F0 2439 #define ACP_SW3_BPT_PORT_FIRST_BYTE_ADDR 0x00B7F4 2440 #define ACP_SW3_CLK_RESUME_CTRL 0x00B7F8 2441 #define ACP_SW3_CLK_RESUME_DELAY_CNTR 0x00B7FC 2442 #define ACP_SW3_BUS_RESET_CTRL 0x00B800 2443 #define ACP_SW3_PRBS_ERR_STATUS 0x00B804 2444 #define ACP_SW3_WALLCLK_MISC 0x00B808 2445 #define ACP_SW3_WALL_CLK_COUNTER 0x00B80C 2446 #define ACP_SW3_PING_STATUS_REGISTER_LOW 0x00B810 2447 #define ACP_SW3_PING_STATUS_REGISTER_HIGH 0x00B814 2448 #define ACP_SW3_PING_STATUS_CURRENT_BANK_SEL 0x00B818 2449 #define ACP_SW3_TZD_CHANGE 0x00B81C 2450 #define ACP_SW3_WALLCLK_INTR_CNTL 0x00B820 2451 2452 #define ACP_PDM_ENABLE 0x002C04 2453 #define ACP_PDM_DMA_ENABLE 0x002C08 2454 #define ACP_PDM_RX_RINGBUFADDR 0x002C0C 2455 #define ACP_PDM_RX_RINGBUFSIZE 0x002C10 2456 #define ACP_PDM_RX_LINKPOSITIONCNTR 0x002C14 2457 #define ACP_PDM_RX_LINEARPOSITIONCNTR_HIGH 0x002C18 2458 #define ACP_PDM_RX_LINEARPOSITIONCNTR_LOW 0x002C1C 2459 #define ACP_PDM_RX_INTR_WATERMARK_SIZE 0x002C20 2460 #define ACP_PDM_FIFO_FLUSH 0x002C24 2461 #define ACP_PDM_NO_OF_CHANNELS 0x002C28 2462 #define ACP_PDM_DECIMATION_FACTOR 0x002C2C 2463 #define ACP_PDM_VAD_CTRL 0x002C30 2464 #define ACP_PDM_WAKE 0x002C54 2465 #define ACP_PDM_BUFFER_STATUS 0x002C58 2466 #define ACP_PDM_MISC_CTRL 0x002C5C 2467 #define ACP_PDM_CLK_CTRL 0x002C60 2468 #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x002C64 2469 #define ACP_PDM_ERROR_STATUS_REGISTER 0x002C68 2470 #define ACP_PDM_CLKDIV 0x002C6C 2471 #define ACP_PDM_WALLCLK_MISC 0x002C70 2472 #define ACP_PDM_WALL_CLK_COUNTER 0x002C74 2473 #define ACP_PDM_SW_ENABLE_REG 0x002CC4 2474 #define ACP_PDM_SW_CTRLREG 0x002CC8 2475 #define ACP_PDM_WALLCLK_INTR_CNTL 0x002CCC 2476 2477 #define ACP_PDM_2_ENABLE 0x002D04 2478 #define ACP_PDM_2_DMA_ENABLE 0x002D08 2479 #define ACP_PDM_2_RX_RINGBUFADDR_96K 0x002D0C 2480 #define ACP_PDM_2_RX_RINGBUFADDR_48K 0x002D10 2481 #define ACP_PDM_2_RX_RINGBUFADDR_16K 0x002D14 2482 #define ACP_PDM_2_RX_RINGBUFSIZE_96K 0x002D18 2483 #define ACP_PDM_2_RX_RINGBUFSIZE_48K 0x002D1C 2484 #define ACP_PDM_2_RX_RINGBUFSIZE_16K 0x002D20 2485 #define ACP_PDM_2_RX_LINKPOSITIONCNTR_96K 0x002D24 2486 #define ACP_PDM_2_RX_LINKPOSITIONCNTR_48K 0x002D28 2487 #define ACP_PDM_2_RX_LINKPOSITIONCNTR_16K 0x002D2C 2488 #define ACP_PDM_2_RX_LINEARPOSITIONCNTR_HIGH_96K 0x002D30 2489 #define ACP_PDM_2_RX_LINEARPOSITIONCNTR_LOW_96K 0x002D34 2490 #define ACP_PDM_2_RX_LINEARPOSITIONCNTR_HIGH_48K 0x002D38 2491 #define ACP_PDM_2_RX_LINEARPOSITIONCNTR_LOW_48K 0x002D3C 2492 #define ACP_PDM_2_RX_LINEARPOSITIONCNTR_HIGH_16K 0x002D40 2493 #define ACP_PDM_2_RX_LINEARPOSITIONCNTR_LOW_16K 0x002D44 2494 #define ACP_PDM_2_RX_INTR_WATERMARK_SIZE_96K 0x002D48 2495 #define ACP_PDM_2_RX_INTR_WATERMARK_SIZE_48K 0x002D4C 2496 #define ACP_PDM_2_RX_INTR_WATERMARK_SIZE_16K 0x002D50 2497 #define ACP_PDM_2_FIFO_FLUSH_96K 0x002D54 2498 #define ACP_PDM_2_FIFO_FLUSH_48K 0x002D58 2499 #define ACP_PDM_2_FIFO_FLUSH_16K 0x002D5C 2500 #define ACP_PDM_2_NO_OF_CHANNELS 0x002D60 2501 #define ACP_PDM_2_DECIMATION_FACTOR 0x002D64 2502 #define ACP_PDM_2_VAD_CTRL 0x002D68 2503 #define ACP_PDM_2_WAKE 0x002D6C 2504 #define ACP_PDM_2_BUFFER_STATUS_96K 0x002D70 2505 #define ACP_PDM_2_BUFFER_STATUS_48K 0x002D74 2506 #define ACP_PDM_2_BUFFER_STATUS_16K 0x002D78 2507 #define ACP_PDM_2_MISC_CTRL 0x002D7C 2508 #define ACP_PDM_2_CLK_CTRL 0x002D80 2509 #define ACP_PDM_2_VAD_DYNAMIC_CLK_GATING_EN 0x002D84 2510 #define ACP_PDM_2_ERROR_STATUS_REGISTER 0x002D8C 2511 #define ACP_PDM_2_CLKDIV 0x002D90 2512 #define ACP_PDM_2_WALLCLK_MISC 0x002D94 2513 #define ACP_PDM_2_WALL_CLK_COUNTER 0x002D98 2514 #define ACP_PDM_2_SW_ENABLE_REG 0x002D9C 2515 #define ACP_PDM_2_SW_CTRLREG 0x002DA0 2516 #define ACP_PDM_2_WALLCLK_INTR_CNTL 0x002DA4 2517 2518 #define ACP_SCRATCH_REG_0 0x0010000 2519 #endif 2520