1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD ACP 6.3 Register Documentation 4 * 5 * Copyright 2022 Advanced Micro Devices, Inc. 6 */ 7 8 #ifndef _acp_ip_OFFSET_HEADER 9 #define _acp_ip_OFFSET_HEADER 10 11 /* Registers from ACP_DMA block */ 12 #define ACP_DMA_CNTL_0 0x0000000 13 #define ACP_DMA_CNTL_1 0x0000004 14 #define ACP_DMA_CNTL_2 0x0000008 15 #define ACP_DMA_CNTL_3 0x000000C 16 #define ACP_DMA_CNTL_4 0x0000010 17 #define ACP_DMA_CNTL_5 0x0000014 18 #define ACP_DMA_CNTL_6 0x0000018 19 #define ACP_DMA_CNTL_7 0x000001C 20 #define ACP_DMA_DSCR_STRT_IDX_0 0x0000020 21 #define ACP_DMA_DSCR_STRT_IDX_1 0x0000024 22 #define ACP_DMA_DSCR_STRT_IDX_2 0x0000028 23 #define ACP_DMA_DSCR_STRT_IDX_3 0x000002C 24 #define ACP_DMA_DSCR_STRT_IDX_4 0x0000030 25 #define ACP_DMA_DSCR_STRT_IDX_5 0x0000034 26 #define ACP_DMA_DSCR_STRT_IDX_6 0x0000038 27 #define ACP_DMA_DSCR_STRT_IDX_7 0x000003C 28 #define ACP_DMA_DSCR_CNT_0 0x0000040 29 #define ACP_DMA_DSCR_CNT_1 0x0000044 30 #define ACP_DMA_DSCR_CNT_2 0x0000048 31 #define ACP_DMA_DSCR_CNT_3 0x000004C 32 #define ACP_DMA_DSCR_CNT_4 0x0000050 33 #define ACP_DMA_DSCR_CNT_5 0x0000054 34 #define ACP_DMA_DSCR_CNT_6 0x0000058 35 #define ACP_DMA_DSCR_CNT_7 0x000005C 36 #define ACP_DMA_PRIO_0 0x0000060 37 #define ACP_DMA_PRIO_1 0x0000064 38 #define ACP_DMA_PRIO_2 0x0000068 39 #define ACP_DMA_PRIO_3 0x000006C 40 #define ACP_DMA_PRIO_4 0x0000070 41 #define ACP_DMA_PRIO_5 0x0000074 42 #define ACP_DMA_PRIO_6 0x0000078 43 #define ACP_DMA_PRIO_7 0x000007C 44 #define ACP_DMA_CUR_DSCR_0 0x0000080 45 #define ACP_DMA_CUR_DSCR_1 0x0000084 46 #define ACP_DMA_CUR_DSCR_2 0x0000088 47 #define ACP_DMA_CUR_DSCR_3 0x000008C 48 #define ACP_DMA_CUR_DSCR_4 0x0000090 49 #define ACP_DMA_CUR_DSCR_5 0x0000094 50 #define ACP_DMA_CUR_DSCR_6 0x0000098 51 #define ACP_DMA_CUR_DSCR_7 0x000009C 52 #define ACP_DMA_CUR_TRANS_CNT_0 0x00000A0 53 #define ACP_DMA_CUR_TRANS_CNT_1 0x00000A4 54 #define ACP_DMA_CUR_TRANS_CNT_2 0x00000A8 55 #define ACP_DMA_CUR_TRANS_CNT_3 0x00000AC 56 #define ACP_DMA_CUR_TRANS_CNT_4 0x00000B0 57 #define ACP_DMA_CUR_TRANS_CNT_5 0x00000B4 58 #define ACP_DMA_CUR_TRANS_CNT_6 0x00000B8 59 #define ACP_DMA_CUR_TRANS_CNT_7 0x00000BC 60 #define ACP_DMA_ERR_STS_0 0x00000C0 61 #define ACP_DMA_ERR_STS_1 0x00000C4 62 #define ACP_DMA_ERR_STS_2 0x00000C8 63 #define ACP_DMA_ERR_STS_3 0x00000CC 64 #define ACP_DMA_ERR_STS_4 0x00000D0 65 #define ACP_DMA_ERR_STS_5 0x00000D4 66 #define ACP_DMA_ERR_STS_6 0x00000D8 67 #define ACP_DMA_ERR_STS_7 0x00000DC 68 #define ACP_DMA_DESC_BASE_ADDR 0x00000E0 69 #define ACP_DMA_DESC_MAX_NUM_DSCR 0x00000E4 70 #define ACP_DMA_CH_STS 0x00000E8 71 #define ACP_DMA_CH_GROUP 0x00000EC 72 #define ACP_DMA_CH_RST_STS 0x00000F0 73 74 /* Registers from ACP_AXI2AXIATU block */ 75 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x0000C00 76 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x0000C04 77 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x0000C08 78 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x0000C0C 79 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x0000C10 80 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x0000C14 81 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x0000C18 82 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x0000C1C 83 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x0000C20 84 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x0000C24 85 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x0000C28 86 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x0000C2C 87 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x0000C30 88 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x0000C34 89 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x0000C38 90 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x0000C3C 91 #define ACPAXI2AXI_ATU_CTRL 0x0000C40 92 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x0000C44 93 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x0000C48 94 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x0000C4C 95 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x0000C50 96 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x0000C54 97 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x0000C58 98 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x0000C5C 99 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x0000C60 100 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x0000C64 101 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x0000C68 102 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x0000C6C 103 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x0000C70 104 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x0000C74 105 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x0000C78 106 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x0000C7C 107 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x0000C80 108 109 /* Registers from ACP_CLKRST block */ 110 #define ACP_SOFT_RESET 0x0001000 111 #define ACP_CONTROL 0x0001004 112 #define ACP_STATUS 0x0001008 113 #define ACP_DYNAMIC_CG_MASTER_CONTROL 0x0001010 114 #define ACP_ZSC_DSP_CTRL 0x0001014 115 #define ACP_ZSC_STS 0x0001018 116 #define ACP_PGFSM_CONTROL 0x0001024 117 #define ACP_PGFSM_STATUS 0x0001028 118 #define ACP_CLKMUX_SEL 0x000102C 119 120 /* Registers from ACP_AON block */ 121 #define ACP_PME_EN 0x0001400 122 #define ACP_DEVICE_STATE 0x0001404 123 #define AZ_DEVICE_STATE 0x0001408 124 #define ACP_PIN_CONFIG 0x0001440 125 #define ACP_PAD_PULLUP_CTRL 0x0001444 126 #define ACP_PAD_PULLDOWN_CTRL 0x0001448 127 #define ACP_PAD_DRIVE_STRENGTH_CTRL 0x000144C 128 #define ACP_PAD_SCHMEN_CTRL 0x0001450 129 #define ACP_SW_PAD_KEEPER_EN 0x0001454 130 #define ACP_SW_WAKE_EN 0x0001458 131 #define ACP_I2S_WAKE_EN 0x000145C 132 #define ACP_SW1_WAKE_EN 0x0001460 133 134 #define ACP_SW_I2S_ERROR_REASON 0x00018B4 135 #define ACP_SW_POS_TRACK_I2S_TX_CTRL 0x00018B8 136 #define ACP_SW_I2S_TX_DMA_POS 0x00018BC 137 #define ACP_SW_POS_TRACK_BT_TX_CTRL 0x00018C0 138 #define ACP_SW_BT_TX_DMA_POS 0x00018C4 139 #define ACP_SW_POS_TRACK_HS_TX_CTRL 0x00018C8 140 #define ACP_SW_HS_TX_DMA_POS 0x00018CC 141 #define ACP_SW_POS_TRACK_I2S_RX_CTRL 0x00018D0 142 #define ACP_SW_I2S_RX_DMA_POS 0x00018D4 143 #define ACP_SW_POS_TRACK_BT_RX_CTRL 0x00018D8 144 #define ACP_SW_BT_RX_DMA_POS 0x00018DC 145 #define ACP_SW_POS_TRACK_HS_RX_CTRL 0x00018E0 146 #define ACP_SW_HS_RX_DMA_POS 0x00018E4 147 #define ACP_ERROR_INTR_MASK1 0X0001974 148 #define ACP_ERROR_INTR_MASK2 0X0001978 149 #define ACP_ERROR_INTR_MASK3 0X000197C 150 151 /* Registers from ACP_P1_MISC block */ 152 #define ACP_EXTERNAL_INTR_ENB 0x0001A00 153 #define ACP_EXTERNAL_INTR_CNTL 0x0001A04 154 #define ACP_EXTERNAL_INTR_CNTL1 0x0001A08 155 #define ACP_EXTERNAL_INTR_STAT 0x0001A0C 156 #define ACP_EXTERNAL_INTR_STAT1 0x0001A10 157 #define ACP_ERROR_STATUS 0x0001A4C 158 #define ACP_P1_SW_I2S_ERROR_REASON 0x0001A50 159 #define ACP_P1_SW_POS_TRACK_I2S_TX_CTRL 0x0001A6C 160 #define ACP_P1_SW_I2S_TX_DMA_POS 0x0001A70 161 #define ACP_P1_SW_POS_TRACK_I2S_RX_CTRL 0x0001A74 162 #define ACP_P1_SW_I2S_RX_DMA_POS 0x0001A78 163 #define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x0001A7C 164 #define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x0001A80 165 #define ACP_SCRATCH_REG_BASE_ADDR 0x0001A84 166 #define ACP_P1_SW_POS_TRACK_BT_TX_CTRL 0x0001A88 167 #define ACP_P1_SW_BT_TX_DMA_POS 0x0001A8C 168 #define ACP_P1_SW_POS_TRACK_HS_TX_CTRL 0x0001A90 169 #define ACP_P1_SW_HS_TX_DMA_POS 0x0001A94 170 #define ACP_P1_SW_POS_TRACK_BT_RX_CTRL 0x0001A98 171 #define ACP_P1_SW_BT_RX_DMA_POS 0x0001A9C 172 #define ACP_P1_SW_POS_TRACK_HS_RX_CTRL 0x0001AA0 173 #define ACP_P1_SW_HS_RX_DMA_POS 0x0001AA4 174 #define ACP_ERROR_INTR_MASK4 0X0001AEC 175 #define ACP_ERROR_INTR_MASK5 0X0001AF0 176 177 /* Registers from ACP_AUDIO_BUFFERS block */ 178 #define ACP_I2S_RX_RINGBUFADDR 0x0002000 179 #define ACP_I2S_RX_RINGBUFSIZE 0x0002004 180 #define ACP_I2S_RX_LINKPOSITIONCNTR 0x0002008 181 #define ACP_I2S_RX_FIFOADDR 0x000200C 182 #define ACP_I2S_RX_FIFOSIZE 0x0002010 183 #define ACP_I2S_RX_DMA_SIZE 0x0002014 184 #define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0002018 185 #define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x000201C 186 #define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x0002020 187 #define ACP_I2S_TX_RINGBUFADDR 0x0002024 188 #define ACP_I2S_TX_RINGBUFSIZE 0x0002028 189 #define ACP_I2S_TX_LINKPOSITIONCNTR 0x000202C 190 #define ACP_I2S_TX_FIFOADDR 0x0002030 191 #define ACP_I2S_TX_FIFOSIZE 0x0002034 192 #define ACP_I2S_TX_DMA_SIZE 0x0002038 193 #define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x000203C 194 #define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0002040 195 #define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x0002044 196 #define ACP_BT_RX_RINGBUFADDR 0x0002048 197 #define ACP_BT_RX_RINGBUFSIZE 0x000204C 198 #define ACP_BT_RX_LINKPOSITIONCNTR 0x0002050 199 #define ACP_BT_RX_FIFOADDR 0x0002054 200 #define ACP_BT_RX_FIFOSIZE 0x0002058 201 #define ACP_BT_RX_DMA_SIZE 0x000205C 202 #define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0002060 203 #define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x0002064 204 #define ACP_BT_RX_INTR_WATERMARK_SIZE 0x0002068 205 #define ACP_BT_TX_RINGBUFADDR 0x000206C 206 #define ACP_BT_TX_RINGBUFSIZE 0x0002070 207 #define ACP_BT_TX_LINKPOSITIONCNTR 0x0002074 208 #define ACP_BT_TX_FIFOADDR 0x0002078 209 #define ACP_BT_TX_FIFOSIZE 0x000207C 210 #define ACP_BT_TX_DMA_SIZE 0x0002080 211 #define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0002084 212 #define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x0002088 213 #define ACP_BT_TX_INTR_WATERMARK_SIZE 0x000208C 214 #define ACP_HS_RX_RINGBUFADDR 0x0002090 215 #define ACP_HS_RX_RINGBUFSIZE 0x0002094 216 #define ACP_HS_RX_LINKPOSITIONCNTR 0x0002098 217 #define ACP_HS_RX_FIFOADDR 0x000209C 218 #define ACP_HS_RX_FIFOSIZE 0x00020A0 219 #define ACP_HS_RX_DMA_SIZE 0x00020A4 220 #define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8 221 #define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x00020AC 222 #define ACP_HS_RX_INTR_WATERMARK_SIZE 0x00020B0 223 #define ACP_HS_TX_RINGBUFADDR 0x00020B4 224 #define ACP_HS_TX_RINGBUFSIZE 0x00020B8 225 #define ACP_HS_TX_LINKPOSITIONCNTR 0x00020BC 226 #define ACP_HS_TX_FIFOADDR 0x00020C0 227 #define ACP_HS_TX_FIFOSIZE 0x00020C4 228 #define ACP_HS_TX_DMA_SIZE 0x00020C8 229 #define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC 230 #define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x00020D0 231 #define ACP_HS_TX_INTR_WATERMARK_SIZE 0x00020D4 232 #define ACP_AUDIO_RX_RINGBUFADDR ACP_I2S_RX_RINGBUFADDR 233 #define ACP_AUDIO_RX_RINGBUFSIZE ACP_I2S_RX_RINGBUFSIZE 234 #define ACP_AUDIO_RX_LINKPOSITIONCNTR ACP_I2S_RX_LINKPOSITIONCNTR 235 #define ACP_AUDIO_RX_FIFOADDR ACP_I2S_RX_FIFOADDR 236 #define ACP_AUDIO_RX_FIFOSIZE ACP_I2S_RX_FIFOSIZE 237 #define ACP_AUDIO_RX_DMA_SIZE ACP_I2S_RX_DMA_SIZE 238 #define ACP_AUDIO_RX_LINEARPOSITIONCNTR_HIGH ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 239 #define ACP_AUDIO_RX_LINEARPOSITIONCNTR_LOW ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 240 #define ACP_AUDIO_RX_INTR_WATERMARK_SIZE ACP_I2S_RX_INTR_WATERMARK_SIZE 241 #define ACP_AUDIO_TX_RINGBUFADDR ACP_I2S_TX_RINGBUFADDR 242 #define ACP_AUDIO_TX_RINGBUFSIZE ACP_I2S_TX_RINGBUFSIZE 243 #define ACP_AUDIO_TX_LINKPOSITIONCNTR ACP_I2S_TX_LINKPOSITIONCNTR 244 #define ACP_AUDIO_TX_FIFOADDR ACP_I2S_TX_FIFOADDR 245 #define ACP_AUDIO_TX_FIFOSIZE ACP_I2S_TX_FIFOSIZE 246 #define ACP_AUDIO_TX_DMA_SIZE ACP_I2S_TX_DMA_SIZE 247 #define ACP_AUDIO_TX_LINEARPOSITIONCNTR_HIGH ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 248 #define ACP_AUDIO_TX_LINEARPOSITIONCNTR_LOW ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 249 #define ACP_AUDIO_TX_INTR_WATERMARK_SIZE ACP_I2S_TX_INTR_WATERMARK_SIZE 250 251 /* Registers from ACP_I2S_TDM block */ 252 #define ACP_I2STDM_IER 0x0002400 253 #define ACP_I2STDM_IRER 0x0002404 254 #define ACP_I2STDM_RXFRMT 0x0002408 255 #define ACP_I2STDM_ITER 0x000240C 256 #define ACP_I2STDM_TXFRMT 0x0002410 257 #define ACP_I2STDM0_MSTRCLKGEN 0x0002414 258 #define ACP_I2STDM1_MSTRCLKGEN 0x0002418 259 #define ACP_I2STDM2_MSTRCLKGEN 0x000241C 260 #define ACP_I2STDM_REFCLKGEN 0x0002420 261 262 /* Registers from ACP_BT_TDM block */ 263 #define ACP_BTTDM_IER 0x0002800 264 #define ACP_BTTDM_IRER 0x0002804 265 #define ACP_BTTDM_RXFRMT 0x0002808 266 #define ACP_BTTDM_ITER 0x000280C 267 #define ACP_BTTDM_TXFRMT 0x0002810 268 #define ACP_HSTDM_IER 0x0002814 269 #define ACP_HSTDM_IRER 0x0002818 270 #define ACP_HSTDM_RXFRMT 0x000281C 271 #define ACP_HSTDM_ITER 0x0002820 272 #define ACP_HSTDM_TXFRMT 0x0002824 273 274 /* Registers from ACP_WOV block */ 275 #define ACP_WOV_PDM_ENABLE 0x0002C04 276 #define ACP_WOV_PDM_DMA_ENABLE 0x0002C08 277 #define ACP_WOV_RX_RINGBUFADDR 0x0002C0C 278 #define ACP_WOV_RX_RINGBUFSIZE 0x0002C10 279 #define ACP_WOV_RX_LINKPOSITIONCNTR 0x0002C14 280 #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x0002C18 281 #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x0002C1C 282 #define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x0002C20 283 #define ACP_WOV_PDM_FIFO_FLUSH 0x0002C24 284 #define ACP_WOV_PDM_NO_OF_CHANNELS 0x0002C28 285 #define ACP_WOV_PDM_DECIMATION_FACTOR 0x0002C2C 286 #define ACP_WOV_PDM_VAD_CTRL 0x0002C30 287 #define ACP_WOV_WAKE 0x0002C54 288 #define ACP_WOV_BUFFER_STATUS 0x0002C58 289 #define ACP_WOV_MISC_CTRL 0x0002C5C 290 #define ACP_WOV_CLK_CTRL 0x0002C60 291 #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x0002C64 292 #define ACP_WOV_ERROR_STATUS_REGISTER 0x0002C68 293 #define ACP_PDM_CLKDIV 0x0002C6C 294 295 /* Registers from ACP_SW_SWCLK block */ 296 #define ACP_SW_EN 0x0003000 297 #define ACP_SW_EN_STATUS 0x0003004 298 #define ACP_SW_FRAMESIZE 0x0003008 299 #define ACP_SW_SSP_COUNTER 0x000300C 300 #define ACP_SW_AUDIO_TX_EN 0x0003010 301 #define ACP_SW_AUDIO_TX_EN_STATUS 0x0003014 302 #define ACP_SW_AUDIO_TX_FRAME_FORMAT 0x0003018 303 #define ACP_SW_AUDIO_TX_SAMPLEINTERVAL 0x000301C 304 #define ACP_SW_AUDIO_TX_HCTRL_DP0 0x0003020 305 #define ACP_SW_AUDIO_TX_HCTRL_DP1 0x0003024 306 #define ACP_SW_AUDIO_TX_HCTRL_DP2 0x0003028 307 #define ACP_SW_AUDIO_TX_HCTRL_DP3 0x000302C 308 #define ACP_SW_AUDIO_TX_OFFSET_DP0 0x0003030 309 #define ACP_SW_AUDIO_TX_OFFSET_DP1 0x0003034 310 #define ACP_SW_AUDIO_TX_OFFSET_DP2 0x0003038 311 #define ACP_SW_AUDIO_TX_OFFSET_DP3 0x000303C 312 #define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP0 0x0003040 313 #define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP1 0x0003044 314 #define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP2 0x0003048 315 #define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP3 0x000304C 316 #define ACP_SW_BT_TX_EN 0x0003050 317 #define ACP_SW_BT_TX_EN_STATUS 0x0003054 318 #define ACP_SW_BT_TX_FRAME_FORMAT 0x0003058 319 #define ACP_SW_BT_TX_SAMPLEINTERVAL 0x000305C 320 #define ACP_SW_BT_TX_HCTRL 0x0003060 321 #define ACP_SW_BT_TX_OFFSET 0x0003064 322 #define ACP_SW_BT_TX_CHANNEL_ENABLE_DP0 0x0003068 323 #define ACP_SW_HEADSET_TX_EN 0x000306C 324 #define ACP_SW_HEADSET_TX_EN_STATUS 0x0003070 325 #define ACP_SW_HEADSET_TX_FRAME_FORMAT 0x0003074 326 #define ACP_SW_HEADSET_TX_SAMPLEINTERVAL 0x0003078 327 #define ACP_SW_HEADSET_TX_HCTRL 0x000307C 328 #define ACP_SW_HEADSET_TX_OFFSET 0x0003080 329 #define ACP_SW_HEADSET_TX_CHANNEL_ENABLE_DP0 0x0003084 330 #define ACP_SW_AUDIO_RX_EN 0x0003088 331 #define ACP_SW_AUDIO_RX_EN_STATUS 0x000308C 332 #define ACP_SW_AUDIO_RX_FRAME_FORMAT 0x0003090 333 #define ACP_SW_AUDIO_RX_SAMPLEINTERVAL 0x0003094 334 #define ACP_SW_AUDIO_RX_HCTRL_DP0 0x0003098 335 #define ACP_SW_AUDIO_RX_HCTRL_DP1 0x000309C 336 #define ACP_SW_AUDIO_RX_HCTRL_DP2 0x0003100 337 #define ACP_SW_AUDIO_RX_HCTRL_DP3 0x0003104 338 #define ACP_SW_AUDIO_RX_OFFSET_DP0 0x0003108 339 #define ACP_SW_AUDIO_RX_OFFSET_DP1 0x000310C 340 #define ACP_SW_AUDIO_RX_OFFSET_DP2 0x0003110 341 #define ACP_SW_AUDIO_RX_OFFSET_DP3 0x0003114 342 #define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP0 0x0003118 343 #define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP1 0x000311C 344 #define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP2 0x0003120 345 #define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP3 0x0003124 346 #define ACP_SW_BT_RX_EN 0x0003128 347 #define ACP_SW_BT_RX_EN_STATUS 0x000312C 348 #define ACP_SW_BT_RX_FRAME_FORMAT 0x0003130 349 #define ACP_SW_BT_RX_SAMPLEINTERVAL 0x0003134 350 #define ACP_SW_BT_RX_HCTRL 0x0003138 351 #define ACP_SW_BT_RX_OFFSET 0x000313C 352 #define ACP_SW_BT_RX_CHANNEL_ENABLE_DP0 0x0003140 353 #define ACP_SW_HEADSET_RX_EN 0x0003144 354 #define ACP_SW_HEADSET_RX_EN_STATUS 0x0003148 355 #define ACP_SW_HEADSET_RX_FRAME_FORMAT 0x000314C 356 #define ACP_SW_HEADSET_RX_SAMPLEINTERVAL 0x0003150 357 #define ACP_SW_HEADSET_RX_HCTRL 0x0003154 358 #define ACP_SW_HEADSET_RX_OFFSET 0x0003158 359 #define ACP_SW_HEADSET_RX_CHANNEL_ENABLE_DP0 0x000315C 360 #define ACP_SW_BPT_PORT_EN 0x0003160 361 #define ACP_SW_BPT_PORT_EN_STATUS 0x0003164 362 #define ACP_SW_BPT_PORT_FRAME_FORMAT 0x0003168 363 #define ACP_SW_BPT_PORT_SAMPLEINTERVAL 0x000316C 364 #define ACP_SW_BPT_PORT_HCTRL 0x0003170 365 #define ACP_SW_BPT_PORT_OFFSET 0x0003174 366 #define ACP_SW_BPT_PORT_CHANNEL_ENABLE 0x0003178 367 #define ACP_SW_BPT_PORT_FIRST_BYTE_ADDR 0x000317C 368 #define ACP_SW_CLK_RESUME_CTRL 0x0003180 369 #define ACP_SW_CLK_RESUME_DELAY_CNTR 0x0003184 370 #define ACP_SW_BUS_RESET_CTRL 0x0003188 371 #define ACP_SW_PRBS_ERR_STATUS 0x000318C 372 #define SW_IMM_CMD_UPPER_WORD 0x0003230 373 #define SW_IMM_CMD_LOWER_QWORD 0x0003234 374 #define SW_IMM_RESP_UPPER_WORD 0x0003238 375 #define SW_IMM_RESP_LOWER_QWORD 0x000323C 376 #define SW_IMM_CMD_STS 0x0003240 377 #define SW_BRA_BASE_ADDRESS 0x0003244 378 #define SW_BRA_TRANSFER_SIZE 0x0003248 379 #define SW_BRA_DMA_BUSY 0x000324C 380 #define SW_BRA_RESP 0x0003250 381 #define SW_BRA_RESP_FRAME_ADDR 0x0003254 382 #define SW_BRA_CURRENT_TRANSFER_SIZE 0x0003258 383 #define SW_STATE_CHANGE_STATUS_0TO7 0x000325C 384 #define SW_STATE_CHANGE_STATUS_8TO11 0x0003260 385 #define SW_STATE_CHANGE_STATUS_MASK_0TO7 0x0003264 386 #define SW_STATE_CHANGE_STATUS_MASK_8TO11 0x0003268 387 #define SW_CLK_FREQUENCY_CTRL 0x000326C 388 #define SW_ERROR_INTR_MASK 0x0003270 389 #define SW_PHY_TEST_MODE_DATA_OFF 0x0003274 390 391 /* Registers from ACP_P1_AUDIO_BUFFERS block */ 392 #define ACP_P1_I2S_RX_RINGBUFADDR 0x0003A00 393 #define ACP_P1_I2S_RX_RINGBUFSIZE 0x0003A04 394 #define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x0003A08 395 #define ACP_P1_I2S_RX_FIFOADDR 0x0003A0C 396 #define ACP_P1_I2S_RX_FIFOSIZE 0x0003A10 397 #define ACP_P1_I2S_RX_DMA_SIZE 0x0003A14 398 #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18 399 #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C 400 #define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x0003A20 401 #define ACP_P1_I2S_TX_RINGBUFADDR 0x0003A24 402 #define ACP_P1_I2S_TX_RINGBUFSIZE 0x0003A28 403 #define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x0003A2C 404 #define ACP_P1_I2S_TX_FIFOADDR 0x0003A30 405 #define ACP_P1_I2S_TX_FIFOSIZE 0x0003A34 406 #define ACP_P1_I2S_TX_DMA_SIZE 0x0003A38 407 #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C 408 #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0003A40 409 #define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x0003A44 410 #define ACP_P1_BT_RX_RINGBUFADDR 0x0003A48 411 #define ACP_P1_BT_RX_RINGBUFSIZE 0x0003A4C 412 #define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x0003A50 413 #define ACP_P1_BT_RX_FIFOADDR 0x0003A54 414 #define ACP_P1_BT_RX_FIFOSIZE 0x0003A58 415 #define ACP_P1_BT_RX_DMA_SIZE 0x0003A5C 416 #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60 417 #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x0003A64 418 #define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x0003A68 419 #define ACP_P1_BT_TX_RINGBUFADDR 0x0003A6C 420 #define ACP_P1_BT_TX_RINGBUFSIZE 0x0003A70 421 #define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x0003A74 422 #define ACP_P1_BT_TX_FIFOADDR 0x0003A78 423 #define ACP_P1_BT_TX_FIFOSIZE 0x0003A7C 424 #define ACP_P1_BT_TX_DMA_SIZE 0x0003A80 425 #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84 426 #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x0003A88 427 #define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x0003A8C 428 #define ACP_P1_HS_RX_RINGBUFADDR 0x0003A90 429 #define ACP_P1_HS_RX_RINGBUFSIZE 0x0003A94 430 #define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x0003A98 431 #define ACP_P1_HS_RX_FIFOADDR 0x0003A9C 432 #define ACP_P1_HS_RX_FIFOSIZE 0x0003AA0 433 #define ACP_P1_HS_RX_DMA_SIZE 0x0003AA4 434 #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8 435 #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC 436 #define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x0003AB0 437 #define ACP_P1_HS_TX_RINGBUFADDR 0x0003AB4 438 #define ACP_P1_HS_TX_RINGBUFSIZE 0x0003AB8 439 #define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x0003ABC 440 #define ACP_P1_HS_TX_FIFOADDR 0x0003AC0 441 #define ACP_P1_HS_TX_FIFOSIZE 0x0003AC4 442 #define ACP_P1_HS_TX_DMA_SIZE 0x0003AC8 443 #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC 444 #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0 445 #define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x0003AD4 446 #define ACP_P1_AUDIO_RX_RINGBUFADDR ACP_P1_I2S_RX_RINGBUFADDR 447 #define ACP_P1_AUDIO_RX_RINGBUFSIZE ACP_P1_I2S_RX_RINGBUFSIZE 448 #define ACP_P1_AUDIO_RX_LINKPOSITIONCNTR ACP_P1_I2S_RX_LINKPOSITIONCNTR 449 #define ACP_P1_AUDIO_RX_FIFOADDR ACP_P1_I2S_RX_FIFOADDR 450 #define ACP_P1_AUDIO_RX_FIFOSIZE ACP_P1_I2S_RX_FIFOSIZE 451 #define ACP_P1_AUDIO_RX_DMA_SIZE ACP_P1_I2S_RX_DMA_SIZE 452 #define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_HIGH ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 453 #define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_LOW ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 454 #define ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 455 #define ACP_P1_AUDIO_TX_RINGBUFADDR ACP_P1_I2S_TX_RINGBUFADDR 456 #define ACP_P1_AUDIO_TX_RINGBUFSIZE ACP_P1_I2S_TX_RINGBUFSIZE 457 #define ACP_P1_AUDIO_TX_LINKPOSITIONCNTR ACP_P1_I2S_TX_LINKPOSITIONCNTR 458 #define ACP_P1_AUDIO_TX_FIFOADDR ACP_P1_I2S_TX_FIFOADDR 459 #define ACP_P1_AUDIO_TX_FIFOSIZE ACP_P1_I2S_TX_FIFOSIZE 460 #define ACP_P1_AUDIO_TX_DMA_SIZE ACP_P1_I2S_TX_DMA_SIZE 461 #define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_HIGH ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 462 #define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_LOW ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 463 #define ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 464 465 /* Registers from ACP_P1_SW_SWCLK block */ 466 #define ACP_P1_SW_EN 0x0003C00 467 #define ACP_P1_SW_EN_STATUS 0x0003C04 468 #define ACP_P1_SW_FRAMESIZE 0x0003C08 469 #define ACP_P1_SW_SSP_COUNTER 0x0003C0C 470 #define ACP_P1_SW_BT_TX_EN 0x0003C50 471 #define ACP_P1_SW_BT_TX_EN_STATUS 0x0003C54 472 #define ACP_P1_SW_BT_TX_FRAME_FORMAT 0x0003C58 473 #define ACP_P1_SW_BT_TX_SAMPLEINTERVAL 0x0003C5C 474 #define ACP_P1_SW_BT_TX_HCTRL 0x0003C60 475 #define ACP_P1_SW_BT_TX_OFFSET 0x0003C64 476 #define ACP_P1_SW_BT_TX_CHANNEL_ENABLE_DP0 0x0003C68 477 #define ACP_P1_SW_BT_RX_EN 0x0003D28 478 #define ACP_P1_SW_BT_RX_EN_STATUS 0x0003D2C 479 #define ACP_P1_SW_BT_RX_FRAME_FORMAT 0x0003D30 480 #define ACP_P1_SW_BT_RX_SAMPLEINTERVAL 0x0003D34 481 #define ACP_P1_SW_BT_RX_HCTRL 0x0003D38 482 #define ACP_P1_SW_BT_RX_OFFSET 0x0003D3C 483 #define ACP_P1_SW_BT_RX_CHANNEL_ENABLE_DP0 0x0003D40 484 #define ACP_P1_SW_BPT_PORT_EN 0x0003D60 485 #define ACP_P1_SW_BPT_PORT_EN_STATUS 0x0003D64 486 #define ACP_P1_SW_BPT_PORT_FRAME_FORMAT 0x0003D68 487 #define ACP_P1_SW_BPT_PORT_SAMPLEINTERVAL 0x0003D6C 488 #define ACP_P1_SW_BPT_PORT_HCTRL 0x0003D70 489 #define ACP_P1_SW_BPT_PORT_OFFSET 0x0003D74 490 #define ACP_P1_SW_BPT_PORT_CHANNEL_ENABLE 0x0003D78 491 #define ACP_P1_SW_BPT_PORT_FIRST_BYTE_ADDR 0x0003D7C 492 #define ACP_P1_SW_CLK_RESUME_CTRL 0x0003D80 493 #define ACP_P1_SW_CLK_RESUME_DELAY_CNTR 0x0003D84 494 #define ACP_P1_SW_BUS_RESET_CTRL 0x0003D88 495 #define ACP_P1_SW_PRBS_ERR_STATUS 0x0003D8C 496 497 /* Registers from ACP_P1_SW_ACLK block */ 498 #define P1_SW_CORB_BASE_ADDRESS 0x0003E00 499 #define P1_SW_CORB_WRITE_POINTER 0x0003E04 500 #define P1_SW_CORB_READ_POINTER 0x0003E08 501 #define P1_SW_CORB_CONTROL 0x0003E0C 502 #define P1_SW_CORB_SIZE 0x0003E14 503 #define P1_SW_RIRB_BASE_ADDRESS 0x0003E18 504 #define P1_SW_RIRB_WRITE_POINTER 0x0003E1C 505 #define P1_SW_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003E20 506 #define P1_SW_RIRB_CONTROL 0x0003E24 507 #define P1_SW_RIRB_SIZE 0x0003E28 508 #define P1_SW_RIRB_FIFO_MIN_THDL 0x0003E2C 509 #define P1_SW_IMM_CMD_UPPER_WORD 0x0003E30 510 #define P1_SW_IMM_CMD_LOWER_QWORD 0x0003E34 511 #define P1_SW_IMM_RESP_UPPER_WORD 0x0003E38 512 #define P1_SW_IMM_RESP_LOWER_QWORD 0x0003E3C 513 #define P1_SW_IMM_CMD_STS 0x0003E40 514 #define P1_SW_BRA_BASE_ADDRESS 0x0003E44 515 #define P1_SW_BRA_TRANSFER_SIZE 0x0003E48 516 #define P1_SW_BRA_DMA_BUSY 0x0003E4C 517 #define P1_SW_BRA_RESP 0x0003E50 518 #define P1_SW_BRA_RESP_FRAME_ADDR 0x0003E54 519 #define P1_SW_BRA_CURRENT_TRANSFER_SIZE 0x0003E58 520 #define P1_SW_STATE_CHANGE_STATUS_0TO7 0x0003E5C 521 #define P1_SW_STATE_CHANGE_STATUS_8TO11 0x0003E60 522 #define P1_SW_STATE_CHANGE_STATUS_MASK_0TO7 0x0003E64 523 #define P1_SW_STATE_CHANGE_STATUS_MASK_8TO11 0x0003E68 524 #define P1_SW_CLK_FREQUENCY_CTRL 0x0003E6C 525 #define P1_SW_ERROR_INTR_MASK 0x0003E70 526 #define P1_SW_PHY_TEST_MODE_DATA_OFF 0x0003E74 527 528 /* Registers from ACP_SCRATCH block */ 529 #define ACP_SCRATCH_REG_0 0x0010000 530 #define ACP_SCRATCH_REG_1 0x0010004 531 #define ACP_SCRATCH_REG_2 0x0010008 532 #define ACP_SCRATCH_REG_3 0x001000C 533 #define ACP_SCRATCH_REG_4 0x0010010 534 #define ACP_SCRATCH_REG_5 0x0010014 535 #define ACP_SCRATCH_REG_6 0x0010018 536 #define ACP_SCRATCH_REG_7 0x001001C 537 #define ACP_SCRATCH_REG_8 0x0010020 538 #define ACP_SCRATCH_REG_9 0x0010024 539 #define ACP_SCRATCH_REG_10 0x0010028 540 #define ACP_SCRATCH_REG_11 0x001002C 541 #define ACP_SCRATCH_REG_12 0x0010030 542 #define ACP_SCRATCH_REG_13 0x0010034 543 #define ACP_SCRATCH_REG_14 0x0010038 544 #define ACP_SCRATCH_REG_15 0x001003C 545 #define ACP_SCRATCH_REG_16 0x0010040 546 #define ACP_SCRATCH_REG_17 0x0010044 547 #define ACP_SCRATCH_REG_18 0x0010048 548 #define ACP_SCRATCH_REG_19 0x001004C 549 #define ACP_SCRATCH_REG_20 0x0010050 550 #define ACP_SCRATCH_REG_21 0x0010054 551 #define ACP_SCRATCH_REG_22 0x0010058 552 #define ACP_SCRATCH_REG_23 0x001005C 553 #define ACP_SCRATCH_REG_24 0x0010060 554 #define ACP_SCRATCH_REG_25 0x0010064 555 #define ACP_SCRATCH_REG_26 0x0010068 556 #define ACP_SCRATCH_REG_27 0x001006C 557 #define ACP_SCRATCH_REG_28 0x0010070 558 #define ACP_SCRATCH_REG_29 0x0010074 559 #define ACP_SCRATCH_REG_30 0x0010078 560 #define ACP_SCRATCH_REG_31 0x001007C 561 #define ACP_SCRATCH_REG_32 0x0010080 562 #define ACP_SCRATCH_REG_33 0x0010084 563 #define ACP_SCRATCH_REG_34 0x0010088 564 #define ACP_SCRATCH_REG_35 0x001008C 565 #define ACP_SCRATCH_REG_36 0x0010090 566 #define ACP_SCRATCH_REG_37 0x0010094 567 #define ACP_SCRATCH_REG_38 0x0010098 568 #define ACP_SCRATCH_REG_39 0x001009C 569 #define ACP_SCRATCH_REG_40 0x00100A0 570 #define ACP_SCRATCH_REG_41 0x00100A4 571 #define ACP_SCRATCH_REG_42 0x00100A8 572 #define ACP_SCRATCH_REG_43 0x00100AC 573 #define ACP_SCRATCH_REG_44 0x00100B0 574 #define ACP_SCRATCH_REG_45 0x00100B4 575 #define ACP_SCRATCH_REG_46 0x00100B8 576 #define ACP_SCRATCH_REG_47 0x00100BC 577 #define ACP_SCRATCH_REG_48 0x00100C0 578 #define ACP_SCRATCH_REG_49 0x00100C4 579 #define ACP_SCRATCH_REG_50 0x00100C8 580 #define ACP_SCRATCH_REG_51 0x00100CC 581 #define ACP_SCRATCH_REG_52 0x00100D0 582 #define ACP_SCRATCH_REG_53 0x00100D4 583 #define ACP_SCRATCH_REG_54 0x00100D8 584 #define ACP_SCRATCH_REG_55 0x00100DC 585 #define ACP_SCRATCH_REG_56 0x00100E0 586 #define ACP_SCRATCH_REG_57 0x00100E4 587 #define ACP_SCRATCH_REG_58 0x00100E8 588 #define ACP_SCRATCH_REG_59 0x00100EC 589 #define ACP_SCRATCH_REG_60 0x00100F0 590 #define ACP_SCRATCH_REG_61 0x00100F4 591 #define ACP_SCRATCH_REG_62 0x00100F8 592 #define ACP_SCRATCH_REG_63 0x00100FC 593 #define ACP_SCRATCH_REG_64 0x0010100 594 #define ACP_SCRATCH_REG_65 0x0010104 595 #define ACP_SCRATCH_REG_66 0x0010108 596 #define ACP_SCRATCH_REG_67 0x001010C 597 #define ACP_SCRATCH_REG_68 0x0010110 598 #define ACP_SCRATCH_REG_69 0x0010114 599 #define ACP_SCRATCH_REG_70 0x0010118 600 #define ACP_SCRATCH_REG_71 0x001011C 601 #define ACP_SCRATCH_REG_72 0x0010120 602 #define ACP_SCRATCH_REG_73 0x0010124 603 #define ACP_SCRATCH_REG_74 0x0010128 604 #define ACP_SCRATCH_REG_75 0x001012C 605 #define ACP_SCRATCH_REG_76 0x0010130 606 #define ACP_SCRATCH_REG_77 0x0010134 607 #define ACP_SCRATCH_REG_78 0x0010138 608 #define ACP_SCRATCH_REG_79 0x001013C 609 #define ACP_SCRATCH_REG_80 0x0010140 610 #define ACP_SCRATCH_REG_81 0x0010144 611 #define ACP_SCRATCH_REG_82 0x0010148 612 #define ACP_SCRATCH_REG_83 0x001014C 613 #define ACP_SCRATCH_REG_84 0x0010150 614 #define ACP_SCRATCH_REG_85 0x0010154 615 #define ACP_SCRATCH_REG_86 0x0010158 616 #define ACP_SCRATCH_REG_87 0x001015C 617 #define ACP_SCRATCH_REG_88 0x0010160 618 #define ACP_SCRATCH_REG_89 0x0010164 619 #define ACP_SCRATCH_REG_90 0x0010168 620 #define ACP_SCRATCH_REG_91 0x001016C 621 #define ACP_SCRATCH_REG_92 0x0010170 622 #define ACP_SCRATCH_REG_93 0x0010174 623 #define ACP_SCRATCH_REG_94 0x0010178 624 #define ACP_SCRATCH_REG_95 0x001017C 625 #define ACP_SCRATCH_REG_96 0x0010180 626 #define ACP_SCRATCH_REG_97 0x0010184 627 #define ACP_SCRATCH_REG_98 0x0010188 628 #define ACP_SCRATCH_REG_99 0x001018C 629 #define ACP_SCRATCH_REG_100 0x0010190 630 #define ACP_SCRATCH_REG_101 0x0010194 631 #define ACP_SCRATCH_REG_102 0x0010198 632 #define ACP_SCRATCH_REG_103 0x001019C 633 #define ACP_SCRATCH_REG_104 0x00101A0 634 #define ACP_SCRATCH_REG_105 0x00101A4 635 #define ACP_SCRATCH_REG_106 0x00101A8 636 #define ACP_SCRATCH_REG_107 0x00101AC 637 #define ACP_SCRATCH_REG_108 0x00101B0 638 #define ACP_SCRATCH_REG_109 0x00101B4 639 #define ACP_SCRATCH_REG_110 0x00101B8 640 #define ACP_SCRATCH_REG_111 0x00101BC 641 #define ACP_SCRATCH_REG_112 0x00101C0 642 #define ACP_SCRATCH_REG_113 0x00101C4 643 #define ACP_SCRATCH_REG_114 0x00101C8 644 #define ACP_SCRATCH_REG_115 0x00101CC 645 #define ACP_SCRATCH_REG_116 0x00101D0 646 #define ACP_SCRATCH_REG_117 0x00101D4 647 #define ACP_SCRATCH_REG_118 0x00101D8 648 #define ACP_SCRATCH_REG_119 0x00101DC 649 #define ACP_SCRATCH_REG_120 0x00101E0 650 #define ACP_SCRATCH_REG_121 0x00101E4 651 #define ACP_SCRATCH_REG_122 0x00101E8 652 #define ACP_SCRATCH_REG_123 0x00101EC 653 #define ACP_SCRATCH_REG_124 0x00101F0 654 #define ACP_SCRATCH_REG_125 0x00101F4 655 #define ACP_SCRATCH_REG_126 0x00101F8 656 #define ACP_SCRATCH_REG_127 0x00101FC 657 #define ACP_SCRATCH_REG_128 0x0010200 658 #endif 659