1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* SpacemiT clock and reset driver definitions for the K1 SoC */ 4 5 #ifndef __SOC_K1_SYSCON_H__ 6 #define __SOC_K1_SYSCON_H__ 7 8 #include "ccu.h" 9 10 /* APBS register offset */ 11 #define APBS_PLL1_SWCR1 0x100 12 #define APBS_PLL1_SWCR2 0x104 13 #define APBS_PLL1_SWCR3 0x108 14 #define APBS_PLL2_SWCR1 0x118 15 #define APBS_PLL2_SWCR2 0x11c 16 #define APBS_PLL2_SWCR3 0x120 17 #define APBS_PLL3_SWCR1 0x124 18 #define APBS_PLL3_SWCR2 0x128 19 #define APBS_PLL3_SWCR3 0x12c 20 21 /* MPMU register offset */ 22 #define MPMU_POSR 0x0010 23 #define MPMU_FCCR 0x0008 24 #define POSR_PLL1_LOCK BIT(27) 25 #define POSR_PLL2_LOCK BIT(28) 26 #define POSR_PLL3_LOCK BIT(29) 27 #define MPMU_SUCCR 0x0014 28 #define MPMU_ISCCR 0x0044 29 #define MPMU_WDTPCR 0x0200 30 #define MPMU_RIPCCR 0x0210 31 #define MPMU_ACGR 0x1024 32 #define MPMU_APBCSCR 0x1050 33 #define MPMU_SUCCR_1 0x10b0 34 35 /* APBC register offset */ 36 #define APBC_UART1_CLK_RST 0x00 37 #define APBC_UART2_CLK_RST 0x04 38 #define APBC_GPIO_CLK_RST 0x08 39 #define APBC_PWM0_CLK_RST 0x0c 40 #define APBC_PWM1_CLK_RST 0x10 41 #define APBC_PWM2_CLK_RST 0x14 42 #define APBC_PWM3_CLK_RST 0x18 43 #define APBC_TWSI8_CLK_RST 0x20 44 #define APBC_UART3_CLK_RST 0x24 45 #define APBC_RTC_CLK_RST 0x28 46 #define APBC_TWSI0_CLK_RST 0x2c 47 #define APBC_TWSI1_CLK_RST 0x30 48 #define APBC_TIMERS1_CLK_RST 0x34 49 #define APBC_TWSI2_CLK_RST 0x38 50 #define APBC_AIB_CLK_RST 0x3c 51 #define APBC_TWSI4_CLK_RST 0x40 52 #define APBC_TIMERS2_CLK_RST 0x44 53 #define APBC_ONEWIRE_CLK_RST 0x48 54 #define APBC_TWSI5_CLK_RST 0x4c 55 #define APBC_DRO_CLK_RST 0x58 56 #define APBC_IR_CLK_RST 0x5c 57 #define APBC_TWSI6_CLK_RST 0x60 58 #define APBC_COUNTER_CLK_SEL 0x64 59 #define APBC_TWSI7_CLK_RST 0x68 60 #define APBC_TSEN_CLK_RST 0x6c 61 #define APBC_UART4_CLK_RST 0x70 62 #define APBC_UART5_CLK_RST 0x74 63 #define APBC_UART6_CLK_RST 0x78 64 #define APBC_SSP3_CLK_RST 0x7c 65 #define APBC_SSPA0_CLK_RST 0x80 66 #define APBC_SSPA1_CLK_RST 0x84 67 #define APBC_IPC_AP2AUD_CLK_RST 0x90 68 #define APBC_UART7_CLK_RST 0x94 69 #define APBC_UART8_CLK_RST 0x98 70 #define APBC_UART9_CLK_RST 0x9c 71 #define APBC_CAN0_CLK_RST 0xa0 72 #define APBC_PWM4_CLK_RST 0xa8 73 #define APBC_PWM5_CLK_RST 0xac 74 #define APBC_PWM6_CLK_RST 0xb0 75 #define APBC_PWM7_CLK_RST 0xb4 76 #define APBC_PWM8_CLK_RST 0xb8 77 #define APBC_PWM9_CLK_RST 0xbc 78 #define APBC_PWM10_CLK_RST 0xc0 79 #define APBC_PWM11_CLK_RST 0xc4 80 #define APBC_PWM12_CLK_RST 0xc8 81 #define APBC_PWM13_CLK_RST 0xcc 82 #define APBC_PWM14_CLK_RST 0xd0 83 #define APBC_PWM15_CLK_RST 0xd4 84 #define APBC_PWM16_CLK_RST 0xd8 85 #define APBC_PWM17_CLK_RST 0xdc 86 #define APBC_PWM18_CLK_RST 0xe0 87 #define APBC_PWM19_CLK_RST 0xe4 88 89 /* APMU register offset */ 90 #define APMU_JPG_CLK_RES_CTRL 0x020 91 #define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 92 #define APMU_ISP_CLK_RES_CTRL 0x038 93 #define APMU_LCD_CLK_RES_CTRL1 0x044 94 #define APMU_LCD_SPI_CLK_RES_CTRL 0x048 95 #define APMU_LCD_CLK_RES_CTRL2 0x04c 96 #define APMU_CCIC_CLK_RES_CTRL 0x050 97 #define APMU_SDH0_CLK_RES_CTRL 0x054 98 #define APMU_SDH1_CLK_RES_CTRL 0x058 99 #define APMU_USB_CLK_RES_CTRL 0x05c 100 #define APMU_QSPI_CLK_RES_CTRL 0x060 101 #define APMU_DMA_CLK_RES_CTRL 0x064 102 #define APMU_AES_CLK_RES_CTRL 0x068 103 #define APMU_VPU_CLK_RES_CTRL 0x0a4 104 #define APMU_GPU_CLK_RES_CTRL 0x0cc 105 #define APMU_SDH2_CLK_RES_CTRL 0x0e0 106 #define APMU_PMUA_MC_CTRL 0x0e8 107 #define APMU_PMU_CC2_AP 0x100 108 #define APMU_PMUA_EM_CLK_RES_CTRL 0x104 109 #define APMU_AUDIO_CLK_RES_CTRL 0x14c 110 #define APMU_HDMI_CLK_RES_CTRL 0x1b8 111 #define APMU_CCI550_CLK_CTRL 0x300 112 #define APMU_ACLK_CLK_CTRL 0x388 113 #define APMU_CPU_C0_CLK_CTRL 0x38C 114 #define APMU_CPU_C1_CLK_CTRL 0x390 115 #define APMU_PCIE_CLK_RES_CTRL_0 0x3cc 116 #define APMU_PCIE_CLK_RES_CTRL_1 0x3d4 117 #define APMU_PCIE_CLK_RES_CTRL_2 0x3dc 118 #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 119 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec 120 121 /* RCPU register offsets */ 122 #define RCPU_SSP0_CLK_RST 0x0028 123 #define RCPU_I2C0_CLK_RST 0x0030 124 #define RCPU_UART1_CLK_RST 0x003c 125 #define RCPU_CAN_CLK_RST 0x0048 126 #define RCPU_IR_CLK_RST 0x004c 127 #define RCPU_UART0_CLK_RST 0x00d8 128 #define AUDIO_HDMI_CLK_CTRL 0x2044 129 130 /* RCPU2 register offsets */ 131 #define RCPU2_PWM0_CLK_RST 0x0000 132 #define RCPU2_PWM1_CLK_RST 0x0004 133 #define RCPU2_PWM2_CLK_RST 0x0008 134 #define RCPU2_PWM3_CLK_RST 0x000c 135 #define RCPU2_PWM4_CLK_RST 0x0010 136 #define RCPU2_PWM5_CLK_RST 0x0014 137 #define RCPU2_PWM6_CLK_RST 0x0018 138 #define RCPU2_PWM7_CLK_RST 0x001c 139 #define RCPU2_PWM8_CLK_RST 0x0020 140 #define RCPU2_PWM9_CLK_RST 0x0024 141 142 /* APBC2 register offsets */ 143 #define APBC2_UART1_CLK_RST 0x0000 144 #define APBC2_SSP2_CLK_RST 0x0004 145 #define APBC2_TWSI3_CLK_RST 0x0008 146 #define APBC2_RTC_CLK_RST 0x000c 147 #define APBC2_TIMERS0_CLK_RST 0x0010 148 #define APBC2_KPC_CLK_RST 0x0014 149 #define APBC2_GPIO_CLK_RST 0x001c 150 151 #endif /* __SOC_K1_SYSCON_H__ */ 152