1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* Copyright (c) 2017 Microsemi Corporation 3 */ 4 5 #ifndef _SOC_MSCC_OCELOT_H 6 #define _SOC_MSCC_OCELOT_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/net_tstamp.h> 10 #include <linux/if_vlan.h> 11 #include <linux/regmap.h> 12 #include <net/dsa.h> 13 14 /* Port Group IDs (PGID) are masks of destination ports. 15 * 16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each 17 * frame, and forwards the frame to the ports that are present in the logical 18 * AND of all 3 PGIDs. 19 * 20 * These PGID lookups are: 21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by 22 * which the switch selects a destination PGID: 23 * - The {DMAC, VID} is present in the MAC table. In that case, the 24 * destination PGID is given by the DEST_IDX field of the MAC table entry 25 * that matched. 26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The 27 * frame is disseminated as being either unicast, multicast or broadcast, 28 * and according to that, the destination PGID is chosen as being the 29 * value contained by ANA_FLOODING_FLD_UNICAST, 30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST. 31 * The destination PGID can be an unicast set: the first PGIDs, 0 to 32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from 33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to 34 * a physical port and has a single bit set in the destination ports mask: 35 * that corresponding to the port number itself. In contrast, a multicast 36 * PGID will have potentially more than one single bit set in the destination 37 * ports mask. 38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier 39 * dissects each frame and generates a 4-bit Link Aggregation Code which is 40 * used for this second PGID table lookup. The goal of link aggregation is to 41 * hash multiple flows within the same LAG on to different destination ports. 42 * The first lookup will result in a PGID with all the LAG members present in 43 * the destination ports mask, and the second lookup, by Link Aggregation 44 * Code, will ensure that each flow gets forwarded only to a single port out 45 * of that mask (there are no duplicates). 46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table 47 * is indexed with the ingress port (plus 80). These PGIDs answer the 48 * question "is port i allowed to forward traffic to port j?" If yes, then 49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used 50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge. 51 */ 52 53 /* Reserve some destination PGIDs at the end of the range: 54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses 55 * of the switch port net devices, towards the CPU port module. 56 * PGID_UC: the flooding destinations for unknown unicast traffic. 57 * PGID_MC: the flooding destinations for non-IP multicast traffic. 58 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic. 59 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic. 60 * PGID_BC: the flooding destinations for broadcast traffic. 61 */ 62 #define PGID_CPU 58 63 #define PGID_UC 59 64 #define PGID_MC 60 65 #define PGID_MCIPV4 61 66 #define PGID_MCIPV6 62 67 #define PGID_BC 63 68 69 #define for_each_unicast_dest_pgid(ocelot, pgid) \ 70 for ((pgid) = 0; \ 71 (pgid) < (ocelot)->num_phys_ports; \ 72 (pgid)++) 73 74 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \ 75 for ((pgid) = (ocelot)->num_phys_ports + 1; \ 76 (pgid) < PGID_CPU; \ 77 (pgid)++) 78 79 #define for_each_aggr_pgid(ocelot, pgid) \ 80 for ((pgid) = PGID_AGGR; \ 81 (pgid) < PGID_SRC; \ 82 (pgid)++) 83 84 /* Aggregation PGIDs, one per Link Aggregation Code */ 85 #define PGID_AGGR 64 86 87 /* Source PGIDs, one per physical port */ 88 #define PGID_SRC 80 89 90 #define IFH_TAG_TYPE_C 0 91 #define IFH_TAG_TYPE_S 1 92 93 #define IFH_REW_OP_NOOP 0x0 94 #define IFH_REW_OP_DSCP 0x1 95 #define IFH_REW_OP_ONE_STEP_PTP 0x2 96 #define IFH_REW_OP_TWO_STEP_PTP 0x3 97 #define IFH_REW_OP_ORIGIN_PTP 0x5 98 99 #define OCELOT_NUM_TC 8 100 101 #define OCELOT_SPEED_2500 0 102 #define OCELOT_SPEED_1000 1 103 #define OCELOT_SPEED_100 2 104 #define OCELOT_SPEED_10 3 105 106 #define OCELOT_PTP_PINS_NUM 4 107 108 #define TARGET_OFFSET 24 109 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 110 #define REG(reg, offset) [reg & REG_MASK] = offset 111 112 #define REG_RESERVED_ADDR 0xffffffff 113 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) 114 115 enum ocelot_target { 116 ANA = 1, 117 QS, 118 QSYS, 119 REW, 120 SYS, 121 S0, 122 S1, 123 S2, 124 HSIO, 125 PTP, 126 GCB, 127 DEV_GMII, 128 TARGET_MAX, 129 }; 130 131 enum ocelot_reg { 132 ANA_ADVLEARN = ANA << TARGET_OFFSET, 133 ANA_VLANMASK, 134 ANA_PORT_B_DOMAIN, 135 ANA_ANAGEFIL, 136 ANA_ANEVENTS, 137 ANA_STORMLIMIT_BURST, 138 ANA_STORMLIMIT_CFG, 139 ANA_ISOLATED_PORTS, 140 ANA_COMMUNITY_PORTS, 141 ANA_AUTOAGE, 142 ANA_MACTOPTIONS, 143 ANA_LEARNDISC, 144 ANA_AGENCTRL, 145 ANA_MIRRORPORTS, 146 ANA_EMIRRORPORTS, 147 ANA_FLOODING, 148 ANA_FLOODING_IPMC, 149 ANA_SFLOW_CFG, 150 ANA_PORT_MODE, 151 ANA_CUT_THRU_CFG, 152 ANA_PGID_PGID, 153 ANA_TABLES_ANMOVED, 154 ANA_TABLES_MACHDATA, 155 ANA_TABLES_MACLDATA, 156 ANA_TABLES_STREAMDATA, 157 ANA_TABLES_MACACCESS, 158 ANA_TABLES_MACTINDX, 159 ANA_TABLES_VLANACCESS, 160 ANA_TABLES_VLANTIDX, 161 ANA_TABLES_ISDXACCESS, 162 ANA_TABLES_ISDXTIDX, 163 ANA_TABLES_ENTRYLIM, 164 ANA_TABLES_PTP_ID_HIGH, 165 ANA_TABLES_PTP_ID_LOW, 166 ANA_TABLES_STREAMACCESS, 167 ANA_TABLES_STREAMTIDX, 168 ANA_TABLES_SEQ_HISTORY, 169 ANA_TABLES_SEQ_MASK, 170 ANA_TABLES_SFID_MASK, 171 ANA_TABLES_SFIDACCESS, 172 ANA_TABLES_SFIDTIDX, 173 ANA_MSTI_STATE, 174 ANA_OAM_UPM_LM_CNT, 175 ANA_SG_ACCESS_CTRL, 176 ANA_SG_CONFIG_REG_1, 177 ANA_SG_CONFIG_REG_2, 178 ANA_SG_CONFIG_REG_3, 179 ANA_SG_CONFIG_REG_4, 180 ANA_SG_CONFIG_REG_5, 181 ANA_SG_GCL_GS_CONFIG, 182 ANA_SG_GCL_TI_CONFIG, 183 ANA_SG_STATUS_REG_1, 184 ANA_SG_STATUS_REG_2, 185 ANA_SG_STATUS_REG_3, 186 ANA_PORT_VLAN_CFG, 187 ANA_PORT_DROP_CFG, 188 ANA_PORT_QOS_CFG, 189 ANA_PORT_VCAP_CFG, 190 ANA_PORT_VCAP_S1_KEY_CFG, 191 ANA_PORT_VCAP_S2_CFG, 192 ANA_PORT_PCP_DEI_MAP, 193 ANA_PORT_CPU_FWD_CFG, 194 ANA_PORT_CPU_FWD_BPDU_CFG, 195 ANA_PORT_CPU_FWD_GARP_CFG, 196 ANA_PORT_CPU_FWD_CCM_CFG, 197 ANA_PORT_PORT_CFG, 198 ANA_PORT_POL_CFG, 199 ANA_PORT_PTP_CFG, 200 ANA_PORT_PTP_DLY1_CFG, 201 ANA_PORT_PTP_DLY2_CFG, 202 ANA_PORT_SFID_CFG, 203 ANA_PFC_PFC_CFG, 204 ANA_PFC_PFC_TIMER, 205 ANA_IPT_OAM_MEP_CFG, 206 ANA_IPT_IPT, 207 ANA_PPT_PPT, 208 ANA_FID_MAP_FID_MAP, 209 ANA_AGGR_CFG, 210 ANA_CPUQ_CFG, 211 ANA_CPUQ_CFG2, 212 ANA_CPUQ_8021_CFG, 213 ANA_DSCP_CFG, 214 ANA_DSCP_REWR_CFG, 215 ANA_VCAP_RNG_TYPE_CFG, 216 ANA_VCAP_RNG_VAL_CFG, 217 ANA_VRAP_CFG, 218 ANA_VRAP_HDR_DATA, 219 ANA_VRAP_HDR_MASK, 220 ANA_DISCARD_CFG, 221 ANA_FID_CFG, 222 ANA_POL_PIR_CFG, 223 ANA_POL_CIR_CFG, 224 ANA_POL_MODE_CFG, 225 ANA_POL_PIR_STATE, 226 ANA_POL_CIR_STATE, 227 ANA_POL_STATE, 228 ANA_POL_FLOWC, 229 ANA_POL_HYST, 230 ANA_POL_MISC_CFG, 231 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 232 QS_XTR_RD, 233 QS_XTR_FRM_PRUNING, 234 QS_XTR_FLUSH, 235 QS_XTR_DATA_PRESENT, 236 QS_XTR_CFG, 237 QS_INJ_GRP_CFG, 238 QS_INJ_WR, 239 QS_INJ_CTRL, 240 QS_INJ_STATUS, 241 QS_INJ_ERR, 242 QS_INH_DBG, 243 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 244 QSYS_SWITCH_PORT_MODE, 245 QSYS_STAT_CNT_CFG, 246 QSYS_EEE_CFG, 247 QSYS_EEE_THRES, 248 QSYS_IGR_NO_SHARING, 249 QSYS_EGR_NO_SHARING, 250 QSYS_SW_STATUS, 251 QSYS_EXT_CPU_CFG, 252 QSYS_PAD_CFG, 253 QSYS_CPU_GROUP_MAP, 254 QSYS_QMAP, 255 QSYS_ISDX_SGRP, 256 QSYS_TIMED_FRAME_ENTRY, 257 QSYS_TFRM_MISC, 258 QSYS_TFRM_PORT_DLY, 259 QSYS_TFRM_TIMER_CFG_1, 260 QSYS_TFRM_TIMER_CFG_2, 261 QSYS_TFRM_TIMER_CFG_3, 262 QSYS_TFRM_TIMER_CFG_4, 263 QSYS_TFRM_TIMER_CFG_5, 264 QSYS_TFRM_TIMER_CFG_6, 265 QSYS_TFRM_TIMER_CFG_7, 266 QSYS_TFRM_TIMER_CFG_8, 267 QSYS_RED_PROFILE, 268 QSYS_RES_QOS_MODE, 269 QSYS_RES_CFG, 270 QSYS_RES_STAT, 271 QSYS_EGR_DROP_MODE, 272 QSYS_EQ_CTRL, 273 QSYS_EVENTS_CORE, 274 QSYS_QMAXSDU_CFG_0, 275 QSYS_QMAXSDU_CFG_1, 276 QSYS_QMAXSDU_CFG_2, 277 QSYS_QMAXSDU_CFG_3, 278 QSYS_QMAXSDU_CFG_4, 279 QSYS_QMAXSDU_CFG_5, 280 QSYS_QMAXSDU_CFG_6, 281 QSYS_QMAXSDU_CFG_7, 282 QSYS_PREEMPTION_CFG, 283 QSYS_CIR_CFG, 284 QSYS_EIR_CFG, 285 QSYS_SE_CFG, 286 QSYS_SE_DWRR_CFG, 287 QSYS_SE_CONNECT, 288 QSYS_SE_DLB_SENSE, 289 QSYS_CIR_STATE, 290 QSYS_EIR_STATE, 291 QSYS_SE_STATE, 292 QSYS_HSCH_MISC_CFG, 293 QSYS_TAG_CONFIG, 294 QSYS_TAS_PARAM_CFG_CTRL, 295 QSYS_PORT_MAX_SDU, 296 QSYS_PARAM_CFG_REG_1, 297 QSYS_PARAM_CFG_REG_2, 298 QSYS_PARAM_CFG_REG_3, 299 QSYS_PARAM_CFG_REG_4, 300 QSYS_PARAM_CFG_REG_5, 301 QSYS_GCL_CFG_REG_1, 302 QSYS_GCL_CFG_REG_2, 303 QSYS_PARAM_STATUS_REG_1, 304 QSYS_PARAM_STATUS_REG_2, 305 QSYS_PARAM_STATUS_REG_3, 306 QSYS_PARAM_STATUS_REG_4, 307 QSYS_PARAM_STATUS_REG_5, 308 QSYS_PARAM_STATUS_REG_6, 309 QSYS_PARAM_STATUS_REG_7, 310 QSYS_PARAM_STATUS_REG_8, 311 QSYS_PARAM_STATUS_REG_9, 312 QSYS_GCL_STATUS_REG_1, 313 QSYS_GCL_STATUS_REG_2, 314 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 315 REW_TAG_CFG, 316 REW_PORT_CFG, 317 REW_DSCP_CFG, 318 REW_PCP_DEI_QOS_MAP_CFG, 319 REW_PTP_CFG, 320 REW_PTP_DLY1_CFG, 321 REW_RED_TAG_CFG, 322 REW_DSCP_REMAP_DP1_CFG, 323 REW_DSCP_REMAP_CFG, 324 REW_STAT_CFG, 325 REW_REW_STICKY, 326 REW_PPT, 327 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 328 SYS_COUNT_RX_UNICAST, 329 SYS_COUNT_RX_MULTICAST, 330 SYS_COUNT_RX_BROADCAST, 331 SYS_COUNT_RX_SHORTS, 332 SYS_COUNT_RX_FRAGMENTS, 333 SYS_COUNT_RX_JABBERS, 334 SYS_COUNT_RX_CRC_ALIGN_ERRS, 335 SYS_COUNT_RX_SYM_ERRS, 336 SYS_COUNT_RX_64, 337 SYS_COUNT_RX_65_127, 338 SYS_COUNT_RX_128_255, 339 SYS_COUNT_RX_256_1023, 340 SYS_COUNT_RX_1024_1526, 341 SYS_COUNT_RX_1527_MAX, 342 SYS_COUNT_RX_PAUSE, 343 SYS_COUNT_RX_CONTROL, 344 SYS_COUNT_RX_LONGS, 345 SYS_COUNT_RX_CLASSIFIED_DROPS, 346 SYS_COUNT_TX_OCTETS, 347 SYS_COUNT_TX_UNICAST, 348 SYS_COUNT_TX_MULTICAST, 349 SYS_COUNT_TX_BROADCAST, 350 SYS_COUNT_TX_COLLISION, 351 SYS_COUNT_TX_DROPS, 352 SYS_COUNT_TX_PAUSE, 353 SYS_COUNT_TX_64, 354 SYS_COUNT_TX_65_127, 355 SYS_COUNT_TX_128_511, 356 SYS_COUNT_TX_512_1023, 357 SYS_COUNT_TX_1024_1526, 358 SYS_COUNT_TX_1527_MAX, 359 SYS_COUNT_TX_AGING, 360 SYS_RESET_CFG, 361 SYS_SR_ETYPE_CFG, 362 SYS_VLAN_ETYPE_CFG, 363 SYS_PORT_MODE, 364 SYS_FRONT_PORT_MODE, 365 SYS_FRM_AGING, 366 SYS_STAT_CFG, 367 SYS_SW_STATUS, 368 SYS_MISC_CFG, 369 SYS_REW_MAC_HIGH_CFG, 370 SYS_REW_MAC_LOW_CFG, 371 SYS_TIMESTAMP_OFFSET, 372 SYS_CMID, 373 SYS_PAUSE_CFG, 374 SYS_PAUSE_TOT_CFG, 375 SYS_ATOP, 376 SYS_ATOP_TOT_CFG, 377 SYS_MAC_FC_CFG, 378 SYS_MMGT, 379 SYS_MMGT_FAST, 380 SYS_EVENTS_DIF, 381 SYS_EVENTS_CORE, 382 SYS_CNT, 383 SYS_PTP_STATUS, 384 SYS_PTP_TXSTAMP, 385 SYS_PTP_NXT, 386 SYS_PTP_CFG, 387 SYS_RAM_INIT, 388 SYS_CM_ADDR, 389 SYS_CM_DATA_WR, 390 SYS_CM_DATA_RD, 391 SYS_CM_OP, 392 SYS_CM_DATA, 393 PTP_PIN_CFG = PTP << TARGET_OFFSET, 394 PTP_PIN_TOD_SEC_MSB, 395 PTP_PIN_TOD_SEC_LSB, 396 PTP_PIN_TOD_NSEC, 397 PTP_PIN_WF_HIGH_PERIOD, 398 PTP_PIN_WF_LOW_PERIOD, 399 PTP_CFG_MISC, 400 PTP_CLK_CFG_ADJ_CFG, 401 PTP_CLK_CFG_ADJ_FREQ, 402 GCB_SOFT_RST = GCB << TARGET_OFFSET, 403 GCB_MIIM_MII_STATUS, 404 GCB_MIIM_MII_CMD, 405 GCB_MIIM_MII_DATA, 406 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, 407 DEV_PORT_MISC, 408 DEV_EVENTS, 409 DEV_EEE_CFG, 410 DEV_RX_PATH_DELAY, 411 DEV_TX_PATH_DELAY, 412 DEV_PTP_PREDICT_CFG, 413 DEV_MAC_ENA_CFG, 414 DEV_MAC_MODE_CFG, 415 DEV_MAC_MAXLEN_CFG, 416 DEV_MAC_TAGS_CFG, 417 DEV_MAC_ADV_CHK_CFG, 418 DEV_MAC_IFG_CFG, 419 DEV_MAC_HDX_CFG, 420 DEV_MAC_DBG_CFG, 421 DEV_MAC_FC_MAC_LOW_CFG, 422 DEV_MAC_FC_MAC_HIGH_CFG, 423 DEV_MAC_STICKY, 424 PCS1G_CFG, 425 PCS1G_MODE_CFG, 426 PCS1G_SD_CFG, 427 PCS1G_ANEG_CFG, 428 PCS1G_ANEG_NP_CFG, 429 PCS1G_LB_CFG, 430 PCS1G_DBG_CFG, 431 PCS1G_CDET_CFG, 432 PCS1G_ANEG_STATUS, 433 PCS1G_ANEG_NP_STATUS, 434 PCS1G_LINK_STATUS, 435 PCS1G_LINK_DOWN_CNT, 436 PCS1G_STICKY, 437 PCS1G_DEBUG_STATUS, 438 PCS1G_LPI_CFG, 439 PCS1G_LPI_WAKE_ERROR_CNT, 440 PCS1G_LPI_STATUS, 441 PCS1G_TSTPAT_MODE_CFG, 442 PCS1G_TSTPAT_STATUS, 443 DEV_PCS_FX100_CFG, 444 DEV_PCS_FX100_STATUS, 445 }; 446 447 enum ocelot_regfield { 448 ANA_ADVLEARN_VLAN_CHK, 449 ANA_ADVLEARN_LEARN_MIRROR, 450 ANA_ANEVENTS_FLOOD_DISCARD, 451 ANA_ANEVENTS_MSTI_DROP, 452 ANA_ANEVENTS_ACLKILL, 453 ANA_ANEVENTS_ACLUSED, 454 ANA_ANEVENTS_AUTOAGE, 455 ANA_ANEVENTS_VS2TTL1, 456 ANA_ANEVENTS_STORM_DROP, 457 ANA_ANEVENTS_LEARN_DROP, 458 ANA_ANEVENTS_AGED_ENTRY, 459 ANA_ANEVENTS_CPU_LEARN_FAILED, 460 ANA_ANEVENTS_AUTO_LEARN_FAILED, 461 ANA_ANEVENTS_LEARN_REMOVE, 462 ANA_ANEVENTS_AUTO_LEARNED, 463 ANA_ANEVENTS_AUTO_MOVED, 464 ANA_ANEVENTS_DROPPED, 465 ANA_ANEVENTS_CLASSIFIED_DROP, 466 ANA_ANEVENTS_CLASSIFIED_COPY, 467 ANA_ANEVENTS_VLAN_DISCARD, 468 ANA_ANEVENTS_FWD_DISCARD, 469 ANA_ANEVENTS_MULTICAST_FLOOD, 470 ANA_ANEVENTS_UNICAST_FLOOD, 471 ANA_ANEVENTS_DEST_KNOWN, 472 ANA_ANEVENTS_BUCKET3_MATCH, 473 ANA_ANEVENTS_BUCKET2_MATCH, 474 ANA_ANEVENTS_BUCKET1_MATCH, 475 ANA_ANEVENTS_BUCKET0_MATCH, 476 ANA_ANEVENTS_CPU_OPERATION, 477 ANA_ANEVENTS_DMAC_LOOKUP, 478 ANA_ANEVENTS_SMAC_LOOKUP, 479 ANA_ANEVENTS_SEQ_GEN_ERR_0, 480 ANA_ANEVENTS_SEQ_GEN_ERR_1, 481 ANA_TABLES_MACACCESS_B_DOM, 482 ANA_TABLES_MACTINDX_BUCKET, 483 ANA_TABLES_MACTINDX_M_INDEX, 484 QSYS_SWITCH_PORT_MODE_PORT_ENA, 485 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG, 486 QSYS_SWITCH_PORT_MODE_YEL_RSRVD, 487 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE, 488 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 489 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE, 490 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 491 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 492 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 493 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 494 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 495 SYS_PORT_MODE_DATA_WO_TS, 496 SYS_PORT_MODE_INCL_INJ_HDR, 497 SYS_PORT_MODE_INCL_XTR_HDR, 498 SYS_PORT_MODE_INCL_HDR_ERR, 499 SYS_RESET_CFG_CORE_ENA, 500 SYS_RESET_CFG_MEM_ENA, 501 SYS_RESET_CFG_MEM_INIT, 502 GCB_SOFT_RST_SWC_RST, 503 GCB_MIIM_MII_STATUS_PENDING, 504 GCB_MIIM_MII_STATUS_BUSY, 505 SYS_PAUSE_CFG_PAUSE_START, 506 SYS_PAUSE_CFG_PAUSE_STOP, 507 SYS_PAUSE_CFG_PAUSE_ENA, 508 REGFIELD_MAX 509 }; 510 511 enum { 512 /* VCAP_CORE_CFG */ 513 VCAP_CORE_UPDATE_CTRL, 514 VCAP_CORE_MV_CFG, 515 /* VCAP_CORE_CACHE */ 516 VCAP_CACHE_ENTRY_DAT, 517 VCAP_CACHE_MASK_DAT, 518 VCAP_CACHE_ACTION_DAT, 519 VCAP_CACHE_CNT_DAT, 520 VCAP_CACHE_TG_DAT, 521 /* VCAP_CONST */ 522 VCAP_CONST_VCAP_VER, 523 VCAP_CONST_ENTRY_WIDTH, 524 VCAP_CONST_ENTRY_CNT, 525 VCAP_CONST_ENTRY_SWCNT, 526 VCAP_CONST_ENTRY_TG_WIDTH, 527 VCAP_CONST_ACTION_DEF_CNT, 528 VCAP_CONST_ACTION_WIDTH, 529 VCAP_CONST_CNT_WIDTH, 530 VCAP_CONST_CORE_CNT, 531 VCAP_CONST_IF_CNT, 532 }; 533 534 enum ocelot_ptp_pins { 535 PTP_PIN_0, 536 PTP_PIN_1, 537 PTP_PIN_2, 538 PTP_PIN_3, 539 TOD_ACC_PIN 540 }; 541 542 struct ocelot_stat_layout { 543 u32 offset; 544 char name[ETH_GSTRING_LEN]; 545 }; 546 547 enum ocelot_tag_prefix { 548 OCELOT_TAG_PREFIX_DISABLED = 0, 549 OCELOT_TAG_PREFIX_NONE, 550 OCELOT_TAG_PREFIX_SHORT, 551 OCELOT_TAG_PREFIX_LONG, 552 }; 553 554 struct ocelot; 555 556 struct ocelot_ops { 557 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port); 558 int (*netdev_to_port)(struct net_device *dev); 559 int (*reset)(struct ocelot *ocelot); 560 u16 (*wm_enc)(u16 value); 561 u16 (*wm_dec)(u16 value); 562 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse); 563 }; 564 565 struct ocelot_vcap_block { 566 struct list_head rules; 567 int count; 568 int pol_lpr; 569 }; 570 571 struct ocelot_vlan { 572 bool valid; 573 u16 vid; 574 }; 575 576 enum ocelot_sb { 577 OCELOT_SB_BUF, 578 OCELOT_SB_REF, 579 OCELOT_SB_NUM, 580 }; 581 582 enum ocelot_sb_pool { 583 OCELOT_SB_POOL_ING, 584 OCELOT_SB_POOL_EGR, 585 OCELOT_SB_POOL_NUM, 586 }; 587 588 struct ocelot_port { 589 struct ocelot *ocelot; 590 591 struct regmap *target; 592 593 bool vlan_aware; 594 /* VLAN that untagged frames are classified to, on ingress */ 595 struct ocelot_vlan pvid_vlan; 596 /* The VLAN ID that will be transmitted as untagged, on egress */ 597 struct ocelot_vlan native_vlan; 598 599 u8 ptp_cmd; 600 struct sk_buff_head tx_skbs; 601 u8 ts_id; 602 spinlock_t ts_id_lock; 603 604 phy_interface_t phy_mode; 605 606 u8 *xmit_template; 607 bool is_dsa_8021q_cpu; 608 bool learn_ena; 609 610 struct net_device *bond; 611 bool lag_tx_active; 612 }; 613 614 struct ocelot { 615 struct device *dev; 616 struct devlink *devlink; 617 struct devlink_port *devlink_ports; 618 619 const struct ocelot_ops *ops; 620 struct regmap *targets[TARGET_MAX]; 621 struct regmap_field *regfields[REGFIELD_MAX]; 622 const u32 *const *map; 623 const struct ocelot_stat_layout *stats_layout; 624 unsigned int num_stats; 625 626 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM]; 627 int packet_buffer_size; 628 int num_frame_refs; 629 int num_mact_rows; 630 631 struct net_device *hw_bridge_dev; 632 u16 bridge_mask; 633 u16 bridge_fwd_mask; 634 635 struct ocelot_port **ports; 636 637 u8 base_mac[ETH_ALEN]; 638 639 /* Keep track of the vlan port masks */ 640 u32 vlan_mask[VLAN_N_VID]; 641 642 /* Switches like VSC9959 have flooding per traffic class */ 643 int num_flooding_pgids; 644 645 /* In tables like ANA:PORT and the ANA:PGID:PGID mask, 646 * the CPU is located after the physical ports (at the 647 * num_phys_ports index). 648 */ 649 u8 num_phys_ports; 650 651 int npi; 652 653 enum ocelot_tag_prefix npi_inj_prefix; 654 enum ocelot_tag_prefix npi_xtr_prefix; 655 656 struct list_head multicast; 657 struct list_head pgids; 658 659 struct list_head dummy_rules; 660 struct ocelot_vcap_block block[3]; 661 struct vcap_props *vcap; 662 663 /* Workqueue to check statistics for overflow with its lock */ 664 struct mutex stats_lock; 665 u64 *stats; 666 struct delayed_work stats_work; 667 struct workqueue_struct *stats_queue; 668 669 struct workqueue_struct *owq; 670 671 u8 ptp:1; 672 struct ptp_clock *ptp_clock; 673 struct ptp_clock_info ptp_info; 674 struct hwtstamp_config hwtstamp_config; 675 /* Protects the PTP interface state */ 676 struct mutex ptp_lock; 677 /* Protects the PTP clock */ 678 spinlock_t ptp_clock_lock; 679 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; 680 }; 681 682 struct ocelot_policer { 683 u32 rate; /* kilobit per second */ 684 u32 burst; /* bytes */ 685 }; 686 687 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 688 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 689 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 690 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) 691 692 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 693 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 694 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 695 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 696 697 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 698 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 699 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 700 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 701 702 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) 703 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) 704 #define ocelot_fields_write(ocelot, id, reg, val) regmap_fields_write((ocelot)->regfields[(reg)], (id), (val)) 705 #define ocelot_fields_read(ocelot, id, reg, val) regmap_fields_read((ocelot)->regfields[(reg)], (id), (val)) 706 707 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \ 708 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 709 #define ocelot_target_read_gix(ocelot, target, reg, gi) \ 710 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi)) 711 #define ocelot_target_read_rix(ocelot, target, reg, ri) \ 712 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri)) 713 #define ocelot_target_read(ocelot, target, reg) \ 714 __ocelot_target_read_ix(ocelot, target, reg, 0) 715 716 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \ 717 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 718 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \ 719 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi)) 720 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \ 721 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri)) 722 #define ocelot_target_write(ocelot, target, val, reg) \ 723 __ocelot_target_write_ix(ocelot, target, val, reg, 0) 724 725 /* I/O */ 726 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 727 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 728 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg); 729 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 730 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 731 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, 732 u32 offset); 733 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target, 734 u32 reg, u32 offset); 735 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target, 736 u32 val, u32 reg, u32 offset); 737 738 /* Packet I/O */ 739 #if IS_ENABLED(CONFIG_MSCC_OCELOT_SWITCH_LIB) 740 741 bool ocelot_can_inject(struct ocelot *ocelot, int grp); 742 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 743 u32 rew_op, struct sk_buff *skb); 744 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb); 745 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp); 746 747 #else 748 749 static inline bool ocelot_can_inject(struct ocelot *ocelot, int grp) 750 { 751 return false; 752 } 753 754 static inline void ocelot_port_inject_frame(struct ocelot *ocelot, int port, 755 int grp, u32 rew_op, 756 struct sk_buff *skb) 757 { 758 } 759 760 static inline int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, 761 struct sk_buff **skb) 762 { 763 return -EIO; 764 } 765 766 static inline void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 767 { 768 } 769 770 #endif 771 772 /* Hardware initialization */ 773 int ocelot_regfields_init(struct ocelot *ocelot, 774 const struct reg_field *const regfields); 775 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res); 776 int ocelot_init(struct ocelot *ocelot); 777 void ocelot_deinit(struct ocelot *ocelot); 778 void ocelot_init_port(struct ocelot *ocelot, int port); 779 void ocelot_deinit_port(struct ocelot *ocelot, int port); 780 781 /* DSA callbacks */ 782 void ocelot_port_enable(struct ocelot *ocelot, int port, 783 struct phy_device *phy); 784 void ocelot_port_disable(struct ocelot *ocelot, int port); 785 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); 786 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); 787 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset); 788 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 789 struct ethtool_ts_info *info); 790 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs); 791 int ocelot_port_flush(struct ocelot *ocelot, int port); 792 void ocelot_adjust_link(struct ocelot *ocelot, int port, 793 struct phy_device *phydev); 794 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled); 795 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state); 796 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot); 797 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 798 struct switchdev_brport_flags val); 799 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 800 struct switchdev_brport_flags val); 801 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 802 struct net_device *bridge); 803 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 804 struct net_device *bridge); 805 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 806 dsa_fdb_dump_cb_t *cb, void *data); 807 int ocelot_fdb_add(struct ocelot *ocelot, int port, 808 const unsigned char *addr, u16 vid); 809 int ocelot_fdb_del(struct ocelot *ocelot, int port, 810 const unsigned char *addr, u16 vid); 811 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 812 bool untagged); 813 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 814 bool untagged); 815 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid); 816 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr); 817 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr); 818 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 819 struct sk_buff *clone); 820 void ocelot_get_txtstamp(struct ocelot *ocelot); 821 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu); 822 int ocelot_get_max_mtu(struct ocelot *ocelot, int port); 823 int ocelot_port_policer_add(struct ocelot *ocelot, int port, 824 struct ocelot_policer *pol); 825 int ocelot_port_policer_del(struct ocelot *ocelot, int port); 826 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port, 827 struct flow_cls_offload *f, bool ingress); 828 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port, 829 struct flow_cls_offload *f, bool ingress); 830 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port, 831 struct flow_cls_offload *f, bool ingress); 832 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 833 const struct switchdev_obj_port_mdb *mdb); 834 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 835 const struct switchdev_obj_port_mdb *mdb); 836 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 837 struct net_device *bond, 838 struct netdev_lag_upper_info *info); 839 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 840 struct net_device *bond); 841 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active); 842 843 int ocelot_devlink_sb_register(struct ocelot *ocelot); 844 void ocelot_devlink_sb_unregister(struct ocelot *ocelot); 845 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index, 846 u16 pool_index, 847 struct devlink_sb_pool_info *pool_info); 848 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index, 849 u16 pool_index, u32 size, 850 enum devlink_sb_threshold_type threshold_type, 851 struct netlink_ext_ack *extack); 852 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port, 853 unsigned int sb_index, u16 pool_index, 854 u32 *p_threshold); 855 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port, 856 unsigned int sb_index, u16 pool_index, 857 u32 threshold, struct netlink_ext_ack *extack); 858 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port, 859 unsigned int sb_index, u16 tc_index, 860 enum devlink_sb_pool_type pool_type, 861 u16 *p_pool_index, u32 *p_threshold); 862 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port, 863 unsigned int sb_index, u16 tc_index, 864 enum devlink_sb_pool_type pool_type, 865 u16 pool_index, u32 threshold, 866 struct netlink_ext_ack *extack); 867 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index); 868 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index); 869 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port, 870 unsigned int sb_index, u16 pool_index, 871 u32 *p_cur, u32 *p_max); 872 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port, 873 unsigned int sb_index, u16 tc_index, 874 enum devlink_sb_pool_type pool_type, 875 u32 *p_cur, u32 *p_max); 876 877 #endif 878