1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* Copyright (c) 2017 Microsemi Corporation 3 */ 4 5 #ifndef _SOC_MSCC_OCELOT_H 6 #define _SOC_MSCC_OCELOT_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/net_tstamp.h> 10 #include <linux/if_vlan.h> 11 #include <linux/regmap.h> 12 #include <net/dsa.h> 13 14 /* Port Group IDs (PGID) are masks of destination ports. 15 * 16 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each 17 * frame, and forwards the frame to the ports that are present in the logical 18 * AND of all 3 PGIDs. 19 * 20 * These PGID lookups are: 21 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by 22 * which the switch selects a destination PGID: 23 * - The {DMAC, VID} is present in the MAC table. In that case, the 24 * destination PGID is given by the DEST_IDX field of the MAC table entry 25 * that matched. 26 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The 27 * frame is disseminated as being either unicast, multicast or broadcast, 28 * and according to that, the destination PGID is chosen as being the 29 * value contained by ANA_FLOODING_FLD_UNICAST, 30 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST. 31 * The destination PGID can be an unicast set: the first PGIDs, 0 to 32 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from 33 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to 34 * a physical port and has a single bit set in the destination ports mask: 35 * that corresponding to the port number itself. In contrast, a multicast 36 * PGID will have potentially more than one single bit set in the destination 37 * ports mask. 38 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier 39 * dissects each frame and generates a 4-bit Link Aggregation Code which is 40 * used for this second PGID table lookup. The goal of link aggregation is to 41 * hash multiple flows within the same LAG on to different destination ports. 42 * The first lookup will result in a PGID with all the LAG members present in 43 * the destination ports mask, and the second lookup, by Link Aggregation 44 * Code, will ensure that each flow gets forwarded only to a single port out 45 * of that mask (there are no duplicates). 46 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table 47 * is indexed with the ingress port (plus 80). These PGIDs answer the 48 * question "is port i allowed to forward traffic to port j?" If yes, then 49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used 50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge. 51 */ 52 53 /* Reserve some destination PGIDs at the end of the range: 54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses 55 * of the switch port net devices, towards the CPU port module. 56 * PGID_UC: the flooding destinations for unknown unicast traffic. 57 * PGID_MC: the flooding destinations for broadcast and non-IP multicast 58 * traffic. 59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic. 60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic. 61 */ 62 #define PGID_CPU 59 63 #define PGID_UC 60 64 #define PGID_MC 61 65 #define PGID_MCIPV4 62 66 #define PGID_MCIPV6 63 67 68 #define for_each_unicast_dest_pgid(ocelot, pgid) \ 69 for ((pgid) = 0; \ 70 (pgid) < (ocelot)->num_phys_ports; \ 71 (pgid)++) 72 73 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \ 74 for ((pgid) = (ocelot)->num_phys_ports + 1; \ 75 (pgid) < PGID_CPU; \ 76 (pgid)++) 77 78 #define for_each_aggr_pgid(ocelot, pgid) \ 79 for ((pgid) = PGID_AGGR; \ 80 (pgid) < PGID_SRC; \ 81 (pgid)++) 82 83 /* Aggregation PGIDs, one per Link Aggregation Code */ 84 #define PGID_AGGR 64 85 86 /* Source PGIDs, one per physical port */ 87 #define PGID_SRC 80 88 89 #define IFH_INJ_BYPASS BIT(31) 90 #define IFH_INJ_POP_CNT_DISABLE (3 << 28) 91 92 #define IFH_TAG_TYPE_C 0 93 #define IFH_TAG_TYPE_S 1 94 95 #define IFH_REW_OP_NOOP 0x0 96 #define IFH_REW_OP_DSCP 0x1 97 #define IFH_REW_OP_ONE_STEP_PTP 0x2 98 #define IFH_REW_OP_TWO_STEP_PTP 0x3 99 #define IFH_REW_OP_ORIGIN_PTP 0x5 100 101 #define OCELOT_NUM_TC 8 102 #define OCELOT_TAG_LEN 16 103 #define OCELOT_SHORT_PREFIX_LEN 4 104 #define OCELOT_LONG_PREFIX_LEN 16 105 #define OCELOT_TOTAL_TAG_LEN (OCELOT_SHORT_PREFIX_LEN + OCELOT_TAG_LEN) 106 107 #define OCELOT_SPEED_2500 0 108 #define OCELOT_SPEED_1000 1 109 #define OCELOT_SPEED_100 2 110 #define OCELOT_SPEED_10 3 111 112 #define OCELOT_PTP_PINS_NUM 4 113 114 #define TARGET_OFFSET 24 115 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0) 116 #define REG(reg, offset) [reg & REG_MASK] = offset 117 118 #define REG_RESERVED_ADDR 0xffffffff 119 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR) 120 121 enum ocelot_target { 122 ANA = 1, 123 QS, 124 QSYS, 125 REW, 126 SYS, 127 S0, 128 S1, 129 S2, 130 HSIO, 131 PTP, 132 GCB, 133 DEV_GMII, 134 TARGET_MAX, 135 }; 136 137 enum ocelot_reg { 138 ANA_ADVLEARN = ANA << TARGET_OFFSET, 139 ANA_VLANMASK, 140 ANA_PORT_B_DOMAIN, 141 ANA_ANAGEFIL, 142 ANA_ANEVENTS, 143 ANA_STORMLIMIT_BURST, 144 ANA_STORMLIMIT_CFG, 145 ANA_ISOLATED_PORTS, 146 ANA_COMMUNITY_PORTS, 147 ANA_AUTOAGE, 148 ANA_MACTOPTIONS, 149 ANA_LEARNDISC, 150 ANA_AGENCTRL, 151 ANA_MIRRORPORTS, 152 ANA_EMIRRORPORTS, 153 ANA_FLOODING, 154 ANA_FLOODING_IPMC, 155 ANA_SFLOW_CFG, 156 ANA_PORT_MODE, 157 ANA_CUT_THRU_CFG, 158 ANA_PGID_PGID, 159 ANA_TABLES_ANMOVED, 160 ANA_TABLES_MACHDATA, 161 ANA_TABLES_MACLDATA, 162 ANA_TABLES_STREAMDATA, 163 ANA_TABLES_MACACCESS, 164 ANA_TABLES_MACTINDX, 165 ANA_TABLES_VLANACCESS, 166 ANA_TABLES_VLANTIDX, 167 ANA_TABLES_ISDXACCESS, 168 ANA_TABLES_ISDXTIDX, 169 ANA_TABLES_ENTRYLIM, 170 ANA_TABLES_PTP_ID_HIGH, 171 ANA_TABLES_PTP_ID_LOW, 172 ANA_TABLES_STREAMACCESS, 173 ANA_TABLES_STREAMTIDX, 174 ANA_TABLES_SEQ_HISTORY, 175 ANA_TABLES_SEQ_MASK, 176 ANA_TABLES_SFID_MASK, 177 ANA_TABLES_SFIDACCESS, 178 ANA_TABLES_SFIDTIDX, 179 ANA_MSTI_STATE, 180 ANA_OAM_UPM_LM_CNT, 181 ANA_SG_ACCESS_CTRL, 182 ANA_SG_CONFIG_REG_1, 183 ANA_SG_CONFIG_REG_2, 184 ANA_SG_CONFIG_REG_3, 185 ANA_SG_CONFIG_REG_4, 186 ANA_SG_CONFIG_REG_5, 187 ANA_SG_GCL_GS_CONFIG, 188 ANA_SG_GCL_TI_CONFIG, 189 ANA_SG_STATUS_REG_1, 190 ANA_SG_STATUS_REG_2, 191 ANA_SG_STATUS_REG_3, 192 ANA_PORT_VLAN_CFG, 193 ANA_PORT_DROP_CFG, 194 ANA_PORT_QOS_CFG, 195 ANA_PORT_VCAP_CFG, 196 ANA_PORT_VCAP_S1_KEY_CFG, 197 ANA_PORT_VCAP_S2_CFG, 198 ANA_PORT_PCP_DEI_MAP, 199 ANA_PORT_CPU_FWD_CFG, 200 ANA_PORT_CPU_FWD_BPDU_CFG, 201 ANA_PORT_CPU_FWD_GARP_CFG, 202 ANA_PORT_CPU_FWD_CCM_CFG, 203 ANA_PORT_PORT_CFG, 204 ANA_PORT_POL_CFG, 205 ANA_PORT_PTP_CFG, 206 ANA_PORT_PTP_DLY1_CFG, 207 ANA_PORT_PTP_DLY2_CFG, 208 ANA_PORT_SFID_CFG, 209 ANA_PFC_PFC_CFG, 210 ANA_PFC_PFC_TIMER, 211 ANA_IPT_OAM_MEP_CFG, 212 ANA_IPT_IPT, 213 ANA_PPT_PPT, 214 ANA_FID_MAP_FID_MAP, 215 ANA_AGGR_CFG, 216 ANA_CPUQ_CFG, 217 ANA_CPUQ_CFG2, 218 ANA_CPUQ_8021_CFG, 219 ANA_DSCP_CFG, 220 ANA_DSCP_REWR_CFG, 221 ANA_VCAP_RNG_TYPE_CFG, 222 ANA_VCAP_RNG_VAL_CFG, 223 ANA_VRAP_CFG, 224 ANA_VRAP_HDR_DATA, 225 ANA_VRAP_HDR_MASK, 226 ANA_DISCARD_CFG, 227 ANA_FID_CFG, 228 ANA_POL_PIR_CFG, 229 ANA_POL_CIR_CFG, 230 ANA_POL_MODE_CFG, 231 ANA_POL_PIR_STATE, 232 ANA_POL_CIR_STATE, 233 ANA_POL_STATE, 234 ANA_POL_FLOWC, 235 ANA_POL_HYST, 236 ANA_POL_MISC_CFG, 237 QS_XTR_GRP_CFG = QS << TARGET_OFFSET, 238 QS_XTR_RD, 239 QS_XTR_FRM_PRUNING, 240 QS_XTR_FLUSH, 241 QS_XTR_DATA_PRESENT, 242 QS_XTR_CFG, 243 QS_INJ_GRP_CFG, 244 QS_INJ_WR, 245 QS_INJ_CTRL, 246 QS_INJ_STATUS, 247 QS_INJ_ERR, 248 QS_INH_DBG, 249 QSYS_PORT_MODE = QSYS << TARGET_OFFSET, 250 QSYS_SWITCH_PORT_MODE, 251 QSYS_STAT_CNT_CFG, 252 QSYS_EEE_CFG, 253 QSYS_EEE_THRES, 254 QSYS_IGR_NO_SHARING, 255 QSYS_EGR_NO_SHARING, 256 QSYS_SW_STATUS, 257 QSYS_EXT_CPU_CFG, 258 QSYS_PAD_CFG, 259 QSYS_CPU_GROUP_MAP, 260 QSYS_QMAP, 261 QSYS_ISDX_SGRP, 262 QSYS_TIMED_FRAME_ENTRY, 263 QSYS_TFRM_MISC, 264 QSYS_TFRM_PORT_DLY, 265 QSYS_TFRM_TIMER_CFG_1, 266 QSYS_TFRM_TIMER_CFG_2, 267 QSYS_TFRM_TIMER_CFG_3, 268 QSYS_TFRM_TIMER_CFG_4, 269 QSYS_TFRM_TIMER_CFG_5, 270 QSYS_TFRM_TIMER_CFG_6, 271 QSYS_TFRM_TIMER_CFG_7, 272 QSYS_TFRM_TIMER_CFG_8, 273 QSYS_RED_PROFILE, 274 QSYS_RES_QOS_MODE, 275 QSYS_RES_CFG, 276 QSYS_RES_STAT, 277 QSYS_EGR_DROP_MODE, 278 QSYS_EQ_CTRL, 279 QSYS_EVENTS_CORE, 280 QSYS_QMAXSDU_CFG_0, 281 QSYS_QMAXSDU_CFG_1, 282 QSYS_QMAXSDU_CFG_2, 283 QSYS_QMAXSDU_CFG_3, 284 QSYS_QMAXSDU_CFG_4, 285 QSYS_QMAXSDU_CFG_5, 286 QSYS_QMAXSDU_CFG_6, 287 QSYS_QMAXSDU_CFG_7, 288 QSYS_PREEMPTION_CFG, 289 QSYS_CIR_CFG, 290 QSYS_EIR_CFG, 291 QSYS_SE_CFG, 292 QSYS_SE_DWRR_CFG, 293 QSYS_SE_CONNECT, 294 QSYS_SE_DLB_SENSE, 295 QSYS_CIR_STATE, 296 QSYS_EIR_STATE, 297 QSYS_SE_STATE, 298 QSYS_HSCH_MISC_CFG, 299 QSYS_TAG_CONFIG, 300 QSYS_TAS_PARAM_CFG_CTRL, 301 QSYS_PORT_MAX_SDU, 302 QSYS_PARAM_CFG_REG_1, 303 QSYS_PARAM_CFG_REG_2, 304 QSYS_PARAM_CFG_REG_3, 305 QSYS_PARAM_CFG_REG_4, 306 QSYS_PARAM_CFG_REG_5, 307 QSYS_GCL_CFG_REG_1, 308 QSYS_GCL_CFG_REG_2, 309 QSYS_PARAM_STATUS_REG_1, 310 QSYS_PARAM_STATUS_REG_2, 311 QSYS_PARAM_STATUS_REG_3, 312 QSYS_PARAM_STATUS_REG_4, 313 QSYS_PARAM_STATUS_REG_5, 314 QSYS_PARAM_STATUS_REG_6, 315 QSYS_PARAM_STATUS_REG_7, 316 QSYS_PARAM_STATUS_REG_8, 317 QSYS_PARAM_STATUS_REG_9, 318 QSYS_GCL_STATUS_REG_1, 319 QSYS_GCL_STATUS_REG_2, 320 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET, 321 REW_TAG_CFG, 322 REW_PORT_CFG, 323 REW_DSCP_CFG, 324 REW_PCP_DEI_QOS_MAP_CFG, 325 REW_PTP_CFG, 326 REW_PTP_DLY1_CFG, 327 REW_RED_TAG_CFG, 328 REW_DSCP_REMAP_DP1_CFG, 329 REW_DSCP_REMAP_CFG, 330 REW_STAT_CFG, 331 REW_REW_STICKY, 332 REW_PPT, 333 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET, 334 SYS_COUNT_RX_UNICAST, 335 SYS_COUNT_RX_MULTICAST, 336 SYS_COUNT_RX_BROADCAST, 337 SYS_COUNT_RX_SHORTS, 338 SYS_COUNT_RX_FRAGMENTS, 339 SYS_COUNT_RX_JABBERS, 340 SYS_COUNT_RX_CRC_ALIGN_ERRS, 341 SYS_COUNT_RX_SYM_ERRS, 342 SYS_COUNT_RX_64, 343 SYS_COUNT_RX_65_127, 344 SYS_COUNT_RX_128_255, 345 SYS_COUNT_RX_256_1023, 346 SYS_COUNT_RX_1024_1526, 347 SYS_COUNT_RX_1527_MAX, 348 SYS_COUNT_RX_PAUSE, 349 SYS_COUNT_RX_CONTROL, 350 SYS_COUNT_RX_LONGS, 351 SYS_COUNT_RX_CLASSIFIED_DROPS, 352 SYS_COUNT_TX_OCTETS, 353 SYS_COUNT_TX_UNICAST, 354 SYS_COUNT_TX_MULTICAST, 355 SYS_COUNT_TX_BROADCAST, 356 SYS_COUNT_TX_COLLISION, 357 SYS_COUNT_TX_DROPS, 358 SYS_COUNT_TX_PAUSE, 359 SYS_COUNT_TX_64, 360 SYS_COUNT_TX_65_127, 361 SYS_COUNT_TX_128_511, 362 SYS_COUNT_TX_512_1023, 363 SYS_COUNT_TX_1024_1526, 364 SYS_COUNT_TX_1527_MAX, 365 SYS_COUNT_TX_AGING, 366 SYS_RESET_CFG, 367 SYS_SR_ETYPE_CFG, 368 SYS_VLAN_ETYPE_CFG, 369 SYS_PORT_MODE, 370 SYS_FRONT_PORT_MODE, 371 SYS_FRM_AGING, 372 SYS_STAT_CFG, 373 SYS_SW_STATUS, 374 SYS_MISC_CFG, 375 SYS_REW_MAC_HIGH_CFG, 376 SYS_REW_MAC_LOW_CFG, 377 SYS_TIMESTAMP_OFFSET, 378 SYS_CMID, 379 SYS_PAUSE_CFG, 380 SYS_PAUSE_TOT_CFG, 381 SYS_ATOP, 382 SYS_ATOP_TOT_CFG, 383 SYS_MAC_FC_CFG, 384 SYS_MMGT, 385 SYS_MMGT_FAST, 386 SYS_EVENTS_DIF, 387 SYS_EVENTS_CORE, 388 SYS_CNT, 389 SYS_PTP_STATUS, 390 SYS_PTP_TXSTAMP, 391 SYS_PTP_NXT, 392 SYS_PTP_CFG, 393 SYS_RAM_INIT, 394 SYS_CM_ADDR, 395 SYS_CM_DATA_WR, 396 SYS_CM_DATA_RD, 397 SYS_CM_OP, 398 SYS_CM_DATA, 399 PTP_PIN_CFG = PTP << TARGET_OFFSET, 400 PTP_PIN_TOD_SEC_MSB, 401 PTP_PIN_TOD_SEC_LSB, 402 PTP_PIN_TOD_NSEC, 403 PTP_PIN_WF_HIGH_PERIOD, 404 PTP_PIN_WF_LOW_PERIOD, 405 PTP_CFG_MISC, 406 PTP_CLK_CFG_ADJ_CFG, 407 PTP_CLK_CFG_ADJ_FREQ, 408 GCB_SOFT_RST = GCB << TARGET_OFFSET, 409 GCB_MIIM_MII_STATUS, 410 GCB_MIIM_MII_CMD, 411 GCB_MIIM_MII_DATA, 412 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, 413 DEV_PORT_MISC, 414 DEV_EVENTS, 415 DEV_EEE_CFG, 416 DEV_RX_PATH_DELAY, 417 DEV_TX_PATH_DELAY, 418 DEV_PTP_PREDICT_CFG, 419 DEV_MAC_ENA_CFG, 420 DEV_MAC_MODE_CFG, 421 DEV_MAC_MAXLEN_CFG, 422 DEV_MAC_TAGS_CFG, 423 DEV_MAC_ADV_CHK_CFG, 424 DEV_MAC_IFG_CFG, 425 DEV_MAC_HDX_CFG, 426 DEV_MAC_DBG_CFG, 427 DEV_MAC_FC_MAC_LOW_CFG, 428 DEV_MAC_FC_MAC_HIGH_CFG, 429 DEV_MAC_STICKY, 430 PCS1G_CFG, 431 PCS1G_MODE_CFG, 432 PCS1G_SD_CFG, 433 PCS1G_ANEG_CFG, 434 PCS1G_ANEG_NP_CFG, 435 PCS1G_LB_CFG, 436 PCS1G_DBG_CFG, 437 PCS1G_CDET_CFG, 438 PCS1G_ANEG_STATUS, 439 PCS1G_ANEG_NP_STATUS, 440 PCS1G_LINK_STATUS, 441 PCS1G_LINK_DOWN_CNT, 442 PCS1G_STICKY, 443 PCS1G_DEBUG_STATUS, 444 PCS1G_LPI_CFG, 445 PCS1G_LPI_WAKE_ERROR_CNT, 446 PCS1G_LPI_STATUS, 447 PCS1G_TSTPAT_MODE_CFG, 448 PCS1G_TSTPAT_STATUS, 449 DEV_PCS_FX100_CFG, 450 DEV_PCS_FX100_STATUS, 451 }; 452 453 enum ocelot_regfield { 454 ANA_ADVLEARN_VLAN_CHK, 455 ANA_ADVLEARN_LEARN_MIRROR, 456 ANA_ANEVENTS_FLOOD_DISCARD, 457 ANA_ANEVENTS_MSTI_DROP, 458 ANA_ANEVENTS_ACLKILL, 459 ANA_ANEVENTS_ACLUSED, 460 ANA_ANEVENTS_AUTOAGE, 461 ANA_ANEVENTS_VS2TTL1, 462 ANA_ANEVENTS_STORM_DROP, 463 ANA_ANEVENTS_LEARN_DROP, 464 ANA_ANEVENTS_AGED_ENTRY, 465 ANA_ANEVENTS_CPU_LEARN_FAILED, 466 ANA_ANEVENTS_AUTO_LEARN_FAILED, 467 ANA_ANEVENTS_LEARN_REMOVE, 468 ANA_ANEVENTS_AUTO_LEARNED, 469 ANA_ANEVENTS_AUTO_MOVED, 470 ANA_ANEVENTS_DROPPED, 471 ANA_ANEVENTS_CLASSIFIED_DROP, 472 ANA_ANEVENTS_CLASSIFIED_COPY, 473 ANA_ANEVENTS_VLAN_DISCARD, 474 ANA_ANEVENTS_FWD_DISCARD, 475 ANA_ANEVENTS_MULTICAST_FLOOD, 476 ANA_ANEVENTS_UNICAST_FLOOD, 477 ANA_ANEVENTS_DEST_KNOWN, 478 ANA_ANEVENTS_BUCKET3_MATCH, 479 ANA_ANEVENTS_BUCKET2_MATCH, 480 ANA_ANEVENTS_BUCKET1_MATCH, 481 ANA_ANEVENTS_BUCKET0_MATCH, 482 ANA_ANEVENTS_CPU_OPERATION, 483 ANA_ANEVENTS_DMAC_LOOKUP, 484 ANA_ANEVENTS_SMAC_LOOKUP, 485 ANA_ANEVENTS_SEQ_GEN_ERR_0, 486 ANA_ANEVENTS_SEQ_GEN_ERR_1, 487 ANA_TABLES_MACACCESS_B_DOM, 488 ANA_TABLES_MACTINDX_BUCKET, 489 ANA_TABLES_MACTINDX_M_INDEX, 490 QSYS_SWITCH_PORT_MODE_PORT_ENA, 491 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG, 492 QSYS_SWITCH_PORT_MODE_YEL_RSRVD, 493 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE, 494 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 495 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE, 496 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD, 497 QSYS_TIMED_FRAME_ENTRY_TFRM_FP, 498 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO, 499 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL, 500 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T, 501 SYS_PORT_MODE_DATA_WO_TS, 502 SYS_PORT_MODE_INCL_INJ_HDR, 503 SYS_PORT_MODE_INCL_XTR_HDR, 504 SYS_PORT_MODE_INCL_HDR_ERR, 505 SYS_RESET_CFG_CORE_ENA, 506 SYS_RESET_CFG_MEM_ENA, 507 SYS_RESET_CFG_MEM_INIT, 508 GCB_SOFT_RST_SWC_RST, 509 GCB_MIIM_MII_STATUS_PENDING, 510 GCB_MIIM_MII_STATUS_BUSY, 511 SYS_PAUSE_CFG_PAUSE_START, 512 SYS_PAUSE_CFG_PAUSE_STOP, 513 SYS_PAUSE_CFG_PAUSE_ENA, 514 REGFIELD_MAX 515 }; 516 517 enum { 518 /* VCAP_CORE_CFG */ 519 VCAP_CORE_UPDATE_CTRL, 520 VCAP_CORE_MV_CFG, 521 /* VCAP_CORE_CACHE */ 522 VCAP_CACHE_ENTRY_DAT, 523 VCAP_CACHE_MASK_DAT, 524 VCAP_CACHE_ACTION_DAT, 525 VCAP_CACHE_CNT_DAT, 526 VCAP_CACHE_TG_DAT, 527 /* VCAP_CONST */ 528 VCAP_CONST_VCAP_VER, 529 VCAP_CONST_ENTRY_WIDTH, 530 VCAP_CONST_ENTRY_CNT, 531 VCAP_CONST_ENTRY_SWCNT, 532 VCAP_CONST_ENTRY_TG_WIDTH, 533 VCAP_CONST_ACTION_DEF_CNT, 534 VCAP_CONST_ACTION_WIDTH, 535 VCAP_CONST_CNT_WIDTH, 536 VCAP_CONST_CORE_CNT, 537 VCAP_CONST_IF_CNT, 538 }; 539 540 enum ocelot_ptp_pins { 541 PTP_PIN_0, 542 PTP_PIN_1, 543 PTP_PIN_2, 544 PTP_PIN_3, 545 TOD_ACC_PIN 546 }; 547 548 struct ocelot_stat_layout { 549 u32 offset; 550 char name[ETH_GSTRING_LEN]; 551 }; 552 553 enum ocelot_tag_prefix { 554 OCELOT_TAG_PREFIX_DISABLED = 0, 555 OCELOT_TAG_PREFIX_NONE, 556 OCELOT_TAG_PREFIX_SHORT, 557 OCELOT_TAG_PREFIX_LONG, 558 }; 559 560 struct ocelot; 561 562 struct ocelot_ops { 563 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port); 564 int (*netdev_to_port)(struct net_device *dev); 565 int (*reset)(struct ocelot *ocelot); 566 u16 (*wm_enc)(u16 value); 567 u16 (*wm_dec)(u16 value); 568 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse); 569 }; 570 571 struct ocelot_vcap_block { 572 struct list_head rules; 573 int count; 574 int pol_lpr; 575 }; 576 577 struct ocelot_vlan { 578 bool valid; 579 u16 vid; 580 }; 581 582 enum ocelot_sb { 583 OCELOT_SB_BUF, 584 OCELOT_SB_REF, 585 OCELOT_SB_NUM, 586 }; 587 588 enum ocelot_sb_pool { 589 OCELOT_SB_POOL_ING, 590 OCELOT_SB_POOL_EGR, 591 OCELOT_SB_POOL_NUM, 592 }; 593 594 struct ocelot_port { 595 struct ocelot *ocelot; 596 597 struct regmap *target; 598 599 bool vlan_aware; 600 /* VLAN that untagged frames are classified to, on ingress */ 601 struct ocelot_vlan pvid_vlan; 602 /* The VLAN ID that will be transmitted as untagged, on egress */ 603 struct ocelot_vlan native_vlan; 604 605 u8 ptp_cmd; 606 struct sk_buff_head tx_skbs; 607 u8 ts_id; 608 spinlock_t ts_id_lock; 609 610 phy_interface_t phy_mode; 611 612 u8 *xmit_template; 613 }; 614 615 struct ocelot { 616 struct device *dev; 617 struct devlink *devlink; 618 struct devlink_port *devlink_ports; 619 620 const struct ocelot_ops *ops; 621 struct regmap *targets[TARGET_MAX]; 622 struct regmap_field *regfields[REGFIELD_MAX]; 623 const u32 *const *map; 624 const struct ocelot_stat_layout *stats_layout; 625 unsigned int num_stats; 626 627 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM]; 628 int packet_buffer_size; 629 int num_frame_refs; 630 int num_mact_rows; 631 632 struct net_device *hw_bridge_dev; 633 u16 bridge_mask; 634 u16 bridge_fwd_mask; 635 636 struct ocelot_port **ports; 637 638 u8 base_mac[ETH_ALEN]; 639 640 /* Keep track of the vlan port masks */ 641 u32 vlan_mask[VLAN_N_VID]; 642 643 /* Switches like VSC9959 have flooding per traffic class */ 644 int num_flooding_pgids; 645 646 /* In tables like ANA:PORT and the ANA:PGID:PGID mask, 647 * the CPU is located after the physical ports (at the 648 * num_phys_ports index). 649 */ 650 u8 num_phys_ports; 651 652 int npi; 653 654 enum ocelot_tag_prefix inj_prefix; 655 enum ocelot_tag_prefix xtr_prefix; 656 657 u32 *lags; 658 659 struct list_head multicast; 660 struct list_head pgids; 661 662 struct list_head dummy_rules; 663 struct ocelot_vcap_block block[3]; 664 struct vcap_props *vcap; 665 666 /* Workqueue to check statistics for overflow with its lock */ 667 struct mutex stats_lock; 668 u64 *stats; 669 struct delayed_work stats_work; 670 struct workqueue_struct *stats_queue; 671 672 struct workqueue_struct *owq; 673 674 u8 ptp:1; 675 struct ptp_clock *ptp_clock; 676 struct ptp_clock_info ptp_info; 677 struct hwtstamp_config hwtstamp_config; 678 /* Protects the PTP interface state */ 679 struct mutex ptp_lock; 680 /* Protects the PTP clock */ 681 spinlock_t ptp_clock_lock; 682 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; 683 }; 684 685 struct ocelot_policer { 686 u32 rate; /* kilobit per second */ 687 u32 burst; /* bytes */ 688 }; 689 690 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 691 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) 692 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) 693 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) 694 695 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 696 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) 697 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) 698 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) 699 700 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 701 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) 702 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) 703 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) 704 705 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) 706 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) 707 #define ocelot_fields_write(ocelot, id, reg, val) regmap_fields_write((ocelot)->regfields[(reg)], (id), (val)) 708 #define ocelot_fields_read(ocelot, id, reg, val) regmap_fields_read((ocelot)->regfields[(reg)], (id), (val)) 709 710 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \ 711 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 712 #define ocelot_target_read_gix(ocelot, target, reg, gi) \ 713 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi)) 714 #define ocelot_target_read_rix(ocelot, target, reg, ri) \ 715 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri)) 716 #define ocelot_target_read(ocelot, target, reg) \ 717 __ocelot_target_read_ix(ocelot, target, reg, 0) 718 719 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \ 720 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) 721 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \ 722 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi)) 723 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \ 724 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri)) 725 #define ocelot_target_write(ocelot, target, val, reg) \ 726 __ocelot_target_write_ix(ocelot, target, val, reg, 0) 727 728 /* I/O */ 729 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); 730 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); 731 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); 732 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); 733 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, 734 u32 offset); 735 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target, 736 u32 reg, u32 offset); 737 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target, 738 u32 val, u32 reg, u32 offset); 739 740 /* Hardware initialization */ 741 int ocelot_regfields_init(struct ocelot *ocelot, 742 const struct reg_field *const regfields); 743 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res); 744 int ocelot_init(struct ocelot *ocelot); 745 void ocelot_deinit(struct ocelot *ocelot); 746 void ocelot_init_port(struct ocelot *ocelot, int port); 747 void ocelot_deinit_port(struct ocelot *ocelot, int port); 748 749 /* DSA callbacks */ 750 void ocelot_port_enable(struct ocelot *ocelot, int port, 751 struct phy_device *phy); 752 void ocelot_port_disable(struct ocelot *ocelot, int port); 753 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); 754 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); 755 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset); 756 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 757 struct ethtool_ts_info *info); 758 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs); 759 void ocelot_adjust_link(struct ocelot *ocelot, int port, 760 struct phy_device *phydev); 761 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled); 762 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state); 763 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 764 struct net_device *bridge); 765 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 766 struct net_device *bridge); 767 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 768 dsa_fdb_dump_cb_t *cb, void *data); 769 int ocelot_fdb_add(struct ocelot *ocelot, int port, 770 const unsigned char *addr, u16 vid); 771 int ocelot_fdb_del(struct ocelot *ocelot, int port, 772 const unsigned char *addr, u16 vid); 773 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 774 bool untagged); 775 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 776 bool untagged); 777 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid); 778 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr); 779 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr); 780 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 781 struct sk_buff *clone); 782 void ocelot_get_txtstamp(struct ocelot *ocelot); 783 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu); 784 int ocelot_get_max_mtu(struct ocelot *ocelot, int port); 785 int ocelot_port_policer_add(struct ocelot *ocelot, int port, 786 struct ocelot_policer *pol); 787 int ocelot_port_policer_del(struct ocelot *ocelot, int port); 788 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port, 789 struct flow_cls_offload *f, bool ingress); 790 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port, 791 struct flow_cls_offload *f, bool ingress); 792 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port, 793 struct flow_cls_offload *f, bool ingress); 794 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 795 const struct switchdev_obj_port_mdb *mdb); 796 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 797 const struct switchdev_obj_port_mdb *mdb); 798 799 int ocelot_devlink_sb_register(struct ocelot *ocelot); 800 void ocelot_devlink_sb_unregister(struct ocelot *ocelot); 801 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index, 802 u16 pool_index, 803 struct devlink_sb_pool_info *pool_info); 804 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index, 805 u16 pool_index, u32 size, 806 enum devlink_sb_threshold_type threshold_type, 807 struct netlink_ext_ack *extack); 808 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port, 809 unsigned int sb_index, u16 pool_index, 810 u32 *p_threshold); 811 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port, 812 unsigned int sb_index, u16 pool_index, 813 u32 threshold, struct netlink_ext_ack *extack); 814 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port, 815 unsigned int sb_index, u16 tc_index, 816 enum devlink_sb_pool_type pool_type, 817 u16 *p_pool_index, u32 *p_threshold); 818 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port, 819 unsigned int sb_index, u16 tc_index, 820 enum devlink_sb_pool_type pool_type, 821 u16 pool_index, u32 threshold, 822 struct netlink_ext_ack *extack); 823 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index); 824 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index); 825 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port, 826 unsigned int sb_index, u16 pool_index, 827 u32 *p_cur, u32 *p_max); 828 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port, 829 unsigned int sb_index, u16 tc_index, 830 enum devlink_sb_pool_type pool_type, 831 u32 *p_cur, u32 *p_max); 832 833 #endif 834